1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/BasicBlock.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
30 #include "llvm/CodeGen/LiveVariables.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/MachineInstrBundle.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineMemOperand.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/ADT/DenseSet.h"
43 #include "llvm/ADT/SetOperations.h"
44 #include "llvm/ADT/SmallVector.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/raw_ostream.h"
51 struct MachineVerifier {
53 MachineVerifier(Pass *pass, const char *b) :
56 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
59 bool runOnMachineFunction(MachineFunction &MF);
63 const char *const OutFileName;
65 const MachineFunction *MF;
66 const TargetMachine *TM;
67 const TargetInstrInfo *TII;
68 const TargetRegisterInfo *TRI;
69 const MachineRegisterInfo *MRI;
73 typedef SmallVector<unsigned, 16> RegVector;
74 typedef SmallVector<const uint32_t*, 4> RegMaskVector;
75 typedef DenseSet<unsigned> RegSet;
76 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
77 typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet;
79 const MachineInstr *FirstTerminator;
80 BlockSet FunctionBlocks;
82 BitVector regsReserved;
84 RegVector regsDefined, regsDead, regsKilled;
85 RegMaskVector regMasks;
86 RegSet regsLiveInButUnused;
90 // Add Reg and any sub-registers to RV
91 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
93 if (TargetRegisterInfo::isPhysicalRegister(Reg))
94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
95 RV.push_back(*SubRegs);
99 // Is this MBB reachable from the MF entry point?
102 // Vregs that must be live in because they are used without being
103 // defined. Map value is the user.
106 // Regs killed in MBB. They may be defined again, and will then be in both
107 // regsKilled and regsLiveOut.
110 // Regs defined in MBB and live out. Note that vregs passing through may
111 // be live out without being mentioned here.
114 // Vregs that pass through MBB untouched. This set is disjoint from
115 // regsKilled and regsLiveOut.
118 // Vregs that must pass through MBB because they are needed by a successor
119 // block. This set is disjoint from regsLiveOut.
120 RegSet vregsRequired;
122 // Set versions of block's predecessor and successor lists.
123 BlockSet Preds, Succs;
125 BBInfo() : reachable(false) {}
127 // Add register to vregsPassed if it belongs there. Return true if
129 bool addPassed(unsigned Reg) {
130 if (!TargetRegisterInfo::isVirtualRegister(Reg))
132 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
134 return vregsPassed.insert(Reg).second;
137 // Same for a full set.
138 bool addPassed(const RegSet &RS) {
139 bool changed = false;
140 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
146 // Add register to vregsRequired if it belongs there. Return true if
148 bool addRequired(unsigned Reg) {
149 if (!TargetRegisterInfo::isVirtualRegister(Reg))
151 if (regsLiveOut.count(Reg))
153 return vregsRequired.insert(Reg).second;
156 // Same for a full set.
157 bool addRequired(const RegSet &RS) {
158 bool changed = false;
159 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
165 // Same for a full map.
166 bool addRequired(const RegMap &RM) {
167 bool changed = false;
168 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
169 if (addRequired(I->first))
174 // Live-out registers are either in regsLiveOut or vregsPassed.
175 bool isLiveOut(unsigned Reg) const {
176 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
180 // Extra register info per MBB.
181 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
183 bool isReserved(unsigned Reg) {
184 return Reg < regsReserved.size() && regsReserved.test(Reg);
187 bool isAllocatable(unsigned Reg) {
188 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
191 // Analysis information if available
192 LiveVariables *LiveVars;
193 LiveIntervals *LiveInts;
194 LiveStacks *LiveStks;
195 SlotIndexes *Indexes;
197 void visitMachineFunctionBefore();
198 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
199 void visitMachineBundleBefore(const MachineInstr *MI);
200 void visitMachineInstrBefore(const MachineInstr *MI);
201 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
202 void visitMachineInstrAfter(const MachineInstr *MI);
203 void visitMachineBundleAfter(const MachineInstr *MI);
204 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
205 void visitMachineFunctionAfter();
207 void report(const char *msg, const MachineFunction *MF);
208 void report(const char *msg, const MachineBasicBlock *MBB);
209 void report(const char *msg, const MachineInstr *MI);
210 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
211 void report(const char *msg, const MachineFunction *MF,
212 const LiveInterval &LI);
213 void report(const char *msg, const MachineBasicBlock *MBB,
214 const LiveInterval &LI);
216 void verifyInlineAsm(const MachineInstr *MI);
218 void checkLiveness(const MachineOperand *MO, unsigned MONum);
219 void markReachable(const MachineBasicBlock *MBB);
220 void calcRegsPassed();
221 void checkPHIOps(const MachineBasicBlock *MBB);
223 void calcRegsRequired();
224 void verifyLiveVariables();
225 void verifyLiveIntervals();
226 void verifyLiveInterval(const LiveInterval&);
227 void verifyLiveIntervalValue(const LiveInterval&, VNInfo*);
228 void verifyLiveIntervalSegment(const LiveInterval&,
229 LiveInterval::const_iterator);
232 struct MachineVerifierPass : public MachineFunctionPass {
233 static char ID; // Pass ID, replacement for typeid
234 const char *const Banner;
236 MachineVerifierPass(const char *b = 0)
237 : MachineFunctionPass(ID), Banner(b) {
238 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
241 void getAnalysisUsage(AnalysisUsage &AU) const {
242 AU.setPreservesAll();
243 MachineFunctionPass::getAnalysisUsage(AU);
246 bool runOnMachineFunction(MachineFunction &MF) {
247 MF.verify(this, Banner);
254 char MachineVerifierPass::ID = 0;
255 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
256 "Verify generated machine code", false, false)
258 FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
259 return new MachineVerifierPass(Banner);
262 void MachineFunction::verify(Pass *p, const char *Banner) const {
263 MachineVerifier(p, Banner)
264 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
267 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
268 raw_ostream *OutFile = 0;
270 std::string ErrorInfo;
271 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
272 raw_fd_ostream::F_Append);
273 if (!ErrorInfo.empty()) {
274 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
286 TM = &MF.getTarget();
287 TII = TM->getInstrInfo();
288 TRI = TM->getRegisterInfo();
289 MRI = &MF.getRegInfo();
296 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
297 // We don't want to verify LiveVariables if LiveIntervals is available.
299 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
300 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
301 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
304 visitMachineFunctionBefore();
305 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
307 visitMachineBasicBlockBefore(MFI);
308 // Keep track of the current bundle header.
309 const MachineInstr *CurBundle = 0;
310 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
311 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
312 if (MBBI->getParent() != MFI) {
313 report("Bad instruction parent pointer", MFI);
314 *OS << "Instruction: " << *MBBI;
317 // Is this a bundle header?
318 if (!MBBI->isInsideBundle()) {
320 visitMachineBundleAfter(CurBundle);
322 visitMachineBundleBefore(CurBundle);
323 } else if (!CurBundle)
324 report("No bundle header", MBBI);
325 visitMachineInstrBefore(MBBI);
326 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
327 visitMachineOperand(&MBBI->getOperand(I), I);
328 visitMachineInstrAfter(MBBI);
331 visitMachineBundleAfter(CurBundle);
332 visitMachineBasicBlockAfter(MFI);
334 visitMachineFunctionAfter();
338 else if (foundErrors)
339 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
347 regsLiveInButUnused.clear();
350 return false; // no changes
353 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
356 if (!foundErrors++) {
358 *OS << "# " << Banner << '\n';
359 MF->print(*OS, Indexes);
361 *OS << "*** Bad machine code: " << msg << " ***\n"
362 << "- function: " << MF->getName() << "\n";
365 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
367 report(msg, MBB->getParent());
368 *OS << "- basic block: BB#" << MBB->getNumber()
369 << ' ' << MBB->getName()
370 << " (" << (const void*)MBB << ')';
372 *OS << " [" << Indexes->getMBBStartIdx(MBB)
373 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
377 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
379 report(msg, MI->getParent());
380 *OS << "- instruction: ";
381 if (Indexes && Indexes->hasIndex(MI))
382 *OS << Indexes->getInstructionIndex(MI) << '\t';
386 void MachineVerifier::report(const char *msg,
387 const MachineOperand *MO, unsigned MONum) {
389 report(msg, MO->getParent());
390 *OS << "- operand " << MONum << ": ";
395 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
396 const LiveInterval &LI) {
398 *OS << "- interval: ";
399 if (TargetRegisterInfo::isVirtualRegister(LI.reg))
400 *OS << PrintReg(LI.reg, TRI);
402 *OS << PrintRegUnit(LI.reg, TRI);
403 *OS << ' ' << LI << '\n';
406 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
407 const LiveInterval &LI) {
409 *OS << "- interval: ";
410 if (TargetRegisterInfo::isVirtualRegister(LI.reg))
411 *OS << PrintReg(LI.reg, TRI);
413 *OS << PrintRegUnit(LI.reg, TRI);
414 *OS << ' ' << LI << '\n';
417 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
418 BBInfo &MInfo = MBBInfoMap[MBB];
419 if (!MInfo.reachable) {
420 MInfo.reachable = true;
421 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
422 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
427 void MachineVerifier::visitMachineFunctionBefore() {
428 lastIndex = SlotIndex();
429 regsReserved = MRI->getReservedRegs();
431 // A sub-register of a reserved register is also reserved
432 for (int Reg = regsReserved.find_first(); Reg>=0;
433 Reg = regsReserved.find_next(Reg)) {
434 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
435 // FIXME: This should probably be:
436 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
437 regsReserved.set(*SubRegs);
441 markReachable(&MF->front());
443 // Build a set of the basic blocks in the function.
444 FunctionBlocks.clear();
445 for (MachineFunction::const_iterator
446 I = MF->begin(), E = MF->end(); I != E; ++I) {
447 FunctionBlocks.insert(I);
448 BBInfo &MInfo = MBBInfoMap[I];
450 MInfo.Preds.insert(I->pred_begin(), I->pred_end());
451 if (MInfo.Preds.size() != I->pred_size())
452 report("MBB has duplicate entries in its predecessor list.", I);
454 MInfo.Succs.insert(I->succ_begin(), I->succ_end());
455 if (MInfo.Succs.size() != I->succ_size())
456 report("MBB has duplicate entries in its successor list.", I);
460 // Does iterator point to a and b as the first two elements?
461 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
462 const MachineBasicBlock *a, const MachineBasicBlock *b) {
471 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
475 // If this block has allocatable physical registers live-in, check that
476 // it is an entry block or landing pad.
477 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
478 LE = MBB->livein_end();
481 if (isAllocatable(reg) && !MBB->isLandingPad() &&
482 MBB != MBB->getParent()->begin()) {
483 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
488 // Count the number of landing pad successors.
489 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
490 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
491 E = MBB->succ_end(); I != E; ++I) {
492 if ((*I)->isLandingPad())
493 LandingPadSuccs.insert(*I);
494 if (!FunctionBlocks.count(*I))
495 report("MBB has successor that isn't part of the function.", MBB);
496 if (!MBBInfoMap[*I].Preds.count(MBB)) {
497 report("Inconsistent CFG", MBB);
498 *OS << "MBB is not in the predecessor list of the successor BB#"
499 << (*I)->getNumber() << ".\n";
503 // Check the predecessor list.
504 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
505 E = MBB->pred_end(); I != E; ++I) {
506 if (!FunctionBlocks.count(*I))
507 report("MBB has predecessor that isn't part of the function.", MBB);
508 if (!MBBInfoMap[*I].Succs.count(MBB)) {
509 report("Inconsistent CFG", MBB);
510 *OS << "MBB is not in the successor list of the predecessor BB#"
511 << (*I)->getNumber() << ".\n";
515 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
516 const BasicBlock *BB = MBB->getBasicBlock();
517 if (LandingPadSuccs.size() > 1 &&
519 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
520 BB && isa<SwitchInst>(BB->getTerminator())))
521 report("MBB has more than one landing pad successor", MBB);
523 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
524 MachineBasicBlock *TBB = 0, *FBB = 0;
525 SmallVector<MachineOperand, 4> Cond;
526 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
528 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
529 // check whether its answers match up with reality.
531 // Block falls through to its successor.
532 MachineFunction::const_iterator MBBI = MBB;
534 if (MBBI == MF->end()) {
535 // It's possible that the block legitimately ends with a noreturn
536 // call or an unreachable, in which case it won't actually fall
537 // out the bottom of the function.
538 } else if (MBB->succ_size() == LandingPadSuccs.size()) {
539 // It's possible that the block legitimately ends with a noreturn
540 // call or an unreachable, in which case it won't actuall fall
542 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
543 report("MBB exits via unconditional fall-through but doesn't have "
544 "exactly one CFG successor!", MBB);
545 } else if (!MBB->isSuccessor(MBBI)) {
546 report("MBB exits via unconditional fall-through but its successor "
547 "differs from its CFG successor!", MBB);
549 if (!MBB->empty() && getBundleStart(&MBB->back())->isBarrier() &&
550 !TII->isPredicated(getBundleStart(&MBB->back()))) {
551 report("MBB exits via unconditional fall-through but ends with a "
552 "barrier instruction!", MBB);
555 report("MBB exits via unconditional fall-through but has a condition!",
558 } else if (TBB && !FBB && Cond.empty()) {
559 // Block unconditionally branches somewhere.
560 if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
561 report("MBB exits via unconditional branch but doesn't have "
562 "exactly one CFG successor!", MBB);
563 } else if (!MBB->isSuccessor(TBB)) {
564 report("MBB exits via unconditional branch but the CFG "
565 "successor doesn't match the actual successor!", MBB);
568 report("MBB exits via unconditional branch but doesn't contain "
569 "any instructions!", MBB);
570 } else if (!getBundleStart(&MBB->back())->isBarrier()) {
571 report("MBB exits via unconditional branch but doesn't end with a "
572 "barrier instruction!", MBB);
573 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
574 report("MBB exits via unconditional branch but the branch isn't a "
575 "terminator instruction!", MBB);
577 } else if (TBB && !FBB && !Cond.empty()) {
578 // Block conditionally branches somewhere, otherwise falls through.
579 MachineFunction::const_iterator MBBI = MBB;
581 if (MBBI == MF->end()) {
582 report("MBB conditionally falls through out of function!", MBB);
583 } if (MBB->succ_size() == 1) {
584 // A conditional branch with only one successor is weird, but allowed.
586 report("MBB exits via conditional branch/fall-through but only has "
587 "one CFG successor!", MBB);
588 else if (TBB != *MBB->succ_begin())
589 report("MBB exits via conditional branch/fall-through but the CFG "
590 "successor don't match the actual successor!", MBB);
591 } else if (MBB->succ_size() != 2) {
592 report("MBB exits via conditional branch/fall-through but doesn't have "
593 "exactly two CFG successors!", MBB);
594 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
595 report("MBB exits via conditional branch/fall-through but the CFG "
596 "successors don't match the actual successors!", MBB);
599 report("MBB exits via conditional branch/fall-through but doesn't "
600 "contain any instructions!", MBB);
601 } else if (getBundleStart(&MBB->back())->isBarrier()) {
602 report("MBB exits via conditional branch/fall-through but ends with a "
603 "barrier instruction!", MBB);
604 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
605 report("MBB exits via conditional branch/fall-through but the branch "
606 "isn't a terminator instruction!", MBB);
608 } else if (TBB && FBB) {
609 // Block conditionally branches somewhere, otherwise branches
611 if (MBB->succ_size() == 1) {
612 // A conditional branch with only one successor is weird, but allowed.
614 report("MBB exits via conditional branch/branch through but only has "
615 "one CFG successor!", MBB);
616 else if (TBB != *MBB->succ_begin())
617 report("MBB exits via conditional branch/branch through but the CFG "
618 "successor don't match the actual successor!", MBB);
619 } else if (MBB->succ_size() != 2) {
620 report("MBB exits via conditional branch/branch but doesn't have "
621 "exactly two CFG successors!", MBB);
622 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
623 report("MBB exits via conditional branch/branch but the CFG "
624 "successors don't match the actual successors!", MBB);
627 report("MBB exits via conditional branch/branch but doesn't "
628 "contain any instructions!", MBB);
629 } else if (!getBundleStart(&MBB->back())->isBarrier()) {
630 report("MBB exits via conditional branch/branch but doesn't end with a "
631 "barrier instruction!", MBB);
632 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
633 report("MBB exits via conditional branch/branch but the branch "
634 "isn't a terminator instruction!", MBB);
637 report("MBB exits via conditinal branch/branch but there's no "
641 report("AnalyzeBranch returned invalid data!", MBB);
646 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
647 E = MBB->livein_end(); I != E; ++I) {
648 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
649 report("MBB live-in list contains non-physical register", MBB);
653 for (MCSubRegIterator SubRegs(*I, TRI); SubRegs.isValid(); ++SubRegs)
654 regsLive.insert(*SubRegs);
656 regsLiveInButUnused = regsLive;
658 const MachineFrameInfo *MFI = MF->getFrameInfo();
659 assert(MFI && "Function has no frame info");
660 BitVector PR = MFI->getPristineRegs(MBB);
661 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
663 for (MCSubRegIterator SubRegs(I, TRI); SubRegs.isValid(); ++SubRegs)
664 regsLive.insert(*SubRegs);
671 lastIndex = Indexes->getMBBStartIdx(MBB);
674 // This function gets called for all bundle headers, including normal
675 // stand-alone unbundled instructions.
676 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
677 if (Indexes && Indexes->hasIndex(MI)) {
678 SlotIndex idx = Indexes->getInstructionIndex(MI);
679 if (!(idx > lastIndex)) {
680 report("Instruction index out of order", MI);
681 *OS << "Last instruction was at " << lastIndex << '\n';
686 // Ensure non-terminators don't follow terminators.
687 // Ignore predicated terminators formed by if conversion.
688 // FIXME: If conversion shouldn't need to violate this rule.
689 if (MI->isTerminator() && !TII->isPredicated(MI)) {
690 if (!FirstTerminator)
691 FirstTerminator = MI;
692 } else if (FirstTerminator) {
693 report("Non-terminator instruction after the first terminator", MI);
694 *OS << "First terminator was:\t" << *FirstTerminator;
698 // The operands on an INLINEASM instruction must follow a template.
699 // Verify that the flag operands make sense.
700 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
701 // The first two operands on INLINEASM are the asm string and global flags.
702 if (MI->getNumOperands() < 2) {
703 report("Too few operands on inline asm", MI);
706 if (!MI->getOperand(0).isSymbol())
707 report("Asm string must be an external symbol", MI);
708 if (!MI->getOperand(1).isImm())
709 report("Asm flags must be an immediate", MI);
710 // Allowed flags are Extra_HasSideEffects = 1, and Extra_IsAlignStack = 2.
711 if (!isUInt<2>(MI->getOperand(1).getImm()))
712 report("Unknown asm flags", &MI->getOperand(1), 1);
714 assert(InlineAsm::MIOp_FirstOperand == 2 && "Asm format changed");
716 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
718 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
719 const MachineOperand &MO = MI->getOperand(OpNo);
720 // There may be implicit ops after the fixed operands.
723 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
726 if (OpNo > MI->getNumOperands())
727 report("Missing operands in last group", MI);
729 // An optional MDNode follows the groups.
730 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
733 // All trailing operands must be implicit registers.
734 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
735 const MachineOperand &MO = MI->getOperand(OpNo);
736 if (!MO.isReg() || !MO.isImplicit())
737 report("Expected implicit register after groups", &MO, OpNo);
741 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
742 const MCInstrDesc &MCID = MI->getDesc();
743 if (MI->getNumOperands() < MCID.getNumOperands()) {
744 report("Too few operands", MI);
745 *OS << MCID.getNumOperands() << " operands expected, but "
746 << MI->getNumExplicitOperands() << " given.\n";
749 // Check the tied operands.
750 if (MI->isInlineAsm())
753 // Check the MachineMemOperands for basic consistency.
754 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
755 E = MI->memoperands_end(); I != E; ++I) {
756 if ((*I)->isLoad() && !MI->mayLoad())
757 report("Missing mayLoad flag", MI);
758 if ((*I)->isStore() && !MI->mayStore())
759 report("Missing mayStore flag", MI);
762 // Debug values must not have a slot index.
763 // Other instructions must have one, unless they are inside a bundle.
765 bool mapped = !LiveInts->isNotInMIMap(MI);
766 if (MI->isDebugValue()) {
768 report("Debug instruction has a slot index", MI);
769 } else if (MI->isInsideBundle()) {
771 report("Instruction inside bundle has a slot index", MI);
774 report("Missing slot index", MI);
779 if (!TII->verifyInstruction(MI, ErrorInfo))
780 report(ErrorInfo.data(), MI);
784 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
785 const MachineInstr *MI = MO->getParent();
786 const MCInstrDesc &MCID = MI->getDesc();
788 // The first MCID.NumDefs operands must be explicit register defines
789 if (MONum < MCID.getNumDefs()) {
790 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
792 report("Explicit definition must be a register", MO, MONum);
793 else if (!MO->isDef() && !MCOI.isOptionalDef())
794 report("Explicit definition marked as use", MO, MONum);
795 else if (MO->isImplicit())
796 report("Explicit definition marked as implicit", MO, MONum);
797 } else if (MONum < MCID.getNumOperands()) {
798 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
799 // Don't check if it's the last operand in a variadic instruction. See,
800 // e.g., LDM_RET in the arm back end.
802 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
803 if (MO->isDef() && !MCOI.isOptionalDef())
804 report("Explicit operand marked as def", MO, MONum);
805 if (MO->isImplicit())
806 report("Explicit operand marked as implicit", MO, MONum);
809 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
812 report("Tied use must be a register", MO, MONum);
813 else if (!MO->isTied())
814 report("Operand should be tied", MO, MONum);
815 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
816 report("Tied def doesn't match MCInstrDesc", MO, MONum);
817 } else if (MO->isReg() && MO->isTied())
818 report("Explicit operand should not be tied", MO, MONum);
820 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
821 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
822 report("Extra explicit operand on non-variadic instruction", MO, MONum);
825 switch (MO->getType()) {
826 case MachineOperand::MO_Register: {
827 const unsigned Reg = MO->getReg();
830 if (MRI->tracksLiveness() && !MI->isDebugValue())
831 checkLiveness(MO, MONum);
833 // Verify the consistency of tied operands.
835 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
836 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
837 if (!OtherMO.isReg())
838 report("Must be tied to a register", MO, MONum);
839 if (!OtherMO.isTied())
840 report("Missing tie flags on tied operand", MO, MONum);
841 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
842 report("Inconsistent tie links", MO, MONum);
843 if (MONum < MCID.getNumDefs()) {
844 if (OtherIdx < MCID.getNumOperands()) {
845 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
846 report("Explicit def tied to explicit use without tie constraint",
849 if (!OtherMO.isImplicit())
850 report("Explicit def should be tied to implicit use", MO, MONum);
855 // Verify two-address constraints after leaving SSA form.
857 if (!MRI->isSSA() && MO->isUse() &&
858 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
859 Reg != MI->getOperand(DefIdx).getReg())
860 report("Two-address instruction operands must be identical", MO, MONum);
862 // Check register classes.
863 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
864 unsigned SubIdx = MO->getSubReg();
866 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
868 report("Illegal subregister index for physical register", MO, MONum);
871 if (const TargetRegisterClass *DRC =
872 TII->getRegClass(MCID, MONum, TRI, *MF)) {
873 if (!DRC->contains(Reg)) {
874 report("Illegal physical register for instruction", MO, MONum);
875 *OS << TRI->getName(Reg) << " is not a "
876 << DRC->getName() << " register.\n";
881 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
883 const TargetRegisterClass *SRC =
884 TRI->getSubClassWithSubReg(RC, SubIdx);
886 report("Invalid subregister index for virtual register", MO, MONum);
887 *OS << "Register class " << RC->getName()
888 << " does not support subreg index " << SubIdx << "\n";
892 report("Invalid register class for subregister index", MO, MONum);
893 *OS << "Register class " << RC->getName()
894 << " does not fully support subreg index " << SubIdx << "\n";
898 if (const TargetRegisterClass *DRC =
899 TII->getRegClass(MCID, MONum, TRI, *MF)) {
901 const TargetRegisterClass *SuperRC =
902 TRI->getLargestLegalSuperClass(RC);
904 report("No largest legal super class exists.", MO, MONum);
907 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
909 report("No matching super-reg register class.", MO, MONum);
913 if (!RC->hasSuperClassEq(DRC)) {
914 report("Illegal virtual register for instruction", MO, MONum);
915 *OS << "Expected a " << DRC->getName() << " register, but got a "
916 << RC->getName() << " register\n";
924 case MachineOperand::MO_RegisterMask:
925 regMasks.push_back(MO->getRegMask());
928 case MachineOperand::MO_MachineBasicBlock:
929 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
930 report("PHI operand is not in the CFG", MO, MONum);
933 case MachineOperand::MO_FrameIndex:
934 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
935 LiveInts && !LiveInts->isNotInMIMap(MI)) {
936 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
937 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
938 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
939 report("Instruction loads from dead spill slot", MO, MONum);
940 *OS << "Live stack: " << LI << '\n';
942 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
943 report("Instruction stores to dead spill slot", MO, MONum);
944 *OS << "Live stack: " << LI << '\n';
954 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
955 const MachineInstr *MI = MO->getParent();
956 const unsigned Reg = MO->getReg();
958 // Both use and def operands can read a register.
959 if (MO->readsReg()) {
960 regsLiveInButUnused.erase(Reg);
963 addRegWithSubRegs(regsKilled, Reg);
965 // Check that LiveVars knows this kill.
966 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
968 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
969 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
970 report("Kill missing from LiveVariables", MO, MONum);
973 // Check LiveInts liveness and kill.
974 if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
975 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
976 // Check the cached regunit intervals.
977 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
978 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
979 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(*Units)) {
980 LiveRangeQuery LRQ(*LI, UseIdx);
981 if (!LRQ.valueIn()) {
982 report("No live range at use", MO, MONum);
983 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
984 << ' ' << *LI << '\n';
986 if (MO->isKill() && !LRQ.isKill()) {
987 report("Live range continues after kill flag", MO, MONum);
988 *OS << PrintRegUnit(*Units, TRI) << ' ' << *LI << '\n';
994 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
995 if (LiveInts->hasInterval(Reg)) {
996 // This is a virtual register interval.
997 const LiveInterval &LI = LiveInts->getInterval(Reg);
998 LiveRangeQuery LRQ(LI, UseIdx);
999 if (!LRQ.valueIn()) {
1000 report("No live range at use", MO, MONum);
1001 *OS << UseIdx << " is not live in " << LI << '\n';
1003 // Check for extra kill flags.
1004 // Note that we allow missing kill flags for now.
1005 if (MO->isKill() && !LRQ.isKill()) {
1006 report("Live range continues after kill flag", MO, MONum);
1007 *OS << "Live range: " << LI << '\n';
1010 report("Virtual register has no live interval", MO, MONum);
1015 // Use of a dead register.
1016 if (!regsLive.count(Reg)) {
1017 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1018 // Reserved registers may be used even when 'dead'.
1019 if (!isReserved(Reg))
1020 report("Using an undefined physical register", MO, MONum);
1021 } else if (MRI->def_empty(Reg)) {
1022 report("Reading virtual register without a def", MO, MONum);
1024 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1025 // We don't know which virtual registers are live in, so only complain
1026 // if vreg was killed in this MBB. Otherwise keep track of vregs that
1027 // must be live in. PHI instructions are handled separately.
1028 if (MInfo.regsKilled.count(Reg))
1029 report("Using a killed virtual register", MO, MONum);
1030 else if (!MI->isPHI())
1031 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1037 // Register defined.
1038 // TODO: verify that earlyclobber ops are not used.
1040 addRegWithSubRegs(regsDead, Reg);
1042 addRegWithSubRegs(regsDefined, Reg);
1045 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1046 llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
1047 report("Multiple virtual register defs in SSA form", MO, MONum);
1049 // Check LiveInts for a live range, but only for virtual registers.
1050 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
1051 !LiveInts->isNotInMIMap(MI)) {
1052 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
1053 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1054 if (LiveInts->hasInterval(Reg)) {
1055 const LiveInterval &LI = LiveInts->getInterval(Reg);
1056 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
1057 assert(VNI && "NULL valno is not allowed");
1058 if (VNI->def != DefIdx) {
1059 report("Inconsistent valno->def", MO, MONum);
1060 *OS << "Valno " << VNI->id << " is not defined at "
1061 << DefIdx << " in " << LI << '\n';
1064 report("No live range at def", MO, MONum);
1065 *OS << DefIdx << " is not live in " << LI << '\n';
1068 report("Virtual register has no Live interval", MO, MONum);
1074 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
1077 // This function gets called after visiting all instructions in a bundle. The
1078 // argument points to the bundle header.
1079 // Normal stand-alone instructions are also considered 'bundles', and this
1080 // function is called for all of them.
1081 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1082 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1083 set_union(MInfo.regsKilled, regsKilled);
1084 set_subtract(regsLive, regsKilled); regsKilled.clear();
1085 // Kill any masked registers.
1086 while (!regMasks.empty()) {
1087 const uint32_t *Mask = regMasks.pop_back_val();
1088 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1089 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
1090 MachineOperand::clobbersPhysReg(Mask, *I))
1091 regsDead.push_back(*I);
1093 set_subtract(regsLive, regsDead); regsDead.clear();
1094 set_union(regsLive, regsDefined); regsDefined.clear();
1098 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1099 MBBInfoMap[MBB].regsLiveOut = regsLive;
1103 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1104 if (!(stop > lastIndex)) {
1105 report("Block ends before last instruction index", MBB);
1106 *OS << "Block ends at " << stop
1107 << " last instruction was at " << lastIndex << '\n';
1113 // Calculate the largest possible vregsPassed sets. These are the registers that
1114 // can pass through an MBB live, but may not be live every time. It is assumed
1115 // that all vregsPassed sets are empty before the call.
1116 void MachineVerifier::calcRegsPassed() {
1117 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1118 // have any vregsPassed.
1119 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1120 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1121 MFI != MFE; ++MFI) {
1122 const MachineBasicBlock &MBB(*MFI);
1123 BBInfo &MInfo = MBBInfoMap[&MBB];
1124 if (!MInfo.reachable)
1126 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
1127 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1128 BBInfo &SInfo = MBBInfoMap[*SuI];
1129 if (SInfo.addPassed(MInfo.regsLiveOut))
1134 // Iteratively push vregsPassed to successors. This will converge to the same
1135 // final state regardless of DenseSet iteration order.
1136 while (!todo.empty()) {
1137 const MachineBasicBlock *MBB = *todo.begin();
1139 BBInfo &MInfo = MBBInfoMap[MBB];
1140 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
1141 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
1144 BBInfo &SInfo = MBBInfoMap[*SuI];
1145 if (SInfo.addPassed(MInfo.vregsPassed))
1151 // Calculate the set of virtual registers that must be passed through each basic
1152 // block in order to satisfy the requirements of successor blocks. This is very
1153 // similar to calcRegsPassed, only backwards.
1154 void MachineVerifier::calcRegsRequired() {
1155 // First push live-in regs to predecessors' vregsRequired.
1156 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1157 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1158 MFI != MFE; ++MFI) {
1159 const MachineBasicBlock &MBB(*MFI);
1160 BBInfo &MInfo = MBBInfoMap[&MBB];
1161 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
1162 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
1163 BBInfo &PInfo = MBBInfoMap[*PrI];
1164 if (PInfo.addRequired(MInfo.vregsLiveIn))
1169 // Iteratively push vregsRequired to predecessors. This will converge to the
1170 // same final state regardless of DenseSet iteration order.
1171 while (!todo.empty()) {
1172 const MachineBasicBlock *MBB = *todo.begin();
1174 BBInfo &MInfo = MBBInfoMap[MBB];
1175 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1176 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1179 BBInfo &SInfo = MBBInfoMap[*PrI];
1180 if (SInfo.addRequired(MInfo.vregsRequired))
1186 // Check PHI instructions at the beginning of MBB. It is assumed that
1187 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1188 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1189 SmallPtrSet<const MachineBasicBlock*, 8> seen;
1190 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
1191 BBI != BBE && BBI->isPHI(); ++BBI) {
1194 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
1195 unsigned Reg = BBI->getOperand(i).getReg();
1196 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
1197 if (!Pre->isSuccessor(MBB))
1200 BBInfo &PrInfo = MBBInfoMap[Pre];
1201 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1202 report("PHI operand is not live-out from predecessor",
1203 &BBI->getOperand(i), i);
1206 // Did we see all predecessors?
1207 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1208 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1209 if (!seen.count(*PrI)) {
1210 report("Missing PHI operand", BBI);
1211 *OS << "BB#" << (*PrI)->getNumber()
1212 << " is a predecessor according to the CFG.\n";
1218 void MachineVerifier::visitMachineFunctionAfter() {
1221 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1222 MFI != MFE; ++MFI) {
1223 BBInfo &MInfo = MBBInfoMap[MFI];
1225 // Skip unreachable MBBs.
1226 if (!MInfo.reachable)
1232 // Now check liveness info if available
1235 // Check for killed virtual registers that should be live out.
1236 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1237 MFI != MFE; ++MFI) {
1238 BBInfo &MInfo = MBBInfoMap[MFI];
1239 for (RegSet::iterator
1240 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1242 if (MInfo.regsKilled.count(*I)) {
1243 report("Virtual register killed in block, but needed live out.", MFI);
1244 *OS << "Virtual register " << PrintReg(*I)
1245 << " is used after the block.\n";
1250 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1251 for (RegSet::iterator
1252 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1254 report("Virtual register def doesn't dominate all uses.",
1255 MRI->getVRegDef(*I));
1259 verifyLiveVariables();
1261 verifyLiveIntervals();
1264 void MachineVerifier::verifyLiveVariables() {
1265 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1266 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1267 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1268 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1269 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1270 MFI != MFE; ++MFI) {
1271 BBInfo &MInfo = MBBInfoMap[MFI];
1273 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1274 if (MInfo.vregsRequired.count(Reg)) {
1275 if (!VI.AliveBlocks.test(MFI->getNumber())) {
1276 report("LiveVariables: Block missing from AliveBlocks", MFI);
1277 *OS << "Virtual register " << PrintReg(Reg)
1278 << " must be live through the block.\n";
1281 if (VI.AliveBlocks.test(MFI->getNumber())) {
1282 report("LiveVariables: Block should not be in AliveBlocks", MFI);
1283 *OS << "Virtual register " << PrintReg(Reg)
1284 << " is not needed live through the block.\n";
1291 void MachineVerifier::verifyLiveIntervals() {
1292 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1293 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1294 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1296 // Spilling and splitting may leave unused registers around. Skip them.
1297 if (MRI->reg_nodbg_empty(Reg))
1300 if (!LiveInts->hasInterval(Reg)) {
1301 report("Missing live interval for virtual register", MF);
1302 *OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
1306 const LiveInterval &LI = LiveInts->getInterval(Reg);
1307 assert(Reg == LI.reg && "Invalid reg to interval mapping");
1308 verifyLiveInterval(LI);
1311 // Verify all the cached regunit intervals.
1312 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1313 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(i))
1314 verifyLiveInterval(*LI);
1317 void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
1319 if (VNI->isUnused())
1322 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
1325 report("Valno not live at def and not marked unused", MF, LI);
1326 *OS << "Valno #" << VNI->id << '\n';
1330 if (DefVNI != VNI) {
1331 report("Live range at def has different valno", MF, LI);
1332 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1333 << " where valno #" << DefVNI->id << " is live\n";
1337 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1339 report("Invalid definition index", MF, LI);
1340 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1341 << " in " << LI << '\n';
1345 if (VNI->isPHIDef()) {
1346 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1347 report("PHIDef value is not defined at MBB start", MBB, LI);
1348 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1349 << ", not at the beginning of BB#" << MBB->getNumber() << '\n';
1355 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1357 report("No instruction at def index", MBB, LI);
1358 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1362 bool hasDef = false;
1363 bool isEarlyClobber = false;
1364 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1365 if (!MOI->isReg() || !MOI->isDef())
1367 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1368 if (MOI->getReg() != LI.reg)
1371 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1372 !TRI->hasRegUnit(MOI->getReg(), LI.reg))
1376 if (MOI->isEarlyClobber())
1377 isEarlyClobber = true;
1381 report("Defining instruction does not modify register", MI);
1382 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1385 // Early clobber defs begin at USE slots, but other defs must begin at
1387 if (isEarlyClobber) {
1388 if (!VNI->def.isEarlyClobber()) {
1389 report("Early clobber def must be at an early-clobber slot", MBB, LI);
1390 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1392 } else if (!VNI->def.isRegister()) {
1393 report("Non-PHI, non-early clobber def must be at a register slot",
1395 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1400 MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
1401 LiveInterval::const_iterator I) {
1402 const VNInfo *VNI = I->valno;
1403 assert(VNI && "Live range has no valno");
1405 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1406 report("Foreign valno in live range", MF, LI);
1407 *OS << *I << " has a bad valno\n";
1410 if (VNI->isUnused()) {
1411 report("Live range valno is marked unused", MF, LI);
1415 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
1417 report("Bad start of live segment, no basic block", MF, LI);
1421 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1422 if (I->start != MBBStartIdx && I->start != VNI->def) {
1423 report("Live segment must begin at MBB entry or valno def", MBB, LI);
1427 const MachineBasicBlock *EndMBB =
1428 LiveInts->getMBBFromIndex(I->end.getPrevSlot());
1430 report("Bad end of live segment, no basic block", MF, LI);
1435 // No more checks for live-out segments.
1436 if (I->end == LiveInts->getMBBEndIdx(EndMBB))
1439 // RegUnit intervals are allowed dead phis.
1440 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) && VNI->isPHIDef() &&
1441 I->start == VNI->def && I->end == VNI->def.getDeadSlot())
1444 // The live segment is ending inside EndMBB
1445 const MachineInstr *MI =
1446 LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
1448 report("Live segment doesn't end at a valid instruction", EndMBB, LI);
1453 // The block slot must refer to a basic block boundary.
1454 if (I->end.isBlock()) {
1455 report("Live segment ends at B slot of an instruction", EndMBB, LI);
1459 if (I->end.isDead()) {
1460 // Segment ends on the dead slot.
1461 // That means there must be a dead def.
1462 if (!SlotIndex::isSameInstr(I->start, I->end)) {
1463 report("Live segment ending at dead slot spans instructions", EndMBB, LI);
1468 // A live segment can only end at an early-clobber slot if it is being
1469 // redefined by an early-clobber def.
1470 if (I->end.isEarlyClobber()) {
1471 if (I+1 == LI.end() || (I+1)->start != I->end) {
1472 report("Live segment ending at early clobber slot must be "
1473 "redefined by an EC def in the same instruction", EndMBB, LI);
1478 // The following checks only apply to virtual registers. Physreg liveness
1479 // is too weird to check.
1480 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1481 // A live range can end with either a redefinition, a kill flag on a
1482 // use, or a dead flag on a def.
1483 bool hasRead = false;
1484 bool hasDeadDef = false;
1485 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1486 if (!MOI->isReg() || MOI->getReg() != LI.reg)
1488 if (MOI->readsReg())
1490 if (MOI->isDef() && MOI->isDead())
1494 if (I->end.isDead()) {
1496 report("Instruction doesn't have a dead def operand", MI);
1498 *OS << " in " << LI << '\n';
1502 report("Instruction ending live range doesn't read the register", MI);
1503 *OS << *I << " in " << LI << '\n';
1508 // Now check all the basic blocks in this live segment.
1509 MachineFunction::const_iterator MFI = MBB;
1510 // Is this live range the beginning of a non-PHIDef VN?
1511 if (I->start == VNI->def && !VNI->isPHIDef()) {
1512 // Not live-in to any blocks.
1519 assert(LiveInts->isLiveInToMBB(LI, MFI));
1520 // We don't know how to track physregs into a landing pad.
1521 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) &&
1522 MFI->isLandingPad()) {
1523 if (&*MFI == EndMBB)
1529 // Is VNI a PHI-def in the current block?
1530 bool IsPHI = VNI->isPHIDef() &&
1531 VNI->def == LiveInts->getMBBStartIdx(MFI);
1533 // Check that VNI is live-out of all predecessors.
1534 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1535 PE = MFI->pred_end(); PI != PE; ++PI) {
1536 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1537 const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
1539 // All predecessors must have a live-out value.
1541 report("Register not marked live out of predecessor", *PI, LI);
1542 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1543 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1548 // Only PHI-defs can take different predecessor values.
1549 if (!IsPHI && PVNI != VNI) {
1550 report("Different value live out of predecessor", *PI, LI);
1551 *OS << "Valno #" << PVNI->id << " live out of BB#"
1552 << (*PI)->getNumber() << '@' << PEnd
1553 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1554 << '@' << LiveInts->getMBBStartIdx(MFI) << '\n';
1557 if (&*MFI == EndMBB)
1563 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
1564 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
1566 verifyLiveIntervalValue(LI, *I);
1568 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I)
1569 verifyLiveIntervalSegment(LI, I);
1571 // Check the LI only has one connected component.
1572 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1573 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1574 unsigned NumComp = ConEQ.Classify(&LI);
1576 report("Multiple connected components in live interval", MF, LI);
1577 for (unsigned comp = 0; comp != NumComp; ++comp) {
1578 *OS << comp << ": valnos";
1579 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1580 E = LI.vni_end(); I!=E; ++I)
1581 if (comp == ConEQ.getEqClass(*I))
1582 *OS << ' ' << (*I)->id;