1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Instructions.h"
27 #include "llvm/Function.h"
28 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/LiveStackAnalysis.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/ADT/DenseSet.h"
41 #include "llvm/ADT/SetOperations.h"
42 #include "llvm/ADT/SmallVector.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/raw_ostream.h"
49 struct MachineVerifier {
51 MachineVerifier(Pass *pass, const char *b) :
54 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
57 bool runOnMachineFunction(MachineFunction &MF);
61 const char *const OutFileName;
63 const MachineFunction *MF;
64 const TargetMachine *TM;
65 const TargetRegisterInfo *TRI;
66 const MachineRegisterInfo *MRI;
70 typedef SmallVector<unsigned, 16> RegVector;
71 typedef DenseSet<unsigned> RegSet;
72 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
74 BitVector regsReserved;
76 RegVector regsDefined, regsDead, regsKilled;
77 RegSet regsLiveInButUnused;
81 // Add Reg and any sub-registers to RV
82 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
84 if (TargetRegisterInfo::isPhysicalRegister(Reg))
85 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
90 // Is this MBB reachable from the MF entry point?
93 // Vregs that must be live in because they are used without being
94 // defined. Map value is the user.
97 // Regs killed in MBB. They may be defined again, and will then be in both
98 // regsKilled and regsLiveOut.
101 // Regs defined in MBB and live out. Note that vregs passing through may
102 // be live out without being mentioned here.
105 // Vregs that pass through MBB untouched. This set is disjoint from
106 // regsKilled and regsLiveOut.
109 // Vregs that must pass through MBB because they are needed by a successor
110 // block. This set is disjoint from regsLiveOut.
111 RegSet vregsRequired;
113 BBInfo() : reachable(false) {}
115 // Add register to vregsPassed if it belongs there. Return true if
117 bool addPassed(unsigned Reg) {
118 if (!TargetRegisterInfo::isVirtualRegister(Reg))
120 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
122 return vregsPassed.insert(Reg).second;
125 // Same for a full set.
126 bool addPassed(const RegSet &RS) {
127 bool changed = false;
128 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
134 // Add register to vregsRequired if it belongs there. Return true if
136 bool addRequired(unsigned Reg) {
137 if (!TargetRegisterInfo::isVirtualRegister(Reg))
139 if (regsLiveOut.count(Reg))
141 return vregsRequired.insert(Reg).second;
144 // Same for a full set.
145 bool addRequired(const RegSet &RS) {
146 bool changed = false;
147 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
153 // Same for a full map.
154 bool addRequired(const RegMap &RM) {
155 bool changed = false;
156 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
157 if (addRequired(I->first))
162 // Live-out registers are either in regsLiveOut or vregsPassed.
163 bool isLiveOut(unsigned Reg) const {
164 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
168 // Extra register info per MBB.
169 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
171 bool isReserved(unsigned Reg) {
172 return Reg < regsReserved.size() && regsReserved.test(Reg);
175 // Analysis information if available
176 LiveVariables *LiveVars;
177 LiveIntervals *LiveInts;
178 LiveStacks *LiveStks;
179 SlotIndexes *Indexes;
181 void visitMachineFunctionBefore();
182 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
183 void visitMachineInstrBefore(const MachineInstr *MI);
184 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
185 void visitMachineInstrAfter(const MachineInstr *MI);
186 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
187 void visitMachineFunctionAfter();
189 void report(const char *msg, const MachineFunction *MF);
190 void report(const char *msg, const MachineBasicBlock *MBB);
191 void report(const char *msg, const MachineInstr *MI);
192 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
194 void markReachable(const MachineBasicBlock *MBB);
195 void calcRegsPassed();
196 void checkPHIOps(const MachineBasicBlock *MBB);
198 void calcRegsRequired();
199 void verifyLiveVariables();
200 void verifyLiveIntervals();
203 struct MachineVerifierPass : public MachineFunctionPass {
204 static char ID; // Pass ID, replacement for typeid
205 const char *const Banner;
207 MachineVerifierPass(const char *b = 0)
208 : MachineFunctionPass(ID), Banner(b) {
209 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
212 void getAnalysisUsage(AnalysisUsage &AU) const {
213 AU.setPreservesAll();
214 MachineFunctionPass::getAnalysisUsage(AU);
217 bool runOnMachineFunction(MachineFunction &MF) {
218 MF.verify(this, Banner);
225 char MachineVerifierPass::ID = 0;
226 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
227 "Verify generated machine code", false, false)
229 FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
230 return new MachineVerifierPass(Banner);
233 void MachineFunction::verify(Pass *p, const char *Banner) const {
234 MachineVerifier(p, Banner)
235 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
238 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
239 raw_ostream *OutFile = 0;
241 std::string ErrorInfo;
242 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
243 raw_fd_ostream::F_Append);
244 if (!ErrorInfo.empty()) {
245 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
257 TM = &MF.getTarget();
258 TRI = TM->getRegisterInfo();
259 MRI = &MF.getRegInfo();
266 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
267 // We don't want to verify LiveVariables if LiveIntervals is available.
269 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
270 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
271 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
274 visitMachineFunctionBefore();
275 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
277 visitMachineBasicBlockBefore(MFI);
278 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
279 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
280 if (MBBI->getParent() != MFI) {
281 report("Bad instruction parent pointer", MFI);
282 *OS << "Instruction: " << *MBBI;
285 visitMachineInstrBefore(MBBI);
286 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
287 visitMachineOperand(&MBBI->getOperand(I), I);
288 visitMachineInstrAfter(MBBI);
290 visitMachineBasicBlockAfter(MFI);
292 visitMachineFunctionAfter();
296 else if (foundErrors)
297 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
304 regsLiveInButUnused.clear();
307 return false; // no changes
310 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
313 if (!foundErrors++) {
315 *OS << "# " << Banner << '\n';
316 MF->print(*OS, Indexes);
318 *OS << "*** Bad machine code: " << msg << " ***\n"
319 << "- function: " << MF->getFunction()->getNameStr() << "\n";
322 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
324 report(msg, MBB->getParent());
325 *OS << "- basic block: " << MBB->getName()
327 << " (BB#" << MBB->getNumber() << ")";
329 *OS << " [" << Indexes->getMBBStartIdx(MBB)
330 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
334 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
336 report(msg, MI->getParent());
337 *OS << "- instruction: ";
338 if (Indexes && Indexes->hasIndex(MI))
339 *OS << Indexes->getInstructionIndex(MI) << '\t';
343 void MachineVerifier::report(const char *msg,
344 const MachineOperand *MO, unsigned MONum) {
346 report(msg, MO->getParent());
347 *OS << "- operand " << MONum << ": ";
352 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
353 BBInfo &MInfo = MBBInfoMap[MBB];
354 if (!MInfo.reachable) {
355 MInfo.reachable = true;
356 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
357 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
362 void MachineVerifier::visitMachineFunctionBefore() {
363 lastIndex = SlotIndex();
364 regsReserved = TRI->getReservedRegs(*MF);
366 // A sub-register of a reserved register is also reserved
367 for (int Reg = regsReserved.find_first(); Reg>=0;
368 Reg = regsReserved.find_next(Reg)) {
369 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
370 // FIXME: This should probably be:
371 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
372 regsReserved.set(*Sub);
375 markReachable(&MF->front());
378 // Does iterator point to a and b as the first two elements?
379 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
380 const MachineBasicBlock *a, const MachineBasicBlock *b) {
389 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
390 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
392 // Count the number of landing pad successors.
393 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
394 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
395 E = MBB->succ_end(); I != E; ++I) {
396 if ((*I)->isLandingPad())
397 LandingPadSuccs.insert(*I);
400 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
401 const BasicBlock *BB = MBB->getBasicBlock();
402 if (LandingPadSuccs.size() > 1 &&
404 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
405 BB && isa<SwitchInst>(BB->getTerminator())))
406 report("MBB has more than one landing pad successor", MBB);
408 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
409 MachineBasicBlock *TBB = 0, *FBB = 0;
410 SmallVector<MachineOperand, 4> Cond;
411 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
413 // If the block branches directly to a landing pad successor, pretend that
414 // the landing pad is a normal block.
415 LandingPadSuccs.erase(TBB);
416 LandingPadSuccs.erase(FBB);
418 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
419 // check whether its answers match up with reality.
421 // Block falls through to its successor.
422 MachineFunction::const_iterator MBBI = MBB;
424 if (MBBI == MF->end()) {
425 // It's possible that the block legitimately ends with a noreturn
426 // call or an unreachable, in which case it won't actually fall
427 // out the bottom of the function.
428 } else if (MBB->succ_size() == LandingPadSuccs.size()) {
429 // It's possible that the block legitimately ends with a noreturn
430 // call or an unreachable, in which case it won't actuall fall
432 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
433 report("MBB exits via unconditional fall-through but doesn't have "
434 "exactly one CFG successor!", MBB);
435 } else if (!MBB->isSuccessor(MBBI)) {
436 report("MBB exits via unconditional fall-through but its successor "
437 "differs from its CFG successor!", MBB);
439 if (!MBB->empty() && MBB->back().getDesc().isBarrier() &&
440 !TII->isPredicated(&MBB->back())) {
441 report("MBB exits via unconditional fall-through but ends with a "
442 "barrier instruction!", MBB);
445 report("MBB exits via unconditional fall-through but has a condition!",
448 } else if (TBB && !FBB && Cond.empty()) {
449 // Block unconditionally branches somewhere.
450 if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
451 report("MBB exits via unconditional branch but doesn't have "
452 "exactly one CFG successor!", MBB);
453 } else if (!MBB->isSuccessor(TBB)) {
454 report("MBB exits via unconditional branch but the CFG "
455 "successor doesn't match the actual successor!", MBB);
458 report("MBB exits via unconditional branch but doesn't contain "
459 "any instructions!", MBB);
460 } else if (!MBB->back().getDesc().isBarrier()) {
461 report("MBB exits via unconditional branch but doesn't end with a "
462 "barrier instruction!", MBB);
463 } else if (!MBB->back().getDesc().isTerminator()) {
464 report("MBB exits via unconditional branch but the branch isn't a "
465 "terminator instruction!", MBB);
467 } else if (TBB && !FBB && !Cond.empty()) {
468 // Block conditionally branches somewhere, otherwise falls through.
469 MachineFunction::const_iterator MBBI = MBB;
471 if (MBBI == MF->end()) {
472 report("MBB conditionally falls through out of function!", MBB);
473 } if (MBB->succ_size() != 2) {
474 report("MBB exits via conditional branch/fall-through but doesn't have "
475 "exactly two CFG successors!", MBB);
476 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
477 report("MBB exits via conditional branch/fall-through but the CFG "
478 "successors don't match the actual successors!", MBB);
481 report("MBB exits via conditional branch/fall-through but doesn't "
482 "contain any instructions!", MBB);
483 } else if (MBB->back().getDesc().isBarrier()) {
484 report("MBB exits via conditional branch/fall-through but ends with a "
485 "barrier instruction!", MBB);
486 } else if (!MBB->back().getDesc().isTerminator()) {
487 report("MBB exits via conditional branch/fall-through but the branch "
488 "isn't a terminator instruction!", MBB);
490 } else if (TBB && FBB) {
491 // Block conditionally branches somewhere, otherwise branches
493 if (MBB->succ_size() != 2) {
494 report("MBB exits via conditional branch/branch but doesn't have "
495 "exactly two CFG successors!", MBB);
496 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
497 report("MBB exits via conditional branch/branch but the CFG "
498 "successors don't match the actual successors!", MBB);
501 report("MBB exits via conditional branch/branch but doesn't "
502 "contain any instructions!", MBB);
503 } else if (!MBB->back().getDesc().isBarrier()) {
504 report("MBB exits via conditional branch/branch but doesn't end with a "
505 "barrier instruction!", MBB);
506 } else if (!MBB->back().getDesc().isTerminator()) {
507 report("MBB exits via conditional branch/branch but the branch "
508 "isn't a terminator instruction!", MBB);
511 report("MBB exits via conditinal branch/branch but there's no "
515 report("AnalyzeBranch returned invalid data!", MBB);
520 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
521 E = MBB->livein_end(); I != E; ++I) {
522 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
523 report("MBB live-in list contains non-physical register", MBB);
527 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
530 regsLiveInButUnused = regsLive;
532 const MachineFrameInfo *MFI = MF->getFrameInfo();
533 assert(MFI && "Function has no frame info");
534 BitVector PR = MFI->getPristineRegs(MBB);
535 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
537 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
545 lastIndex = Indexes->getMBBStartIdx(MBB);
548 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
549 const TargetInstrDesc &TI = MI->getDesc();
550 if (MI->getNumOperands() < TI.getNumOperands()) {
551 report("Too few operands", MI);
552 *OS << TI.getNumOperands() << " operands expected, but "
553 << MI->getNumExplicitOperands() << " given.\n";
556 // Check the MachineMemOperands for basic consistency.
557 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
558 E = MI->memoperands_end(); I != E; ++I) {
559 if ((*I)->isLoad() && !TI.mayLoad())
560 report("Missing mayLoad flag", MI);
561 if ((*I)->isStore() && !TI.mayStore())
562 report("Missing mayStore flag", MI);
565 // Debug values must not have a slot index.
566 // Other instructions must have one.
568 bool mapped = !LiveInts->isNotInMIMap(MI);
569 if (MI->isDebugValue()) {
571 report("Debug instruction has a slot index", MI);
574 report("Missing slot index", MI);
581 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
582 const MachineInstr *MI = MO->getParent();
583 const TargetInstrDesc &TI = MI->getDesc();
584 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
586 // The first TI.NumDefs operands must be explicit register defines
587 if (MONum < TI.getNumDefs()) {
589 report("Explicit definition must be a register", MO, MONum);
590 else if (!MO->isDef())
591 report("Explicit definition marked as use", MO, MONum);
592 else if (MO->isImplicit())
593 report("Explicit definition marked as implicit", MO, MONum);
594 } else if (MONum < TI.getNumOperands()) {
595 // Don't check if it's the last operand in a variadic instruction. See,
596 // e.g., LDM_RET in the arm back end.
597 if (MO->isReg() && !(TI.isVariadic() && MONum == TI.getNumOperands()-1)) {
598 if (MO->isDef() && !TOI.isOptionalDef())
599 report("Explicit operand marked as def", MO, MONum);
600 if (MO->isImplicit())
601 report("Explicit operand marked as implicit", MO, MONum);
604 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
605 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
606 report("Extra explicit operand on non-variadic instruction", MO, MONum);
609 switch (MO->getType()) {
610 case MachineOperand::MO_Register: {
611 const unsigned Reg = MO->getReg();
615 // Check Live Variables.
616 if (MI->isDebugValue()) {
617 // Liveness checks are not valid for debug values.
618 } else if (MO->isUse() && !MO->isUndef()) {
619 regsLiveInButUnused.erase(Reg);
623 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
624 // A two-addr use counts as a kill if use and def are the same.
625 unsigned DefReg = MI->getOperand(defIdx).getReg();
628 else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
629 report("Two-address instruction operands must be identical",
633 isKill = MO->isKill();
636 addRegWithSubRegs(regsKilled, Reg);
638 // Check that LiveVars knows this kill.
639 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
641 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
642 if (std::find(VI.Kills.begin(),
643 VI.Kills.end(), MI) == VI.Kills.end())
644 report("Kill missing from LiveVariables", MO, MONum);
647 // Check LiveInts liveness and kill.
648 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
649 LiveInts && !LiveInts->isNotInMIMap(MI)) {
650 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getUseIndex();
651 if (LiveInts->hasInterval(Reg)) {
652 const LiveInterval &LI = LiveInts->getInterval(Reg);
653 if (!LI.liveAt(UseIdx)) {
654 report("No live range at use", MO, MONum);
655 *OS << UseIdx << " is not live in " << LI << '\n';
657 // Check for extra kill flags.
658 // Note that we allow missing kill flags for now.
659 if (MO->isKill() && !LI.killedAt(UseIdx.getDefIndex())) {
660 report("Live range continues after kill flag", MO, MONum);
661 *OS << "Live range: " << LI << '\n';
664 report("Virtual register has no Live interval", MO, MONum);
668 // Use of a dead register.
669 if (!regsLive.count(Reg)) {
670 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
671 // Reserved registers may be used even when 'dead'.
672 if (!isReserved(Reg))
673 report("Using an undefined physical register", MO, MONum);
675 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
676 // We don't know which virtual registers are live in, so only complain
677 // if vreg was killed in this MBB. Otherwise keep track of vregs that
678 // must be live in. PHI instructions are handled separately.
679 if (MInfo.regsKilled.count(Reg))
680 report("Using a killed virtual register", MO, MONum);
681 else if (!MI->isPHI())
682 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
685 } else if (MO->isDef()) {
687 // TODO: verify that earlyclobber ops are not used.
689 addRegWithSubRegs(regsDead, Reg);
691 addRegWithSubRegs(regsDefined, Reg);
693 // Check LiveInts for a live range, but only for virtual registers.
694 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
695 !LiveInts->isNotInMIMap(MI)) {
696 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getDefIndex();
697 if (LiveInts->hasInterval(Reg)) {
698 const LiveInterval &LI = LiveInts->getInterval(Reg);
699 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
700 assert(VNI && "NULL valno is not allowed");
701 if (VNI->def != DefIdx && !MO->isEarlyClobber()) {
702 report("Inconsistent valno->def", MO, MONum);
703 *OS << "Valno " << VNI->id << " is not defined at "
704 << DefIdx << " in " << LI << '\n';
707 report("No live range at def", MO, MONum);
708 *OS << DefIdx << " is not live in " << LI << '\n';
711 report("Virtual register has no Live interval", MO, MONum);
716 // Check register classes.
717 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
718 unsigned SubIdx = MO->getSubReg();
720 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
723 unsigned s = TRI->getSubReg(Reg, SubIdx);
725 report("Invalid subregister index for physical register",
731 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
732 if (!DRC->contains(sr)) {
733 report("Illegal physical register for instruction", MO, MONum);
734 *OS << TRI->getName(sr) << " is not a "
735 << DRC->getName() << " register.\n";
740 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
742 const TargetRegisterClass *SRC = RC->getSubRegisterRegClass(SubIdx);
744 report("Invalid subregister index for virtual register", MO, MONum);
745 *OS << "Register class " << RC->getName()
746 << " does not support subreg index " << SubIdx << "\n";
751 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
752 if (RC != DRC && !RC->hasSuperClass(DRC)) {
753 report("Illegal virtual register for instruction", MO, MONum);
754 *OS << "Expected a " << DRC->getName() << " register, but got a "
755 << RC->getName() << " register\n";
763 case MachineOperand::MO_MachineBasicBlock:
764 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
765 report("PHI operand is not in the CFG", MO, MONum);
768 case MachineOperand::MO_FrameIndex:
769 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
770 LiveInts && !LiveInts->isNotInMIMap(MI)) {
771 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
772 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
773 if (TI.mayLoad() && !LI.liveAt(Idx.getUseIndex())) {
774 report("Instruction loads from dead spill slot", MO, MONum);
775 *OS << "Live stack: " << LI << '\n';
777 if (TI.mayStore() && !LI.liveAt(Idx.getDefIndex())) {
778 report("Instruction stores to dead spill slot", MO, MONum);
779 *OS << "Live stack: " << LI << '\n';
789 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
790 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
791 set_union(MInfo.regsKilled, regsKilled);
792 set_subtract(regsLive, regsKilled); regsKilled.clear();
793 set_subtract(regsLive, regsDead); regsDead.clear();
794 set_union(regsLive, regsDefined); regsDefined.clear();
796 if (Indexes && Indexes->hasIndex(MI)) {
797 SlotIndex idx = Indexes->getInstructionIndex(MI);
798 if (!(idx > lastIndex)) {
799 report("Instruction index out of order", MI);
800 *OS << "Last instruction was at " << lastIndex << '\n';
807 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
808 MBBInfoMap[MBB].regsLiveOut = regsLive;
812 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
813 if (!(stop > lastIndex)) {
814 report("Block ends before last instruction index", MBB);
815 *OS << "Block ends at " << stop
816 << " last instruction was at " << lastIndex << '\n';
822 // Calculate the largest possible vregsPassed sets. These are the registers that
823 // can pass through an MBB live, but may not be live every time. It is assumed
824 // that all vregsPassed sets are empty before the call.
825 void MachineVerifier::calcRegsPassed() {
826 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
827 // have any vregsPassed.
828 DenseSet<const MachineBasicBlock*> todo;
829 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
831 const MachineBasicBlock &MBB(*MFI);
832 BBInfo &MInfo = MBBInfoMap[&MBB];
833 if (!MInfo.reachable)
835 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
836 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
837 BBInfo &SInfo = MBBInfoMap[*SuI];
838 if (SInfo.addPassed(MInfo.regsLiveOut))
843 // Iteratively push vregsPassed to successors. This will converge to the same
844 // final state regardless of DenseSet iteration order.
845 while (!todo.empty()) {
846 const MachineBasicBlock *MBB = *todo.begin();
848 BBInfo &MInfo = MBBInfoMap[MBB];
849 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
850 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
853 BBInfo &SInfo = MBBInfoMap[*SuI];
854 if (SInfo.addPassed(MInfo.vregsPassed))
860 // Calculate the set of virtual registers that must be passed through each basic
861 // block in order to satisfy the requirements of successor blocks. This is very
862 // similar to calcRegsPassed, only backwards.
863 void MachineVerifier::calcRegsRequired() {
864 // First push live-in regs to predecessors' vregsRequired.
865 DenseSet<const MachineBasicBlock*> todo;
866 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
868 const MachineBasicBlock &MBB(*MFI);
869 BBInfo &MInfo = MBBInfoMap[&MBB];
870 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
871 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
872 BBInfo &PInfo = MBBInfoMap[*PrI];
873 if (PInfo.addRequired(MInfo.vregsLiveIn))
878 // Iteratively push vregsRequired to predecessors. This will converge to the
879 // same final state regardless of DenseSet iteration order.
880 while (!todo.empty()) {
881 const MachineBasicBlock *MBB = *todo.begin();
883 BBInfo &MInfo = MBBInfoMap[MBB];
884 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
885 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
888 BBInfo &SInfo = MBBInfoMap[*PrI];
889 if (SInfo.addRequired(MInfo.vregsRequired))
895 // Check PHI instructions at the beginning of MBB. It is assumed that
896 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
897 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
898 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
899 BBI != BBE && BBI->isPHI(); ++BBI) {
900 DenseSet<const MachineBasicBlock*> seen;
902 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
903 unsigned Reg = BBI->getOperand(i).getReg();
904 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
905 if (!Pre->isSuccessor(MBB))
908 BBInfo &PrInfo = MBBInfoMap[Pre];
909 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
910 report("PHI operand is not live-out from predecessor",
911 &BBI->getOperand(i), i);
914 // Did we see all predecessors?
915 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
916 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
917 if (!seen.count(*PrI)) {
918 report("Missing PHI operand", BBI);
919 *OS << "BB#" << (*PrI)->getNumber()
920 << " is a predecessor according to the CFG.\n";
926 void MachineVerifier::visitMachineFunctionAfter() {
929 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
931 BBInfo &MInfo = MBBInfoMap[MFI];
933 // Skip unreachable MBBs.
934 if (!MInfo.reachable)
940 // Now check liveness info if available
941 if (LiveVars || LiveInts)
944 verifyLiveVariables();
946 verifyLiveIntervals();
949 void MachineVerifier::verifyLiveVariables() {
950 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
951 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
952 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
953 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
954 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
956 BBInfo &MInfo = MBBInfoMap[MFI];
958 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
959 if (MInfo.vregsRequired.count(Reg)) {
960 if (!VI.AliveBlocks.test(MFI->getNumber())) {
961 report("LiveVariables: Block missing from AliveBlocks", MFI);
962 *OS << "Virtual register " << PrintReg(Reg)
963 << " must be live through the block.\n";
966 if (VI.AliveBlocks.test(MFI->getNumber())) {
967 report("LiveVariables: Block should not be in AliveBlocks", MFI);
968 *OS << "Virtual register " << PrintReg(Reg)
969 << " is not needed live through the block.\n";
976 void MachineVerifier::verifyLiveIntervals() {
977 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
978 for (LiveIntervals::const_iterator LVI = LiveInts->begin(),
979 LVE = LiveInts->end(); LVI != LVE; ++LVI) {
980 const LiveInterval &LI = *LVI->second;
982 // Spilling and splitting may leave unused registers around. Skip them.
983 if (MRI->use_empty(LI.reg))
986 // Physical registers have much weirdness going on, mostly from coalescing.
987 // We should probably fix it, but for now just ignore them.
988 if (TargetRegisterInfo::isPhysicalRegister(LI.reg))
991 assert(LVI->first == LI.reg && "Invalid reg to interval mapping");
993 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
996 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
999 if (!VNI->isUnused()) {
1000 report("Valno not live at def and not marked unused", MF);
1001 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1006 if (VNI->isUnused())
1009 if (DefVNI != VNI) {
1010 report("Live range at def has different valno", MF);
1011 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1012 << " where valno #" << DefVNI->id << " is live in " << LI << '\n';
1016 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1018 report("Invalid definition index", MF);
1019 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1020 << " in " << LI << '\n';
1024 if (VNI->isPHIDef()) {
1025 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1026 report("PHIDef value is not defined at MBB start", MF);
1027 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1028 << ", not at the beginning of BB#" << MBB->getNumber()
1029 << " in " << LI << '\n';
1033 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1035 report("No instruction at def index", MF);
1036 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1037 << " in " << LI << '\n';
1038 } else if (!MI->modifiesRegister(LI.reg, TRI)) {
1039 report("Defining instruction does not modify register", MI);
1040 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1043 bool isEarlyClobber = false;
1045 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1046 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1047 if (MOI->isReg() && MOI->getReg() == LI.reg && MOI->isDef() &&
1048 MOI->isEarlyClobber()) {
1049 isEarlyClobber = true;
1055 // Early clobber defs begin at USE slots, but other defs must begin at
1057 if (isEarlyClobber) {
1058 if (!VNI->def.isUse()) {
1059 report("Early clobber def must be at a USE slot", MF);
1060 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1061 << " in " << LI << '\n';
1063 } else if (!VNI->def.isDef()) {
1064 report("Non-PHI, non-early clobber def must be at a DEF slot", MF);
1065 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1066 << " in " << LI << '\n';
1071 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
1072 const VNInfo *VNI = I->valno;
1073 assert(VNI && "Live range has no valno");
1075 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1076 report("Foreign valno in live range", MF);
1078 *OS << " has a valno not in " << LI << '\n';
1081 if (VNI->isUnused()) {
1082 report("Live range valno is marked unused", MF);
1084 *OS << " in " << LI << '\n';
1087 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
1089 report("Bad start of live segment, no basic block", MF);
1091 *OS << " in " << LI << '\n';
1094 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1095 if (I->start != MBBStartIdx && I->start != VNI->def) {
1096 report("Live segment must begin at MBB entry or valno def", MBB);
1098 *OS << " in " << LI << '\n' << "Basic block starts at "
1099 << MBBStartIdx << '\n';
1102 const MachineBasicBlock *EndMBB =
1103 LiveInts->getMBBFromIndex(I->end.getPrevSlot());
1105 report("Bad end of live segment, no basic block", MF);
1107 *OS << " in " << LI << '\n';
1110 if (I->end != LiveInts->getMBBEndIdx(EndMBB)) {
1111 // The live segment is ending inside EndMBB
1112 const MachineInstr *MI =
1113 LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
1115 report("Live segment doesn't end at a valid instruction", EndMBB);
1117 *OS << " in " << LI << '\n' << "Basic block starts at "
1118 << MBBStartIdx << '\n';
1119 } else if (TargetRegisterInfo::isVirtualRegister(LI.reg) &&
1120 !MI->readsVirtualRegister(LI.reg)) {
1121 // A live range can end with either a redefinition, a kill flag on a
1122 // use, or a dead flag on a def.
1123 // FIXME: Should we check for each of these?
1124 bool hasDeadDef = false;
1125 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1126 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1127 if (MOI->isReg() && MOI->getReg() == LI.reg && MOI->isDef() && MOI->isDead()) {
1134 report("Instruction killing live segment neither defines nor reads "
1137 *OS << " in " << LI << '\n';
1142 // Now check all the basic blocks in this live segment.
1143 MachineFunction::const_iterator MFI = MBB;
1144 // Is this live range the beginning of a non-PHIDef VN?
1145 if (I->start == VNI->def && !VNI->isPHIDef()) {
1146 // Not live-in to any blocks.
1153 assert(LiveInts->isLiveInToMBB(LI, MFI));
1154 // We don't know how to track physregs into a landing pad.
1155 if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
1156 MFI->isLandingPad()) {
1157 if (&*MFI == EndMBB)
1162 // Check that VNI is live-out of all predecessors.
1163 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1164 PE = MFI->pred_end(); PI != PE; ++PI) {
1165 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI).getPrevSlot();
1166 const VNInfo *PVNI = LI.getVNInfoAt(PEnd);
1168 if (VNI->isPHIDef() && VNI->def == LiveInts->getMBBStartIdx(MFI)) {
1169 if (PVNI && !PVNI->hasPHIKill()) {
1170 report("Value live out of predecessor doesn't have PHIKill", MF);
1171 *OS << "Valno #" << PVNI->id << " live out of BB#"
1172 << (*PI)->getNumber() << '@' << PEnd
1173 << " doesn't have PHIKill, but Valno #" << VNI->id
1174 << " is PHIDef and defined at the beginning of BB#"
1175 << MFI->getNumber() << '@' << LiveInts->getMBBStartIdx(MFI)
1176 << " in " << LI << '\n';
1182 report("Register not marked live out of predecessor", *PI);
1183 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1184 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live at "
1185 << PEnd << " in " << LI << '\n';
1190 report("Different value live out of predecessor", *PI);
1191 *OS << "Valno #" << PVNI->id << " live out of BB#"
1192 << (*PI)->getNumber() << '@' << PEnd
1193 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1194 << '@' << LiveInts->getMBBStartIdx(MFI) << " in " << LI << '\n';
1197 if (&*MFI == EndMBB)
1203 // Check the LI only has one connected component.
1204 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1205 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1206 unsigned NumComp = ConEQ.Classify(&LI);
1208 report("Multiple connected components in live interval", MF);
1209 *OS << NumComp << " components in " << LI << '\n';
1210 for (unsigned comp = 0; comp != NumComp; ++comp) {
1211 *OS << comp << ": valnos";
1212 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1213 E = LI.vni_end(); I!=E; ++I)
1214 if (comp == ConEQ.getEqClass(*I))
1215 *OS << ' ' << (*I)->id;