1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/ADT/DenseSet.h"
27 #include "llvm/ADT/SetOperations.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Function.h"
30 #include "llvm/CodeGen/LiveVariables.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
45 struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
46 static char ID; // Pass ID, replacement for typeid
48 MachineVerifier(bool allowDoubleDefs = false) :
49 MachineFunctionPass(&ID),
50 allowVirtDoubleDefs(allowDoubleDefs),
51 allowPhysDoubleDefs(allowDoubleDefs),
52 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
55 void getAnalysisUsage(AnalysisUsage &AU) const {
57 MachineFunctionPass::getAnalysisUsage(AU);
60 bool runOnMachineFunction(MachineFunction &MF);
62 const bool allowVirtDoubleDefs;
63 const bool allowPhysDoubleDefs;
65 const char *const OutFileName;
67 const MachineFunction *MF;
68 const TargetMachine *TM;
69 const TargetRegisterInfo *TRI;
70 const MachineRegisterInfo *MRI;
74 typedef SmallVector<unsigned, 16> RegVector;
75 typedef DenseSet<unsigned> RegSet;
76 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
78 BitVector regsReserved;
80 RegVector regsDefined, regsDead, regsKilled;
81 RegSet regsLiveInButUnused;
83 // Add Reg and any sub-registers to RV
84 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
86 if (TargetRegisterInfo::isPhysicalRegister(Reg))
87 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
92 // Is this MBB reachable from the MF entry point?
95 // Vregs that must be live in because they are used without being
96 // defined. Map value is the user.
99 // Vregs that must be dead in because they are defined without being
100 // killed first. Map value is the defining instruction.
103 // Regs killed in MBB. They may be defined again, and will then be in both
104 // regsKilled and regsLiveOut.
107 // Regs defined in MBB and live out. Note that vregs passing through may
108 // be live out without being mentioned here.
111 // Vregs that pass through MBB untouched. This set is disjoint from
112 // regsKilled and regsLiveOut.
115 BBInfo() : reachable(false) {}
117 // Add register to vregsPassed if it belongs there. Return true if
119 bool addPassed(unsigned Reg) {
120 if (!TargetRegisterInfo::isVirtualRegister(Reg))
122 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
124 return vregsPassed.insert(Reg).second;
127 // Same for a full set.
128 bool addPassed(const RegSet &RS) {
129 bool changed = false;
130 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
136 // Live-out registers are either in regsLiveOut or vregsPassed.
137 bool isLiveOut(unsigned Reg) const {
138 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
142 // Extra register info per MBB.
143 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
145 bool isReserved(unsigned Reg) {
146 return Reg < regsReserved.size() && regsReserved.test(Reg);
149 void visitMachineFunctionBefore();
150 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
151 void visitMachineInstrBefore(const MachineInstr *MI);
152 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
153 void visitMachineInstrAfter(const MachineInstr *MI);
154 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
155 void visitMachineFunctionAfter();
157 void report(const char *msg, const MachineFunction *MF);
158 void report(const char *msg, const MachineBasicBlock *MBB);
159 void report(const char *msg, const MachineInstr *MI);
160 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
162 void markReachable(const MachineBasicBlock *MBB);
163 void calcMaxRegsPassed();
164 void calcMinRegsPassed();
165 void checkPHIOps(const MachineBasicBlock *MBB);
169 char MachineVerifier::ID = 0;
170 static RegisterPass<MachineVerifier>
171 MachineVer("machineverifier", "Verify generated machine code");
172 static const PassInfo *const MachineVerifyID = &MachineVer;
174 FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {
175 return new MachineVerifier(allowPhysDoubleDefs);
178 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
179 raw_ostream *OutFile = 0;
181 std::string ErrorInfo;
182 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
183 raw_fd_ostream::F_Append);
184 if (!ErrorInfo.empty()) {
185 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
197 TM = &MF.getTarget();
198 TRI = TM->getRegisterInfo();
199 MRI = &MF.getRegInfo();
201 visitMachineFunctionBefore();
202 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
204 visitMachineBasicBlockBefore(MFI);
205 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
206 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
207 visitMachineInstrBefore(MBBI);
208 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
209 visitMachineOperand(&MBBI->getOperand(I), I);
210 visitMachineInstrAfter(MBBI);
212 visitMachineBasicBlockAfter(MFI);
214 visitMachineFunctionAfter();
218 else if (foundErrors)
219 llvm_report_error("Found "+Twine(foundErrors)+" machine code errors.");
226 regsLiveInButUnused.clear();
229 return false; // no changes
232 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
237 *OS << "*** Bad machine code: " << msg << " ***\n"
238 << "- function: " << MF->getFunction()->getNameStr() << "\n";
242 MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
245 report(msg, MBB->getParent());
246 *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
248 << " (#" << MBB->getNumber() << ")\n";
252 MachineVerifier::report(const char *msg, const MachineInstr *MI)
255 report(msg, MI->getParent());
256 *OS << "- instruction: ";
261 MachineVerifier::report(const char *msg,
262 const MachineOperand *MO, unsigned MONum)
265 report(msg, MO->getParent());
266 *OS << "- operand " << MONum << ": ";
272 MachineVerifier::markReachable(const MachineBasicBlock *MBB)
274 BBInfo &MInfo = MBBInfoMap[MBB];
275 if (!MInfo.reachable) {
276 MInfo.reachable = true;
277 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
278 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
284 MachineVerifier::visitMachineFunctionBefore()
286 regsReserved = TRI->getReservedRegs(*MF);
288 // A sub-register of a reserved register is also reserved
289 for (int Reg = regsReserved.find_first(); Reg>=0;
290 Reg = regsReserved.find_next(Reg)) {
291 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
292 // FIXME: This should probably be:
293 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
294 regsReserved.set(*Sub);
297 markReachable(&MF->front());
301 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
304 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
305 E = MBB->livein_end(); I != E; ++I) {
306 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
307 report("MBB live-in list contains non-physical register", MBB);
311 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
314 regsLiveInButUnused = regsLive;
316 const MachineFrameInfo *MFI = MF->getFrameInfo();
317 assert(MFI && "Function has no frame info");
318 BitVector PR = MFI->getPristineRegs(MBB);
319 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
321 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
330 MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
332 const TargetInstrDesc &TI = MI->getDesc();
333 if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
334 report("Too few operands", MI);
335 *OS << TI.getNumOperands() << " operands expected, but "
336 << MI->getNumExplicitOperands() << " given.\n";
338 if (!TI.isVariadic()) {
339 if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
340 report("Too many operands", MI);
341 *OS << TI.getNumOperands() << " operands expected, but "
342 << MI->getNumExplicitOperands() << " given.\n";
348 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
350 const MachineInstr *MI = MO->getParent();
351 const TargetInstrDesc &TI = MI->getDesc();
353 // The first TI.NumDefs operands must be explicit register defines
354 if (MONum < TI.getNumDefs()) {
356 report("Explicit definition must be a register", MO, MONum);
357 else if (!MO->isDef())
358 report("Explicit definition marked as use", MO, MONum);
359 else if (MO->isImplicit())
360 report("Explicit definition marked as implicit", MO, MONum);
363 switch (MO->getType()) {
364 case MachineOperand::MO_Register: {
365 const unsigned Reg = MO->getReg();
369 // Check Live Variables.
371 // An <undef> doesn't refer to any register, so just skip it.
372 } else if (MO->isUse()) {
373 regsLiveInButUnused.erase(Reg);
376 addRegWithSubRegs(regsKilled, Reg);
377 // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
378 if (MI->isRegTiedToDefOperand(MONum))
379 report("Illegal kill flag on two-address instruction operand",
382 // TwoAddress instr modifying a reg is treated as kill+def.
384 if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
385 MI->getOperand(defIdx).getReg() == Reg)
386 addRegWithSubRegs(regsKilled, Reg);
388 // Use of a dead register.
389 if (!regsLive.count(Reg)) {
390 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
391 // Reserved registers may be used even when 'dead'.
392 if (!isReserved(Reg))
393 report("Using an undefined physical register", MO, MONum);
395 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
396 // We don't know which virtual registers are live in, so only complain
397 // if vreg was killed in this MBB. Otherwise keep track of vregs that
398 // must be live in. PHI instructions are handled separately.
399 if (MInfo.regsKilled.count(Reg))
400 report("Using a killed virtual register", MO, MONum);
401 else if (MI->getOpcode() != TargetInstrInfo::PHI)
402 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
408 // TODO: verify that earlyclobber ops are not used.
410 addRegWithSubRegs(regsDead, Reg);
412 addRegWithSubRegs(regsDefined, Reg);
415 // Check register classes.
416 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
417 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
418 unsigned SubIdx = MO->getSubReg();
420 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
423 unsigned s = TRI->getSubReg(Reg, SubIdx);
425 report("Invalid subregister index for physical register",
431 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
432 if (!DRC->contains(sr)) {
433 report("Illegal physical register for instruction", MO, MONum);
434 *OS << TRI->getName(sr) << " is not a "
435 << DRC->getName() << " register.\n";
440 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
442 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
443 report("Invalid subregister index for virtual register", MO, MONum);
446 RC = *(RC->subregclasses_begin()+SubIdx);
448 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
449 if (RC != DRC && !RC->hasSuperClass(DRC)) {
450 report("Illegal virtual register for instruction", MO, MONum);
451 *OS << "Expected a " << DRC->getName() << " register, but got a "
452 << RC->getName() << " register\n";
459 // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
460 // case MachineOperand::MO_MachineBasicBlock:
461 // if (MI->getOpcode() == TargetInstrInfo::PHI) {
462 // if (!MO->getMBB()->isSuccessor(MI->getParent()))
463 // report("PHI operand is not in the CFG", MO, MONum);
472 MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
474 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
475 set_union(MInfo.regsKilled, regsKilled);
476 set_subtract(regsLive, regsKilled);
479 // Verify that both <def> and <def,dead> operands refer to dead registers.
480 RegVector defs(regsDefined);
481 defs.append(regsDead.begin(), regsDead.end());
483 for (RegVector::const_iterator I = defs.begin(), E = defs.end();
485 if (regsLive.count(*I)) {
486 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
487 if (!allowPhysDoubleDefs && !isReserved(*I) &&
488 !regsLiveInButUnused.count(*I)) {
489 report("Redefining a live physical register", MI);
490 *OS << "Register " << TRI->getName(*I)
491 << " was defined but already live.\n";
494 if (!allowVirtDoubleDefs) {
495 report("Redefining a live virtual register", MI);
496 *OS << "Virtual register %reg" << *I
497 << " was defined but already live.\n";
500 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
501 !MInfo.regsKilled.count(*I)) {
502 // Virtual register defined without being killed first must be dead on
504 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
508 set_subtract(regsLive, regsDead); regsDead.clear();
509 set_union(regsLive, regsDefined); regsDefined.clear();
513 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
515 MBBInfoMap[MBB].regsLiveOut = regsLive;
519 // Calculate the largest possible vregsPassed sets. These are the registers that
520 // can pass through an MBB live, but may not be live every time. It is assumed
521 // that all vregsPassed sets are empty before the call.
523 MachineVerifier::calcMaxRegsPassed()
525 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
526 // have any vregsPassed.
527 DenseSet<const MachineBasicBlock*> todo;
528 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
530 const MachineBasicBlock &MBB(*MFI);
531 BBInfo &MInfo = MBBInfoMap[&MBB];
532 if (!MInfo.reachable)
534 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
535 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
536 BBInfo &SInfo = MBBInfoMap[*SuI];
537 if (SInfo.addPassed(MInfo.regsLiveOut))
542 // Iteratively push vregsPassed to successors. This will converge to the same
543 // final state regardless of DenseSet iteration order.
544 while (!todo.empty()) {
545 const MachineBasicBlock *MBB = *todo.begin();
547 BBInfo &MInfo = MBBInfoMap[MBB];
548 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
549 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
552 BBInfo &SInfo = MBBInfoMap[*SuI];
553 if (SInfo.addPassed(MInfo.vregsPassed))
559 // Calculate the minimum vregsPassed set. These are the registers that always
560 // pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
561 // been called earlier.
563 MachineVerifier::calcMinRegsPassed()
565 DenseSet<const MachineBasicBlock*> todo;
566 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
570 while (!todo.empty()) {
571 const MachineBasicBlock *MBB = *todo.begin();
573 BBInfo &MInfo = MBBInfoMap[MBB];
575 // Remove entries from vRegsPassed that are not live out from all
576 // reachable predecessors.
578 for (RegSet::iterator I = MInfo.vregsPassed.begin(),
579 E = MInfo.vregsPassed.end(); I != E; ++I) {
580 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
581 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
582 BBInfo &PrInfo = MBBInfoMap[*PrI];
583 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
589 // If any regs removed, we need to recheck successors.
591 set_subtract(MInfo.vregsPassed, dead);
592 todo.insert(MBB->succ_begin(), MBB->succ_end());
597 // Check PHI instructions at the beginning of MBB. It is assumed that
598 // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
600 MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
602 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
603 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
604 DenseSet<const MachineBasicBlock*> seen;
606 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
607 unsigned Reg = BBI->getOperand(i).getReg();
608 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
609 if (!Pre->isSuccessor(MBB))
612 BBInfo &PrInfo = MBBInfoMap[Pre];
613 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
614 report("PHI operand is not live-out from predecessor",
615 &BBI->getOperand(i), i);
618 // Did we see all predecessors?
619 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
620 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
621 if (!seen.count(*PrI)) {
622 report("Missing PHI operand", BBI);
623 *OS << "MBB #" << (*PrI)->getNumber()
624 << " is a predecessor according to the CFG.\n";
631 MachineVerifier::visitMachineFunctionAfter()
635 // With the maximal set of vregsPassed we can verify dead-in registers.
636 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
638 BBInfo &MInfo = MBBInfoMap[MFI];
640 // Skip unreachable MBBs.
641 if (!MInfo.reachable)
644 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
645 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
646 BBInfo &PrInfo = MBBInfoMap[*PrI];
647 if (!PrInfo.reachable)
650 // Verify physical live-ins. EH landing pads have magic live-ins so we
652 if (!MFI->isLandingPad()) {
653 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
654 E = MFI->livein_end(); I != E; ++I) {
655 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
656 !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
657 report("Live-in physical register is not live-out from predecessor",
659 *OS << "Register " << TRI->getName(*I)
660 << " is not live-out from MBB #" << (*PrI)->getNumber()
667 // Verify dead-in virtual registers.
668 if (!allowVirtDoubleDefs) {
669 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
670 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
671 // DeadIn register must be in neither regsLiveOut or vregsPassed of
673 if (PrInfo.isLiveOut(I->first)) {
674 report("Live-in virtual register redefined", I->second);
675 *OS << "Register %reg" << I->first
676 << " was live-out from predecessor MBB #"
677 << (*PrI)->getNumber() << ".\n";
686 // With the minimal set of vregsPassed we can verify live-in virtual
687 // registers, including PHI instructions.
688 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
690 BBInfo &MInfo = MBBInfoMap[MFI];
692 // Skip unreachable MBBs.
693 if (!MInfo.reachable)
698 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
699 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
700 BBInfo &PrInfo = MBBInfoMap[*PrI];
701 if (!PrInfo.reachable)
704 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
705 E = MInfo.vregsLiveIn.end(); I != E; ++I) {
706 if (!PrInfo.isLiveOut(I->first)) {
707 report("Used virtual register is not live-in", I->second);
708 *OS << "Register %reg" << I->first
709 << " is not live-out from predecessor MBB #"
710 << (*PrI)->getNumber()