1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/ADT/DenseSet.h"
27 #include "llvm/ADT/SetOperations.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Function.h"
30 #include "llvm/CodeGen/LiveVariables.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
47 struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
48 static char ID; // Pass ID, replacement for typeid
50 MachineVerifier(bool allowDoubleDefs = false) :
51 MachineFunctionPass(&ID),
52 allowVirtDoubleDefs(allowDoubleDefs),
53 allowPhysDoubleDefs(allowDoubleDefs),
54 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
57 void getAnalysisUsage(AnalysisUsage &AU) const {
59 MachineFunctionPass::getAnalysisUsage(AU);
62 bool runOnMachineFunction(MachineFunction &MF);
64 const bool allowVirtDoubleDefs;
65 const bool allowPhysDoubleDefs;
67 const char *const OutFileName;
69 const MachineFunction *MF;
70 const TargetMachine *TM;
71 const TargetRegisterInfo *TRI;
72 const MachineRegisterInfo *MRI;
76 typedef SmallVector<unsigned, 16> RegVector;
77 typedef DenseSet<unsigned> RegSet;
78 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
80 BitVector regsReserved;
82 RegVector regsDefined, regsDead, regsKilled;
83 RegSet regsLiveInButUnused;
85 // Add Reg and any sub-registers to RV
86 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
88 if (TargetRegisterInfo::isPhysicalRegister(Reg))
89 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
94 // Is this MBB reachable from the MF entry point?
97 // Vregs that must be live in because they are used without being
98 // defined. Map value is the user.
101 // Vregs that must be dead in because they are defined without being
102 // killed first. Map value is the defining instruction.
105 // Regs killed in MBB. They may be defined again, and will then be in both
106 // regsKilled and regsLiveOut.
109 // Regs defined in MBB and live out. Note that vregs passing through may
110 // be live out without being mentioned here.
113 // Vregs that pass through MBB untouched. This set is disjoint from
114 // regsKilled and regsLiveOut.
117 BBInfo() : reachable(false) {}
119 // Add register to vregsPassed if it belongs there. Return true if
121 bool addPassed(unsigned Reg) {
122 if (!TargetRegisterInfo::isVirtualRegister(Reg))
124 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
126 return vregsPassed.insert(Reg).second;
129 // Same for a full set.
130 bool addPassed(const RegSet &RS) {
131 bool changed = false;
132 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
138 // Live-out registers are either in regsLiveOut or vregsPassed.
139 bool isLiveOut(unsigned Reg) const {
140 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
144 // Extra register info per MBB.
145 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
147 bool isReserved(unsigned Reg) {
148 return Reg < regsReserved.size() && regsReserved.test(Reg);
151 void visitMachineFunctionBefore();
152 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
153 void visitMachineInstrBefore(const MachineInstr *MI);
154 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
155 void visitMachineInstrAfter(const MachineInstr *MI);
156 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
157 void visitMachineFunctionAfter();
159 void report(const char *msg, const MachineFunction *MF);
160 void report(const char *msg, const MachineBasicBlock *MBB);
161 void report(const char *msg, const MachineInstr *MI);
162 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
164 void markReachable(const MachineBasicBlock *MBB);
165 void calcMaxRegsPassed();
166 void calcMinRegsPassed();
167 void checkPHIOps(const MachineBasicBlock *MBB);
171 char MachineVerifier::ID = 0;
172 static RegisterPass<MachineVerifier>
173 MachineVer("machineverifier", "Verify generated machine code");
174 static const PassInfo *const MachineVerifyID = &MachineVer;
177 llvm::createMachineVerifierPass(bool allowPhysDoubleDefs)
179 return new MachineVerifier(allowPhysDoubleDefs);
183 MachineVerifier::runOnMachineFunction(MachineFunction &MF)
185 std::ofstream OutFile;
187 OutFile.open(OutFileName, std::ios::out | std::ios::app);
196 TM = &MF.getTarget();
197 TRI = TM->getRegisterInfo();
198 MRI = &MF.getRegInfo();
200 visitMachineFunctionBefore();
201 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
203 visitMachineBasicBlockBefore(MFI);
204 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
205 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
206 visitMachineInstrBefore(MBBI);
207 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
208 visitMachineOperand(&MBBI->getOperand(I), I);
209 visitMachineInstrAfter(MBBI);
211 visitMachineBasicBlockAfter(MFI);
213 visitMachineFunctionAfter();
217 else if (foundErrors) {
219 raw_string_ostream Msg(msg);
220 Msg << "Found " << foundErrors << " machine code errors.";
221 llvm_report_error(Msg.str());
229 regsLiveInButUnused.clear();
232 return false; // no changes
235 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
240 *OS << "*** Bad machine code: " << msg << " ***\n"
241 << "- function: " << MF->getFunction()->getNameStr() << "\n";
245 MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
248 report(msg, MBB->getParent());
249 *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
251 << " (#" << MBB->getNumber() << ")\n";
255 MachineVerifier::report(const char *msg, const MachineInstr *MI)
258 report(msg, MI->getParent());
259 *OS << "- instruction: ";
264 MachineVerifier::report(const char *msg,
265 const MachineOperand *MO, unsigned MONum)
268 report(msg, MO->getParent());
269 *OS << "- operand " << MONum << ": ";
275 MachineVerifier::markReachable(const MachineBasicBlock *MBB)
277 BBInfo &MInfo = MBBInfoMap[MBB];
278 if (!MInfo.reachable) {
279 MInfo.reachable = true;
280 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
281 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
287 MachineVerifier::visitMachineFunctionBefore()
289 regsReserved = TRI->getReservedRegs(*MF);
291 // A sub-register of a reserved register is also reserved
292 for (int Reg = regsReserved.find_first(); Reg>=0;
293 Reg = regsReserved.find_next(Reg)) {
294 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
295 // FIXME: This should probably be:
296 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
297 regsReserved.set(*Sub);
300 markReachable(&MF->front());
304 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
307 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
308 E = MBB->livein_end(); I != E; ++I) {
309 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
310 report("MBB live-in list contains non-physical register", MBB);
314 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
317 regsLiveInButUnused = regsLive;
319 const MachineFrameInfo *MFI = MF->getFrameInfo();
320 assert(MFI && "Function has no frame info");
321 BitVector PR = MFI->getPristineRegs(MBB);
322 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
324 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
333 MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
335 const TargetInstrDesc &TI = MI->getDesc();
336 if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
337 report("Too few operands", MI);
338 *OS << TI.getNumOperands() << " operands expected, but "
339 << MI->getNumExplicitOperands() << " given.\n";
341 if (!TI.isVariadic()) {
342 if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
343 report("Too many operands", MI);
344 *OS << TI.getNumOperands() << " operands expected, but "
345 << MI->getNumExplicitOperands() << " given.\n";
351 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
353 const MachineInstr *MI = MO->getParent();
354 const TargetInstrDesc &TI = MI->getDesc();
356 // The first TI.NumDefs operands must be explicit register defines
357 if (MONum < TI.getNumDefs()) {
359 report("Explicit definition must be a register", MO, MONum);
360 else if (!MO->isDef())
361 report("Explicit definition marked as use", MO, MONum);
362 else if (MO->isImplicit())
363 report("Explicit definition marked as implicit", MO, MONum);
366 switch (MO->getType()) {
367 case MachineOperand::MO_Register: {
368 const unsigned Reg = MO->getReg();
372 // Check Live Variables.
374 // An <undef> doesn't refer to any register, so just skip it.
375 } else if (MO->isUse()) {
376 regsLiveInButUnused.erase(Reg);
379 addRegWithSubRegs(regsKilled, Reg);
380 // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
381 if (MI->isRegTiedToDefOperand(MONum))
382 report("Illegal kill flag on two-address instruction operand",
385 // TwoAddress instr modifying a reg is treated as kill+def.
387 if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
388 MI->getOperand(defIdx).getReg() == Reg)
389 addRegWithSubRegs(regsKilled, Reg);
391 // Use of a dead register.
392 if (!regsLive.count(Reg)) {
393 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
394 // Reserved registers may be used even when 'dead'.
395 if (!isReserved(Reg))
396 report("Using an undefined physical register", MO, MONum);
398 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
399 // We don't know which virtual registers are live in, so only complain
400 // if vreg was killed in this MBB. Otherwise keep track of vregs that
401 // must be live in. PHI instructions are handled separately.
402 if (MInfo.regsKilled.count(Reg))
403 report("Using a killed virtual register", MO, MONum);
404 else if (MI->getOpcode() != TargetInstrInfo::PHI)
405 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
411 // TODO: verify that earlyclobber ops are not used.
413 addRegWithSubRegs(regsDead, Reg);
415 addRegWithSubRegs(regsDefined, Reg);
418 // Check register classes.
419 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
420 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
421 unsigned SubIdx = MO->getSubReg();
423 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
426 unsigned s = TRI->getSubReg(Reg, SubIdx);
428 report("Invalid subregister index for physical register",
434 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
435 if (!DRC->contains(sr)) {
436 report("Illegal physical register for instruction", MO, MONum);
437 *OS << TRI->getName(sr) << " is not a "
438 << DRC->getName() << " register.\n";
443 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
445 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
446 report("Invalid subregister index for virtual register", MO, MONum);
449 RC = *(RC->subregclasses_begin()+SubIdx);
451 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
452 if (RC != DRC && !RC->hasSuperClass(DRC)) {
453 report("Illegal virtual register for instruction", MO, MONum);
454 *OS << "Expected a " << DRC->getName() << " register, but got a "
455 << RC->getName() << " register\n";
462 // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
463 // case MachineOperand::MO_MachineBasicBlock:
464 // if (MI->getOpcode() == TargetInstrInfo::PHI) {
465 // if (!MO->getMBB()->isSuccessor(MI->getParent()))
466 // report("PHI operand is not in the CFG", MO, MONum);
475 MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
477 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
478 set_union(MInfo.regsKilled, regsKilled);
479 set_subtract(regsLive, regsKilled);
482 // Verify that both <def> and <def,dead> operands refer to dead registers.
483 RegVector defs(regsDefined);
484 defs.append(regsDead.begin(), regsDead.end());
486 for (RegVector::const_iterator I = defs.begin(), E = defs.end();
488 if (regsLive.count(*I)) {
489 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
490 if (!allowPhysDoubleDefs && !isReserved(*I) &&
491 !regsLiveInButUnused.count(*I)) {
492 report("Redefining a live physical register", MI);
493 *OS << "Register " << TRI->getName(*I)
494 << " was defined but already live.\n";
497 if (!allowVirtDoubleDefs) {
498 report("Redefining a live virtual register", MI);
499 *OS << "Virtual register %reg" << *I
500 << " was defined but already live.\n";
503 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
504 !MInfo.regsKilled.count(*I)) {
505 // Virtual register defined without being killed first must be dead on
507 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
511 set_subtract(regsLive, regsDead); regsDead.clear();
512 set_union(regsLive, regsDefined); regsDefined.clear();
516 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
518 MBBInfoMap[MBB].regsLiveOut = regsLive;
522 // Calculate the largest possible vregsPassed sets. These are the registers that
523 // can pass through an MBB live, but may not be live every time. It is assumed
524 // that all vregsPassed sets are empty before the call.
526 MachineVerifier::calcMaxRegsPassed()
528 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
529 // have any vregsPassed.
530 DenseSet<const MachineBasicBlock*> todo;
531 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
533 const MachineBasicBlock &MBB(*MFI);
534 BBInfo &MInfo = MBBInfoMap[&MBB];
535 if (!MInfo.reachable)
537 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
538 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
539 BBInfo &SInfo = MBBInfoMap[*SuI];
540 if (SInfo.addPassed(MInfo.regsLiveOut))
545 // Iteratively push vregsPassed to successors. This will converge to the same
546 // final state regardless of DenseSet iteration order.
547 while (!todo.empty()) {
548 const MachineBasicBlock *MBB = *todo.begin();
550 BBInfo &MInfo = MBBInfoMap[MBB];
551 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
552 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
555 BBInfo &SInfo = MBBInfoMap[*SuI];
556 if (SInfo.addPassed(MInfo.vregsPassed))
562 // Calculate the minimum vregsPassed set. These are the registers that always
563 // pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
564 // been called earlier.
566 MachineVerifier::calcMinRegsPassed()
568 DenseSet<const MachineBasicBlock*> todo;
569 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
573 while (!todo.empty()) {
574 const MachineBasicBlock *MBB = *todo.begin();
576 BBInfo &MInfo = MBBInfoMap[MBB];
578 // Remove entries from vRegsPassed that are not live out from all
579 // reachable predecessors.
581 for (RegSet::iterator I = MInfo.vregsPassed.begin(),
582 E = MInfo.vregsPassed.end(); I != E; ++I) {
583 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
584 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
585 BBInfo &PrInfo = MBBInfoMap[*PrI];
586 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
592 // If any regs removed, we need to recheck successors.
594 set_subtract(MInfo.vregsPassed, dead);
595 todo.insert(MBB->succ_begin(), MBB->succ_end());
600 // Check PHI instructions at the beginning of MBB. It is assumed that
601 // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
603 MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
605 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
606 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
607 DenseSet<const MachineBasicBlock*> seen;
609 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
610 unsigned Reg = BBI->getOperand(i).getReg();
611 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
612 if (!Pre->isSuccessor(MBB))
615 BBInfo &PrInfo = MBBInfoMap[Pre];
616 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
617 report("PHI operand is not live-out from predecessor",
618 &BBI->getOperand(i), i);
621 // Did we see all predecessors?
622 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
623 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
624 if (!seen.count(*PrI)) {
625 report("Missing PHI operand", BBI);
626 *OS << "MBB #" << (*PrI)->getNumber()
627 << " is a predecessor according to the CFG.\n";
634 MachineVerifier::visitMachineFunctionAfter()
638 // With the maximal set of vregsPassed we can verify dead-in registers.
639 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
641 BBInfo &MInfo = MBBInfoMap[MFI];
643 // Skip unreachable MBBs.
644 if (!MInfo.reachable)
647 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
648 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
649 BBInfo &PrInfo = MBBInfoMap[*PrI];
650 if (!PrInfo.reachable)
653 // Verify physical live-ins. EH landing pads have magic live-ins so we
655 if (!MFI->isLandingPad()) {
656 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
657 E = MFI->livein_end(); I != E; ++I) {
658 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
659 !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
660 report("Live-in physical register is not live-out from predecessor",
662 *OS << "Register " << TRI->getName(*I)
663 << " is not live-out from MBB #" << (*PrI)->getNumber()
670 // Verify dead-in virtual registers.
671 if (!allowVirtDoubleDefs) {
672 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
673 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
674 // DeadIn register must be in neither regsLiveOut or vregsPassed of
676 if (PrInfo.isLiveOut(I->first)) {
677 report("Live-in virtual register redefined", I->second);
678 *OS << "Register %reg" << I->first
679 << " was live-out from predecessor MBB #"
680 << (*PrI)->getNumber() << ".\n";
689 // With the minimal set of vregsPassed we can verify live-in virtual
690 // registers, including PHI instructions.
691 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
693 BBInfo &MInfo = MBBInfoMap[MFI];
695 // Skip unreachable MBBs.
696 if (!MInfo.reachable)
701 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
702 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
703 BBInfo &PrInfo = MBBInfoMap[*PrI];
704 if (!PrInfo.reachable)
707 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
708 E = MInfo.vregsLiveIn.end(); I != E; ++I) {
709 if (!PrInfo.isLiveOut(I->first)) {
710 report("Used virtual register is not live-in", I->second);
711 *OS << "Register %reg" << I->first
712 << " is not live-out from predecessor MBB #"
713 << (*PrI)->getNumber()