1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Instructions.h"
27 #include "llvm/Function.h"
28 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/LiveStackAnalysis.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineMemOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/ADT/DenseSet.h"
42 #include "llvm/ADT/SetOperations.h"
43 #include "llvm/ADT/SmallVector.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/raw_ostream.h"
50 struct MachineVerifier {
52 MachineVerifier(Pass *pass, const char *b) :
55 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
58 bool runOnMachineFunction(MachineFunction &MF);
62 const char *const OutFileName;
64 const MachineFunction *MF;
65 const TargetMachine *TM;
66 const TargetInstrInfo *TII;
67 const TargetRegisterInfo *TRI;
68 const MachineRegisterInfo *MRI;
72 typedef SmallVector<unsigned, 16> RegVector;
73 typedef SmallVector<const uint32_t*, 4> RegMaskVector;
74 typedef DenseSet<unsigned> RegSet;
75 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
77 const MachineInstr *FirstTerminator;
79 BitVector regsReserved;
80 BitVector regsAllocatable;
82 RegVector regsDefined, regsDead, regsKilled;
83 RegMaskVector regMasks;
84 RegSet regsLiveInButUnused;
88 // Add Reg and any sub-registers to RV
89 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
91 if (TargetRegisterInfo::isPhysicalRegister(Reg))
92 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
93 RV.push_back(*SubRegs);
97 // Is this MBB reachable from the MF entry point?
100 // Vregs that must be live in because they are used without being
101 // defined. Map value is the user.
104 // Regs killed in MBB. They may be defined again, and will then be in both
105 // regsKilled and regsLiveOut.
108 // Regs defined in MBB and live out. Note that vregs passing through may
109 // be live out without being mentioned here.
112 // Vregs that pass through MBB untouched. This set is disjoint from
113 // regsKilled and regsLiveOut.
116 // Vregs that must pass through MBB because they are needed by a successor
117 // block. This set is disjoint from regsLiveOut.
118 RegSet vregsRequired;
120 BBInfo() : reachable(false) {}
122 // Add register to vregsPassed if it belongs there. Return true if
124 bool addPassed(unsigned Reg) {
125 if (!TargetRegisterInfo::isVirtualRegister(Reg))
127 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
129 return vregsPassed.insert(Reg).second;
132 // Same for a full set.
133 bool addPassed(const RegSet &RS) {
134 bool changed = false;
135 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
141 // Add register to vregsRequired if it belongs there. Return true if
143 bool addRequired(unsigned Reg) {
144 if (!TargetRegisterInfo::isVirtualRegister(Reg))
146 if (regsLiveOut.count(Reg))
148 return vregsRequired.insert(Reg).second;
151 // Same for a full set.
152 bool addRequired(const RegSet &RS) {
153 bool changed = false;
154 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
160 // Same for a full map.
161 bool addRequired(const RegMap &RM) {
162 bool changed = false;
163 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
164 if (addRequired(I->first))
169 // Live-out registers are either in regsLiveOut or vregsPassed.
170 bool isLiveOut(unsigned Reg) const {
171 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
175 // Extra register info per MBB.
176 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
178 bool isReserved(unsigned Reg) {
179 return Reg < regsReserved.size() && regsReserved.test(Reg);
182 bool isAllocatable(unsigned Reg) {
183 return Reg < regsAllocatable.size() && regsAllocatable.test(Reg);
186 // Analysis information if available
187 LiveVariables *LiveVars;
188 LiveIntervals *LiveInts;
189 LiveStacks *LiveStks;
190 SlotIndexes *Indexes;
192 void visitMachineFunctionBefore();
193 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
194 void visitMachineBundleBefore(const MachineInstr *MI);
195 void visitMachineInstrBefore(const MachineInstr *MI);
196 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
197 void visitMachineInstrAfter(const MachineInstr *MI);
198 void visitMachineBundleAfter(const MachineInstr *MI);
199 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
200 void visitMachineFunctionAfter();
202 void report(const char *msg, const MachineFunction *MF);
203 void report(const char *msg, const MachineBasicBlock *MBB);
204 void report(const char *msg, const MachineInstr *MI);
205 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
207 void checkLiveness(const MachineOperand *MO, unsigned MONum);
208 void markReachable(const MachineBasicBlock *MBB);
209 void calcRegsPassed();
210 void checkPHIOps(const MachineBasicBlock *MBB);
212 void calcRegsRequired();
213 void verifyLiveVariables();
214 void verifyLiveIntervals();
217 struct MachineVerifierPass : public MachineFunctionPass {
218 static char ID; // Pass ID, replacement for typeid
219 const char *const Banner;
221 MachineVerifierPass(const char *b = 0)
222 : MachineFunctionPass(ID), Banner(b) {
223 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
226 void getAnalysisUsage(AnalysisUsage &AU) const {
227 AU.setPreservesAll();
228 MachineFunctionPass::getAnalysisUsage(AU);
231 bool runOnMachineFunction(MachineFunction &MF) {
232 MF.verify(this, Banner);
239 char MachineVerifierPass::ID = 0;
240 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
241 "Verify generated machine code", false, false)
243 FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
244 return new MachineVerifierPass(Banner);
247 void MachineFunction::verify(Pass *p, const char *Banner) const {
248 MachineVerifier(p, Banner)
249 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
252 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
253 raw_ostream *OutFile = 0;
255 std::string ErrorInfo;
256 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
257 raw_fd_ostream::F_Append);
258 if (!ErrorInfo.empty()) {
259 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
271 TM = &MF.getTarget();
272 TII = TM->getInstrInfo();
273 TRI = TM->getRegisterInfo();
274 MRI = &MF.getRegInfo();
281 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
282 // We don't want to verify LiveVariables if LiveIntervals is available.
284 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
285 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
286 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
289 visitMachineFunctionBefore();
290 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
292 visitMachineBasicBlockBefore(MFI);
293 // Keep track of the current bundle header.
294 const MachineInstr *CurBundle = 0;
295 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
296 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
297 if (MBBI->getParent() != MFI) {
298 report("Bad instruction parent pointer", MFI);
299 *OS << "Instruction: " << *MBBI;
302 // Is this a bundle header?
303 if (!MBBI->isInsideBundle()) {
305 visitMachineBundleAfter(CurBundle);
307 visitMachineBundleBefore(CurBundle);
308 } else if (!CurBundle)
309 report("No bundle header", MBBI);
310 visitMachineInstrBefore(MBBI);
311 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
312 visitMachineOperand(&MBBI->getOperand(I), I);
313 visitMachineInstrAfter(MBBI);
316 visitMachineBundleAfter(CurBundle);
317 visitMachineBasicBlockAfter(MFI);
319 visitMachineFunctionAfter();
323 else if (foundErrors)
324 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
332 regsLiveInButUnused.clear();
335 return false; // no changes
338 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
341 if (!foundErrors++) {
343 *OS << "# " << Banner << '\n';
344 MF->print(*OS, Indexes);
346 *OS << "*** Bad machine code: " << msg << " ***\n"
347 << "- function: " << MF->getFunction()->getName() << "\n";
350 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
352 report(msg, MBB->getParent());
353 *OS << "- basic block: " << MBB->getName()
355 << " (BB#" << MBB->getNumber() << ")";
357 *OS << " [" << Indexes->getMBBStartIdx(MBB)
358 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
362 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
364 report(msg, MI->getParent());
365 *OS << "- instruction: ";
366 if (Indexes && Indexes->hasIndex(MI))
367 *OS << Indexes->getInstructionIndex(MI) << '\t';
371 void MachineVerifier::report(const char *msg,
372 const MachineOperand *MO, unsigned MONum) {
374 report(msg, MO->getParent());
375 *OS << "- operand " << MONum << ": ";
380 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
381 BBInfo &MInfo = MBBInfoMap[MBB];
382 if (!MInfo.reachable) {
383 MInfo.reachable = true;
384 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
385 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
390 void MachineVerifier::visitMachineFunctionBefore() {
391 lastIndex = SlotIndex();
392 regsReserved = TRI->getReservedRegs(*MF);
394 // A sub-register of a reserved register is also reserved
395 for (int Reg = regsReserved.find_first(); Reg>=0;
396 Reg = regsReserved.find_next(Reg)) {
397 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
398 // FIXME: This should probably be:
399 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
400 regsReserved.set(*SubRegs);
404 regsAllocatable = TRI->getAllocatableSet(*MF);
406 markReachable(&MF->front());
409 // Does iterator point to a and b as the first two elements?
410 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
411 const MachineBasicBlock *a, const MachineBasicBlock *b) {
420 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
424 // If this block has allocatable physical registers live-in, check that
425 // it is an entry block or landing pad.
426 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
427 LE = MBB->livein_end();
430 if (isAllocatable(reg) && !MBB->isLandingPad() &&
431 MBB != MBB->getParent()->begin()) {
432 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
437 // Count the number of landing pad successors.
438 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
439 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
440 E = MBB->succ_end(); I != E; ++I) {
441 if ((*I)->isLandingPad())
442 LandingPadSuccs.insert(*I);
445 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
446 const BasicBlock *BB = MBB->getBasicBlock();
447 if (LandingPadSuccs.size() > 1 &&
449 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
450 BB && isa<SwitchInst>(BB->getTerminator())))
451 report("MBB has more than one landing pad successor", MBB);
453 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
454 MachineBasicBlock *TBB = 0, *FBB = 0;
455 SmallVector<MachineOperand, 4> Cond;
456 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
458 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
459 // check whether its answers match up with reality.
461 // Block falls through to its successor.
462 MachineFunction::const_iterator MBBI = MBB;
464 if (MBBI == MF->end()) {
465 // It's possible that the block legitimately ends with a noreturn
466 // call or an unreachable, in which case it won't actually fall
467 // out the bottom of the function.
468 } else if (MBB->succ_size() == LandingPadSuccs.size()) {
469 // It's possible that the block legitimately ends with a noreturn
470 // call or an unreachable, in which case it won't actuall fall
472 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
473 report("MBB exits via unconditional fall-through but doesn't have "
474 "exactly one CFG successor!", MBB);
475 } else if (!MBB->isSuccessor(MBBI)) {
476 report("MBB exits via unconditional fall-through but its successor "
477 "differs from its CFG successor!", MBB);
479 if (!MBB->empty() && getBundleStart(&MBB->back())->isBarrier() &&
480 !TII->isPredicated(getBundleStart(&MBB->back()))) {
481 report("MBB exits via unconditional fall-through but ends with a "
482 "barrier instruction!", MBB);
485 report("MBB exits via unconditional fall-through but has a condition!",
488 } else if (TBB && !FBB && Cond.empty()) {
489 // Block unconditionally branches somewhere.
490 if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
491 report("MBB exits via unconditional branch but doesn't have "
492 "exactly one CFG successor!", MBB);
493 } else if (!MBB->isSuccessor(TBB)) {
494 report("MBB exits via unconditional branch but the CFG "
495 "successor doesn't match the actual successor!", MBB);
498 report("MBB exits via unconditional branch but doesn't contain "
499 "any instructions!", MBB);
500 } else if (!getBundleStart(&MBB->back())->isBarrier()) {
501 report("MBB exits via unconditional branch but doesn't end with a "
502 "barrier instruction!", MBB);
503 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
504 report("MBB exits via unconditional branch but the branch isn't a "
505 "terminator instruction!", MBB);
507 } else if (TBB && !FBB && !Cond.empty()) {
508 // Block conditionally branches somewhere, otherwise falls through.
509 MachineFunction::const_iterator MBBI = MBB;
511 if (MBBI == MF->end()) {
512 report("MBB conditionally falls through out of function!", MBB);
513 } if (MBB->succ_size() != 2) {
514 report("MBB exits via conditional branch/fall-through but doesn't have "
515 "exactly two CFG successors!", MBB);
516 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
517 report("MBB exits via conditional branch/fall-through but the CFG "
518 "successors don't match the actual successors!", MBB);
521 report("MBB exits via conditional branch/fall-through but doesn't "
522 "contain any instructions!", MBB);
523 } else if (getBundleStart(&MBB->back())->isBarrier()) {
524 report("MBB exits via conditional branch/fall-through but ends with a "
525 "barrier instruction!", MBB);
526 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
527 report("MBB exits via conditional branch/fall-through but the branch "
528 "isn't a terminator instruction!", MBB);
530 } else if (TBB && FBB) {
531 // Block conditionally branches somewhere, otherwise branches
533 if (MBB->succ_size() != 2) {
534 report("MBB exits via conditional branch/branch but doesn't have "
535 "exactly two CFG successors!", MBB);
536 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
537 report("MBB exits via conditional branch/branch but the CFG "
538 "successors don't match the actual successors!", MBB);
541 report("MBB exits via conditional branch/branch but doesn't "
542 "contain any instructions!", MBB);
543 } else if (!getBundleStart(&MBB->back())->isBarrier()) {
544 report("MBB exits via conditional branch/branch but doesn't end with a "
545 "barrier instruction!", MBB);
546 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
547 report("MBB exits via conditional branch/branch but the branch "
548 "isn't a terminator instruction!", MBB);
551 report("MBB exits via conditinal branch/branch but there's no "
555 report("AnalyzeBranch returned invalid data!", MBB);
560 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
561 E = MBB->livein_end(); I != E; ++I) {
562 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
563 report("MBB live-in list contains non-physical register", MBB);
567 for (MCSubRegIterator SubRegs(*I, TRI); SubRegs.isValid(); ++SubRegs)
568 regsLive.insert(*SubRegs);
570 regsLiveInButUnused = regsLive;
572 const MachineFrameInfo *MFI = MF->getFrameInfo();
573 assert(MFI && "Function has no frame info");
574 BitVector PR = MFI->getPristineRegs(MBB);
575 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
577 for (MCSubRegIterator SubRegs(I, TRI); SubRegs.isValid(); ++SubRegs)
578 regsLive.insert(*SubRegs);
585 lastIndex = Indexes->getMBBStartIdx(MBB);
588 // This function gets called for all bundle headers, including normal
589 // stand-alone unbundled instructions.
590 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
591 if (Indexes && Indexes->hasIndex(MI)) {
592 SlotIndex idx = Indexes->getInstructionIndex(MI);
593 if (!(idx > lastIndex)) {
594 report("Instruction index out of order", MI);
595 *OS << "Last instruction was at " << lastIndex << '\n';
600 // Ensure non-terminators don't follow terminators.
601 // Ignore predicated terminators formed by if conversion.
602 // FIXME: If conversion shouldn't need to violate this rule.
603 if (MI->isTerminator() && !TII->isPredicated(MI)) {
604 if (!FirstTerminator)
605 FirstTerminator = MI;
606 } else if (FirstTerminator) {
607 report("Non-terminator instruction after the first terminator", MI);
608 *OS << "First terminator was:\t" << *FirstTerminator;
612 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
613 const MCInstrDesc &MCID = MI->getDesc();
614 if (MI->getNumOperands() < MCID.getNumOperands()) {
615 report("Too few operands", MI);
616 *OS << MCID.getNumOperands() << " operands expected, but "
617 << MI->getNumExplicitOperands() << " given.\n";
620 // Check the MachineMemOperands for basic consistency.
621 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
622 E = MI->memoperands_end(); I != E; ++I) {
623 if ((*I)->isLoad() && !MI->mayLoad())
624 report("Missing mayLoad flag", MI);
625 if ((*I)->isStore() && !MI->mayStore())
626 report("Missing mayStore flag", MI);
629 // Debug values must not have a slot index.
630 // Other instructions must have one, unless they are inside a bundle.
632 bool mapped = !LiveInts->isNotInMIMap(MI);
633 if (MI->isDebugValue()) {
635 report("Debug instruction has a slot index", MI);
636 } else if (MI->isInsideBundle()) {
638 report("Instruction inside bundle has a slot index", MI);
641 report("Missing slot index", MI);
646 if (!TII->verifyInstruction(MI, ErrorInfo))
647 report(ErrorInfo.data(), MI);
651 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
652 const MachineInstr *MI = MO->getParent();
653 const MCInstrDesc &MCID = MI->getDesc();
654 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
656 // The first MCID.NumDefs operands must be explicit register defines
657 if (MONum < MCID.getNumDefs()) {
659 report("Explicit definition must be a register", MO, MONum);
660 else if (!MO->isDef() && !MCOI.isOptionalDef())
661 report("Explicit definition marked as use", MO, MONum);
662 else if (MO->isImplicit())
663 report("Explicit definition marked as implicit", MO, MONum);
664 } else if (MONum < MCID.getNumOperands()) {
665 // Don't check if it's the last operand in a variadic instruction. See,
666 // e.g., LDM_RET in the arm back end.
668 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
669 if (MO->isDef() && !MCOI.isOptionalDef())
670 report("Explicit operand marked as def", MO, MONum);
671 if (MO->isImplicit())
672 report("Explicit operand marked as implicit", MO, MONum);
675 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
676 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
677 report("Extra explicit operand on non-variadic instruction", MO, MONum);
680 switch (MO->getType()) {
681 case MachineOperand::MO_Register: {
682 const unsigned Reg = MO->getReg();
685 if (MRI->tracksLiveness() && !MI->isDebugValue())
686 checkLiveness(MO, MONum);
689 // Check register classes.
690 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
691 unsigned SubIdx = MO->getSubReg();
693 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
695 report("Illegal subregister index for physical register", MO, MONum);
698 if (const TargetRegisterClass *DRC =
699 TII->getRegClass(MCID, MONum, TRI, *MF)) {
700 if (!DRC->contains(Reg)) {
701 report("Illegal physical register for instruction", MO, MONum);
702 *OS << TRI->getName(Reg) << " is not a "
703 << DRC->getName() << " register.\n";
708 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
710 const TargetRegisterClass *SRC =
711 TRI->getSubClassWithSubReg(RC, SubIdx);
713 report("Invalid subregister index for virtual register", MO, MONum);
714 *OS << "Register class " << RC->getName()
715 << " does not support subreg index " << SubIdx << "\n";
719 report("Invalid register class for subregister index", MO, MONum);
720 *OS << "Register class " << RC->getName()
721 << " does not fully support subreg index " << SubIdx << "\n";
725 if (const TargetRegisterClass *DRC =
726 TII->getRegClass(MCID, MONum, TRI, *MF)) {
728 const TargetRegisterClass *SuperRC =
729 TRI->getLargestLegalSuperClass(RC);
731 report("No largest legal super class exists.", MO, MONum);
734 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
736 report("No matching super-reg register class.", MO, MONum);
740 if (!RC->hasSuperClassEq(DRC)) {
741 report("Illegal virtual register for instruction", MO, MONum);
742 *OS << "Expected a " << DRC->getName() << " register, but got a "
743 << RC->getName() << " register\n";
751 case MachineOperand::MO_RegisterMask:
752 regMasks.push_back(MO->getRegMask());
755 case MachineOperand::MO_MachineBasicBlock:
756 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
757 report("PHI operand is not in the CFG", MO, MONum);
760 case MachineOperand::MO_FrameIndex:
761 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
762 LiveInts && !LiveInts->isNotInMIMap(MI)) {
763 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
764 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
765 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
766 report("Instruction loads from dead spill slot", MO, MONum);
767 *OS << "Live stack: " << LI << '\n';
769 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
770 report("Instruction stores to dead spill slot", MO, MONum);
771 *OS << "Live stack: " << LI << '\n';
781 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
782 const MachineInstr *MI = MO->getParent();
783 const unsigned Reg = MO->getReg();
785 // Both use and def operands can read a register.
786 if (MO->readsReg()) {
787 regsLiveInButUnused.erase(Reg);
791 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
792 // A two-addr use counts as a kill if use and def are the same.
793 unsigned DefReg = MI->getOperand(defIdx).getReg();
796 else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
797 report("Two-address instruction operands must be identical", MO, MONum);
800 isKill = MO->isKill();
803 addRegWithSubRegs(regsKilled, Reg);
805 // Check that LiveVars knows this kill.
806 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
808 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
809 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
810 report("Kill missing from LiveVariables", MO, MONum);
813 // Check LiveInts liveness and kill.
814 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
815 LiveInts && !LiveInts->isNotInMIMap(MI)) {
816 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getRegSlot(true);
817 if (LiveInts->hasInterval(Reg)) {
818 const LiveInterval &LI = LiveInts->getInterval(Reg);
819 if (!LI.liveAt(UseIdx)) {
820 report("No live range at use", MO, MONum);
821 *OS << UseIdx << " is not live in " << LI << '\n';
823 // Check for extra kill flags.
824 // Note that we allow missing kill flags for now.
825 if (MO->isKill() && !LI.killedAt(UseIdx.getRegSlot())) {
826 report("Live range continues after kill flag", MO, MONum);
827 *OS << "Live range: " << LI << '\n';
830 report("Virtual register has no Live interval", MO, MONum);
834 // Use of a dead register.
835 if (!regsLive.count(Reg)) {
836 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
837 // Reserved registers may be used even when 'dead'.
838 if (!isReserved(Reg))
839 report("Using an undefined physical register", MO, MONum);
840 } else if (MRI->def_empty(Reg)) {
841 report("Reading virtual register without a def", MO, MONum);
843 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
844 // We don't know which virtual registers are live in, so only complain
845 // if vreg was killed in this MBB. Otherwise keep track of vregs that
846 // must be live in. PHI instructions are handled separately.
847 if (MInfo.regsKilled.count(Reg))
848 report("Using a killed virtual register", MO, MONum);
849 else if (!MI->isPHI())
850 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
857 // TODO: verify that earlyclobber ops are not used.
859 addRegWithSubRegs(regsDead, Reg);
861 addRegWithSubRegs(regsDefined, Reg);
864 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
865 llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
866 report("Multiple virtual register defs in SSA form", MO, MONum);
868 // Check LiveInts for a live range, but only for virtual registers.
869 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
870 !LiveInts->isNotInMIMap(MI)) {
871 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
872 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
873 if (LiveInts->hasInterval(Reg)) {
874 const LiveInterval &LI = LiveInts->getInterval(Reg);
875 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
876 assert(VNI && "NULL valno is not allowed");
877 if (VNI->def != DefIdx) {
878 report("Inconsistent valno->def", MO, MONum);
879 *OS << "Valno " << VNI->id << " is not defined at "
880 << DefIdx << " in " << LI << '\n';
883 report("No live range at def", MO, MONum);
884 *OS << DefIdx << " is not live in " << LI << '\n';
887 report("Virtual register has no Live interval", MO, MONum);
893 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
896 // This function gets called after visiting all instructions in a bundle. The
897 // argument points to the bundle header.
898 // Normal stand-alone instructions are also considered 'bundles', and this
899 // function is called for all of them.
900 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
901 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
902 set_union(MInfo.regsKilled, regsKilled);
903 set_subtract(regsLive, regsKilled); regsKilled.clear();
904 // Kill any masked registers.
905 while (!regMasks.empty()) {
906 const uint32_t *Mask = regMasks.pop_back_val();
907 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
908 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
909 MachineOperand::clobbersPhysReg(Mask, *I))
910 regsDead.push_back(*I);
912 set_subtract(regsLive, regsDead); regsDead.clear();
913 set_union(regsLive, regsDefined); regsDefined.clear();
917 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
918 MBBInfoMap[MBB].regsLiveOut = regsLive;
922 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
923 if (!(stop > lastIndex)) {
924 report("Block ends before last instruction index", MBB);
925 *OS << "Block ends at " << stop
926 << " last instruction was at " << lastIndex << '\n';
932 // Calculate the largest possible vregsPassed sets. These are the registers that
933 // can pass through an MBB live, but may not be live every time. It is assumed
934 // that all vregsPassed sets are empty before the call.
935 void MachineVerifier::calcRegsPassed() {
936 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
937 // have any vregsPassed.
938 SmallPtrSet<const MachineBasicBlock*, 8> todo;
939 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
941 const MachineBasicBlock &MBB(*MFI);
942 BBInfo &MInfo = MBBInfoMap[&MBB];
943 if (!MInfo.reachable)
945 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
946 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
947 BBInfo &SInfo = MBBInfoMap[*SuI];
948 if (SInfo.addPassed(MInfo.regsLiveOut))
953 // Iteratively push vregsPassed to successors. This will converge to the same
954 // final state regardless of DenseSet iteration order.
955 while (!todo.empty()) {
956 const MachineBasicBlock *MBB = *todo.begin();
958 BBInfo &MInfo = MBBInfoMap[MBB];
959 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
960 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
963 BBInfo &SInfo = MBBInfoMap[*SuI];
964 if (SInfo.addPassed(MInfo.vregsPassed))
970 // Calculate the set of virtual registers that must be passed through each basic
971 // block in order to satisfy the requirements of successor blocks. This is very
972 // similar to calcRegsPassed, only backwards.
973 void MachineVerifier::calcRegsRequired() {
974 // First push live-in regs to predecessors' vregsRequired.
975 SmallPtrSet<const MachineBasicBlock*, 8> todo;
976 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
978 const MachineBasicBlock &MBB(*MFI);
979 BBInfo &MInfo = MBBInfoMap[&MBB];
980 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
981 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
982 BBInfo &PInfo = MBBInfoMap[*PrI];
983 if (PInfo.addRequired(MInfo.vregsLiveIn))
988 // Iteratively push vregsRequired to predecessors. This will converge to the
989 // same final state regardless of DenseSet iteration order.
990 while (!todo.empty()) {
991 const MachineBasicBlock *MBB = *todo.begin();
993 BBInfo &MInfo = MBBInfoMap[MBB];
994 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
995 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
998 BBInfo &SInfo = MBBInfoMap[*PrI];
999 if (SInfo.addRequired(MInfo.vregsRequired))
1005 // Check PHI instructions at the beginning of MBB. It is assumed that
1006 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1007 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1008 SmallPtrSet<const MachineBasicBlock*, 8> seen;
1009 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
1010 BBI != BBE && BBI->isPHI(); ++BBI) {
1013 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
1014 unsigned Reg = BBI->getOperand(i).getReg();
1015 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
1016 if (!Pre->isSuccessor(MBB))
1019 BBInfo &PrInfo = MBBInfoMap[Pre];
1020 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1021 report("PHI operand is not live-out from predecessor",
1022 &BBI->getOperand(i), i);
1025 // Did we see all predecessors?
1026 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1027 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1028 if (!seen.count(*PrI)) {
1029 report("Missing PHI operand", BBI);
1030 *OS << "BB#" << (*PrI)->getNumber()
1031 << " is a predecessor according to the CFG.\n";
1037 void MachineVerifier::visitMachineFunctionAfter() {
1040 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1041 MFI != MFE; ++MFI) {
1042 BBInfo &MInfo = MBBInfoMap[MFI];
1044 // Skip unreachable MBBs.
1045 if (!MInfo.reachable)
1051 // Now check liveness info if available
1054 // Check for killed virtual registers that should be live out.
1055 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1056 MFI != MFE; ++MFI) {
1057 BBInfo &MInfo = MBBInfoMap[MFI];
1058 for (RegSet::iterator
1059 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1061 if (MInfo.regsKilled.count(*I)) {
1062 report("Virtual register killed in block, but needed live out.", MFI);
1063 *OS << "Virtual register " << PrintReg(*I)
1064 << " is used after the block.\n";
1069 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1070 for (RegSet::iterator
1071 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1073 report("Virtual register def doesn't dominate all uses.",
1074 MRI->getVRegDef(*I));
1078 verifyLiveVariables();
1080 verifyLiveIntervals();
1083 void MachineVerifier::verifyLiveVariables() {
1084 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1085 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1086 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1087 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1088 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1089 MFI != MFE; ++MFI) {
1090 BBInfo &MInfo = MBBInfoMap[MFI];
1092 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1093 if (MInfo.vregsRequired.count(Reg)) {
1094 if (!VI.AliveBlocks.test(MFI->getNumber())) {
1095 report("LiveVariables: Block missing from AliveBlocks", MFI);
1096 *OS << "Virtual register " << PrintReg(Reg)
1097 << " must be live through the block.\n";
1100 if (VI.AliveBlocks.test(MFI->getNumber())) {
1101 report("LiveVariables: Block should not be in AliveBlocks", MFI);
1102 *OS << "Virtual register " << PrintReg(Reg)
1103 << " is not needed live through the block.\n";
1110 void MachineVerifier::verifyLiveIntervals() {
1111 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1112 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1113 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1115 // Spilling and splitting may leave unused registers around. Skip them.
1116 if (MRI->reg_nodbg_empty(Reg))
1119 if (!LiveInts->hasInterval(Reg)) {
1120 report("Missing live interval for virtual register", MF);
1121 *OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
1125 const LiveInterval &LI = LiveInts->getInterval(Reg);
1126 assert(Reg == LI.reg && "Invalid reg to interval mapping");
1128 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
1131 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
1134 if (!VNI->isUnused()) {
1135 report("Valno not live at def and not marked unused", MF);
1136 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1141 if (VNI->isUnused())
1144 if (DefVNI != VNI) {
1145 report("Live range at def has different valno", MF);
1146 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1147 << " where valno #" << DefVNI->id << " is live in " << LI << '\n';
1151 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1153 report("Invalid definition index", MF);
1154 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1155 << " in " << LI << '\n';
1159 if (VNI->isPHIDef()) {
1160 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1161 report("PHIDef value is not defined at MBB start", MF);
1162 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1163 << ", not at the beginning of BB#" << MBB->getNumber()
1164 << " in " << LI << '\n';
1168 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1170 report("No instruction at def index", MF);
1171 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1172 << " in " << LI << '\n';
1176 bool hasDef = false;
1177 bool isEarlyClobber = false;
1178 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1179 if (!MOI->isReg() || !MOI->isDef())
1181 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1182 if (MOI->getReg() != LI.reg)
1185 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1186 !TRI->regsOverlap(LI.reg, MOI->getReg()))
1190 if (MOI->isEarlyClobber())
1191 isEarlyClobber = true;
1195 report("Defining instruction does not modify register", MI);
1196 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1199 // Early clobber defs begin at USE slots, but other defs must begin at
1201 if (isEarlyClobber) {
1202 if (!VNI->def.isEarlyClobber()) {
1203 report("Early clobber def must be at an early-clobber slot", MF);
1204 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1205 << " in " << LI << '\n';
1207 } else if (!VNI->def.isRegister()) {
1208 report("Non-PHI, non-early clobber def must be at a register slot",
1210 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1211 << " in " << LI << '\n';
1216 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
1217 const VNInfo *VNI = I->valno;
1218 assert(VNI && "Live range has no valno");
1220 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1221 report("Foreign valno in live range", MF);
1223 *OS << " has a valno not in " << LI << '\n';
1226 if (VNI->isUnused()) {
1227 report("Live range valno is marked unused", MF);
1229 *OS << " in " << LI << '\n';
1232 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
1234 report("Bad start of live segment, no basic block", MF);
1236 *OS << " in " << LI << '\n';
1239 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1240 if (I->start != MBBStartIdx && I->start != VNI->def) {
1241 report("Live segment must begin at MBB entry or valno def", MBB);
1243 *OS << " in " << LI << '\n' << "Basic block starts at "
1244 << MBBStartIdx << '\n';
1247 const MachineBasicBlock *EndMBB =
1248 LiveInts->getMBBFromIndex(I->end.getPrevSlot());
1250 report("Bad end of live segment, no basic block", MF);
1252 *OS << " in " << LI << '\n';
1256 // No more checks for live-out segments.
1257 if (I->end == LiveInts->getMBBEndIdx(EndMBB))
1260 // The live segment is ending inside EndMBB
1261 const MachineInstr *MI =
1262 LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
1264 report("Live segment doesn't end at a valid instruction", EndMBB);
1266 *OS << " in " << LI << '\n' << "Basic block starts at "
1267 << MBBStartIdx << '\n';
1271 // The block slot must refer to a basic block boundary.
1272 if (I->end.isBlock()) {
1273 report("Live segment ends at B slot of an instruction", MI);
1275 *OS << " in " << LI << '\n';
1278 if (I->end.isDead()) {
1279 // Segment ends on the dead slot.
1280 // That means there must be a dead def.
1281 if (!SlotIndex::isSameInstr(I->start, I->end)) {
1282 report("Live segment ending at dead slot spans instructions", MI);
1284 *OS << " in " << LI << '\n';
1288 // A live segment can only end at an early-clobber slot if it is being
1289 // redefined by an early-clobber def.
1290 if (I->end.isEarlyClobber()) {
1291 if (I+1 == E || (I+1)->start != I->end) {
1292 report("Live segment ending at early clobber slot must be "
1293 "redefined by an EC def in the same instruction", MI);
1295 *OS << " in " << LI << '\n';
1299 // The following checks only apply to virtual registers. Physreg liveness
1300 // is too weird to check.
1301 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1302 // A live range can end with either a redefinition, a kill flag on a
1303 // use, or a dead flag on a def.
1304 bool hasRead = false;
1305 bool hasDeadDef = false;
1306 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1307 if (!MOI->isReg() || MOI->getReg() != LI.reg)
1309 if (MOI->readsReg())
1311 if (MOI->isDef() && MOI->isDead())
1315 if (I->end.isDead()) {
1317 report("Instruction doesn't have a dead def operand", MI);
1319 *OS << " in " << LI << '\n';
1323 report("Instruction ending live range doesn't read the register",
1326 *OS << " in " << LI << '\n';
1331 // Now check all the basic blocks in this live segment.
1332 MachineFunction::const_iterator MFI = MBB;
1333 // Is this live range the beginning of a non-PHIDef VN?
1334 if (I->start == VNI->def && !VNI->isPHIDef()) {
1335 // Not live-in to any blocks.
1342 assert(LiveInts->isLiveInToMBB(LI, MFI));
1343 // We don't know how to track physregs into a landing pad.
1344 if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
1345 MFI->isLandingPad()) {
1346 if (&*MFI == EndMBB)
1352 // Is VNI a PHI-def in the current block?
1353 bool IsPHI = VNI->isPHIDef() &&
1354 VNI->def == LiveInts->getMBBStartIdx(MFI);
1356 // Check that VNI is live-out of all predecessors.
1357 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1358 PE = MFI->pred_end(); PI != PE; ++PI) {
1359 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1360 const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
1362 // All predecessors must have a live-out value.
1364 report("Register not marked live out of predecessor", *PI);
1365 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1366 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1367 << PEnd << " in " << LI << '\n';
1371 // Only PHI-defs can take different predecessor values.
1372 if (!IsPHI && PVNI != VNI) {
1373 report("Different value live out of predecessor", *PI);
1374 *OS << "Valno #" << PVNI->id << " live out of BB#"
1375 << (*PI)->getNumber() << '@' << PEnd
1376 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1377 << '@' << LiveInts->getMBBStartIdx(MFI) << " in "
1378 << PrintReg(Reg) << ": " << LI << '\n';
1381 if (&*MFI == EndMBB)
1387 // Check the LI only has one connected component.
1388 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1389 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1390 unsigned NumComp = ConEQ.Classify(&LI);
1392 report("Multiple connected components in live interval", MF);
1393 *OS << NumComp << " components in " << LI << '\n';
1394 for (unsigned comp = 0; comp != NumComp; ++comp) {
1395 *OS << comp << ": valnos";
1396 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1397 E = LI.vni_end(); I!=E; ++I)
1398 if (comp == ConEQ.getEqClass(*I))
1399 *OS << ' ' << (*I)->id;