1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "phielim"
17 #include "PHIElimination.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Function.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/ADT/SmallPtrSet.h"
27 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
36 STATISTIC(NumAtomic, "Number of atomic phis lowered");
37 STATISTIC(NumSplits, "Number of critical edges split on demand");
38 STATISTIC(NumReused, "Number of reused lowered phis");
40 char PHIElimination::ID = 0;
41 static RegisterPass<PHIElimination>
42 X("phi-node-elimination", "Eliminate PHI nodes for register allocation");
44 const PassInfo *const llvm::PHIEliminationID = &X;
46 void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
47 AU.addPreserved<LiveVariables>();
48 AU.addPreserved<MachineDominatorTree>();
49 // rdar://7401784 This would be nice:
50 // AU.addPreservedID(MachineLoopInfoID);
51 MachineFunctionPass::getAnalysisUsage(AU);
54 bool llvm::PHIElimination::runOnMachineFunction(MachineFunction &Fn) {
55 MRI = &Fn.getRegInfo();
61 // Split critical edges to help the coalescer
62 if (LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>())
63 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
64 Changed |= SplitPHIEdges(Fn, *I, *LV);
66 // Populate VRegPHIUseCount
69 // Eliminate PHI instructions by inserting copies into predecessor blocks.
70 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
71 Changed |= EliminatePHINodes(Fn, *I);
73 // Remove dead IMPLICIT_DEF instructions.
74 for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(),
75 E = ImpDefs.end(); I != E; ++I) {
76 MachineInstr *DefMI = *I;
77 unsigned DefReg = DefMI->getOperand(0).getReg();
78 if (MRI->use_empty(DefReg))
79 DefMI->eraseFromParent();
82 // Clean up the lowered PHI instructions.
83 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
85 Fn.DeleteMachineInstr(I->first);
89 VRegPHIUseCount.clear();
93 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
94 /// predecessor basic blocks.
96 bool llvm::PHIElimination::EliminatePHINodes(MachineFunction &MF,
97 MachineBasicBlock &MBB) {
98 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
99 return false; // Quick exit for basic blocks without PHIs.
101 // Get an iterator to the first instruction after the last PHI node (this may
102 // also be the end of the basic block).
103 MachineBasicBlock::iterator AfterPHIsIt = SkipPHIsAndLabels(MBB, MBB.begin());
105 while (MBB.front().getOpcode() == TargetInstrInfo::PHI)
106 LowerAtomicPHINode(MBB, AfterPHIsIt);
111 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
112 /// are implicit_def's.
113 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
114 const MachineRegisterInfo *MRI) {
115 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
116 unsigned SrcReg = MPhi->getOperand(i).getReg();
117 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
118 if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
124 // FindCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
125 // when following the CFG edge to SuccMBB. This needs to be after any def of
126 // SrcReg, but before any subsequent point where control flow might jump out of
128 MachineBasicBlock::iterator
129 llvm::PHIElimination::FindCopyInsertPoint(MachineBasicBlock &MBB,
130 MachineBasicBlock &SuccMBB,
132 // Handle the trivial case trivially.
136 // Usually, we just want to insert the copy before the first terminator
137 // instruction. However, for the edge going to a landing pad, we must insert
138 // the copy before the call/invoke instruction.
139 if (!SuccMBB.isLandingPad())
140 return MBB.getFirstTerminator();
142 // Discover any defs/uses in this basic block.
143 SmallPtrSet<MachineInstr*, 8> DefUsesInMBB;
144 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
145 RE = MRI->reg_end(); RI != RE; ++RI) {
146 MachineInstr *DefUseMI = &*RI;
147 if (DefUseMI->getParent() == &MBB)
148 DefUsesInMBB.insert(DefUseMI);
151 MachineBasicBlock::iterator InsertPoint;
152 if (DefUsesInMBB.empty()) {
153 // No defs. Insert the copy at the start of the basic block.
154 InsertPoint = MBB.begin();
155 } else if (DefUsesInMBB.size() == 1) {
156 // Insert the copy immediately after the def/use.
157 InsertPoint = *DefUsesInMBB.begin();
160 // Insert the copy immediately after the last def/use.
161 InsertPoint = MBB.end();
162 while (!DefUsesInMBB.count(&*--InsertPoint)) {}
166 // Make sure the copy goes after any phi nodes however.
167 return SkipPHIsAndLabels(MBB, InsertPoint);
170 /// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
171 /// under the assuption that it needs to be lowered in a way that supports
172 /// atomic execution of PHIs. This lowering method is always correct all of the
175 void llvm::PHIElimination::LowerAtomicPHINode(
176 MachineBasicBlock &MBB,
177 MachineBasicBlock::iterator AfterPHIsIt) {
179 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
180 MachineInstr *MPhi = MBB.remove(MBB.begin());
182 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
183 unsigned DestReg = MPhi->getOperand(0).getReg();
184 bool isDead = MPhi->getOperand(0).isDead();
186 // Create a new register for the incoming PHI arguments.
187 MachineFunction &MF = *MBB.getParent();
188 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
189 unsigned IncomingReg = 0;
190 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
192 // Insert a register to register copy at the top of the current block (but
193 // after any remaining phi nodes) which copies the new incoming register
194 // into the phi node destination.
195 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
196 if (isSourceDefinedByImplicitDef(MPhi, MRI))
197 // If all sources of a PHI node are implicit_def, just emit an
198 // implicit_def instead of a copy.
199 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
200 TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
202 // Can we reuse an earlier PHI node? This only happens for critical edges,
203 // typically those created by tail duplication.
204 unsigned &entry = LoweredPHIs[MPhi];
206 // An identical PHI node was already lowered. Reuse the incoming register.
208 reusedIncoming = true;
210 DEBUG(dbgs() << "Reusing %reg" << IncomingReg << " for " << *MPhi);
212 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
214 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
218 assert(!hasPHIDef(DestReg) && "Vreg has multiple phi-defs?");
219 PHIDefs[DestReg] = &MBB;
221 // Update live variable information if there is any.
222 LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>();
224 MachineInstr *PHICopy = prior(AfterPHIsIt);
227 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
229 // Increment use count of the newly created virtual register.
232 // When we are reusing the incoming register, it may already have been
233 // killed in this block. The old kill will also have been inserted at
234 // AfterPHIsIt, so it appears before the current PHICopy.
236 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
237 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
238 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
242 // Add information to LiveVariables to know that the incoming value is
243 // killed. Note that because the value is defined in several places (once
244 // each for each incoming block), the "def" block and instruction fields
245 // for the VarInfo is not filled in.
246 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
249 // Since we are going to be deleting the PHI node, if it is the last use of
250 // any registers, or if the value itself is dead, we need to move this
251 // information over to the new copy we just inserted.
252 LV->removeVirtualRegistersKilled(MPhi);
254 // If the result is dead, update LV.
256 LV->addVirtualRegisterDead(DestReg, PHICopy);
257 LV->removeVirtualRegisterDead(DestReg, MPhi);
261 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
262 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
263 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
264 MPhi->getOperand(i).getReg())];
266 // Now loop over all of the incoming arguments, changing them to copy into the
267 // IncomingReg register in the corresponding predecessor basic block.
268 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
269 for (int i = NumSrcs - 1; i >= 0; --i) {
270 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
271 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
272 "Machine PHI Operands must all be virtual registers!");
274 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
276 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
279 PHIKills[SrcReg].insert(&opBlock);
281 // If source is defined by an implicit def, there is no need to insert a
283 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
284 if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
285 ImpDefs.insert(DefMI);
289 // Check to make sure we haven't already emitted the copy for this block.
290 // This can happen because PHI nodes may have multiple entries for the same
292 if (!MBBsInsertedInto.insert(&opBlock))
293 continue; // If the copy has already been emitted, we're done.
295 // Find a safe location to insert the copy, this may be the first terminator
296 // in the block (or end()).
297 MachineBasicBlock::iterator InsertPos =
298 FindCopyInsertPoint(opBlock, MBB, SrcReg);
301 if (!reusedIncoming && IncomingReg)
302 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
304 // Now update live variable information if we have it. Otherwise we're done
307 // We want to be able to insert a kill of the register if this PHI (aka, the
308 // copy we just inserted) is the last use of the source value. Live
309 // variable analysis conservatively handles this by saying that the value is
310 // live until the end of the block the PHI entry lives in. If the value
311 // really is dead at the PHI copy, there will be no successor blocks which
312 // have the value live-in.
314 // Also check to see if this register is in use by another PHI node which
315 // has not yet been eliminated. If so, it will be killed at an appropriate
318 // Is it used by any PHI instructions in this block?
319 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)];
321 // Okay, if we now know that the value is not live out of the block, we can
322 // add a kill marker in this block saying that it kills the incoming value!
323 if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) {
324 // In our final twist, we have to decide which instruction kills the
325 // register. In most cases this is the copy, however, the first
326 // terminator instruction at the end of the block may also use the value.
327 // In this case, we should mark *it* as being the killing block, not the
329 MachineBasicBlock::iterator KillInst;
330 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator();
331 if (Term != opBlock.end() && Term->readsRegister(SrcReg)) {
334 // Check that no other terminators use values.
336 for (MachineBasicBlock::iterator TI = llvm::next(Term);
337 TI != opBlock.end(); ++TI) {
338 assert(!TI->readsRegister(SrcReg) &&
339 "Terminator instructions cannot use virtual registers unless"
340 "they are the first terminator in a block!");
343 } else if (reusedIncoming || !IncomingReg) {
344 // We may have to rewind a bit if we didn't insert a copy this time.
346 while (KillInst != opBlock.begin())
347 if ((--KillInst)->readsRegister(SrcReg))
350 // We just inserted this copy.
351 KillInst = prior(InsertPos);
353 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
355 // Finally, mark it killed.
356 LV->addVirtualRegisterKilled(SrcReg, KillInst);
358 // This vreg no longer lives all of the way through opBlock.
359 unsigned opBlockNum = opBlock.getNumber();
360 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
364 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
365 if (reusedIncoming || !IncomingReg)
366 MF.DeleteMachineInstr(MPhi);
369 /// analyzePHINodes - Gather information about the PHI nodes in here. In
370 /// particular, we want to map the number of uses of a virtual register which is
371 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
372 /// used later to determine when the vreg is killed in the BB.
374 void llvm::PHIElimination::analyzePHINodes(const MachineFunction& Fn) {
375 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
377 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
378 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
379 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
380 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(),
381 BBI->getOperand(i).getReg())];
384 bool llvm::PHIElimination::SplitPHIEdges(MachineFunction &MF,
385 MachineBasicBlock &MBB,
387 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI ||
389 return false; // Quick exit for basic blocks without PHIs.
391 for (MachineBasicBlock::const_iterator BBI = MBB.begin(), BBE = MBB.end();
392 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
393 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
394 unsigned Reg = BBI->getOperand(i).getReg();
395 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
396 // We break edges when registers are live out from the predecessor block
397 // (not considering PHI nodes). If the register is live in to this block
398 // anyway, we would gain nothing from splitting.
399 if (!LV.isLiveIn(Reg, MBB) && LV.isLiveOut(Reg, *PreMBB))
400 SplitCriticalEdge(PreMBB, &MBB);
406 MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
407 MachineBasicBlock *B) {
408 assert(A && B && "Missing MBB end point");
410 MachineFunction *MF = A->getParent();
412 // We may need to update A's terminator, but we can't do that if AnalyzeBranch
413 // fails. If A uses a jump table, we won't touch it.
414 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
415 MachineBasicBlock *TBB = 0, *FBB = 0;
416 SmallVector<MachineOperand, 4> Cond;
417 if (TII->AnalyzeBranch(*A, TBB, FBB, Cond))
422 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
423 MF->insert(llvm::next(MachineFunction::iterator(A)), NMBB);
424 DEBUG(dbgs() << "PHIElimination splitting critical edge:"
425 " BB#" << A->getNumber()
426 << " -- BB#" << NMBB->getNumber()
427 << " -- BB#" << B->getNumber() << '\n');
429 A->ReplaceUsesOfBlockWith(B, NMBB);
430 A->updateTerminator();
432 // Insert unconditional "jump B" instruction in NMBB if necessary.
433 NMBB->addSuccessor(B);
434 if (!NMBB->isLayoutSuccessor(B)) {
436 MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond);
439 // Fix PHI nodes in B so they refer to NMBB instead of A
440 for (MachineBasicBlock::iterator i = B->begin(), e = B->end();
441 i != e && i->getOpcode() == TargetInstrInfo::PHI; ++i)
442 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
443 if (i->getOperand(ni+1).getMBB() == A)
444 i->getOperand(ni+1).setMBB(NMBB);
446 if (LiveVariables *LV=getAnalysisIfAvailable<LiveVariables>())
447 LV->addNewBlock(NMBB, A, B);
449 if (MachineDominatorTree *MDT=getAnalysisIfAvailable<MachineDominatorTree>())
450 MDT->addNewBlock(NMBB, A);
456 PHIElimination::PHINodeTraits::getHashValue(const MachineInstr *MI) {
457 if (!MI || MI==getEmptyKey() || MI==getTombstoneKey())
458 return DenseMapInfo<MachineInstr*>::getHashValue(MI);
460 for (unsigned ni = 1, ne = MI->getNumOperands(); ni != ne; ni += 2)
461 hash = hash*37 + DenseMapInfo<BBVRegPair>::
462 getHashValue(BBVRegPair(MI->getOperand(ni+1).getMBB()->getNumber(),
463 MI->getOperand(ni).getReg()));
467 bool PHIElimination::PHINodeTraits::isEqual(const MachineInstr *LHS,
468 const MachineInstr *RHS) {
469 const MachineInstr *EmptyKey = getEmptyKey();
470 const MachineInstr *TombstoneKey = getTombstoneKey();
471 if (!LHS || !RHS || LHS==EmptyKey || RHS==EmptyKey ||
472 LHS==TombstoneKey || RHS==TombstoneKey)
475 unsigned ne = LHS->getNumOperands();
476 if (ne != RHS->getNumOperands())
478 // Ignore operand 0, the defined register.
479 for (unsigned ni = 1; ni != ne; ni += 2)
480 if (LHS->getOperand(ni).getReg() != RHS->getOperand(ni).getReg() ||
481 LHS->getOperand(ni+1).getMBB() != RHS->getOperand(ni+1).getMBB())