1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "phielim"
17 #include "llvm/CodeGen/Passes.h"
18 #include "PHIEliminationUtils.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
39 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
40 cl::Hidden, cl::desc("Disable critical edge splitting "
41 "during PHI elimination"));
44 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
45 cl::Hidden, cl::desc("Split all critical edges during "
49 class PHIElimination : public MachineFunctionPass {
50 MachineRegisterInfo *MRI; // Machine register information
55 static char ID; // Pass identification, replacement for typeid
56 PHIElimination() : MachineFunctionPass(ID) {
57 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
60 virtual bool runOnMachineFunction(MachineFunction &Fn);
61 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
64 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
65 /// in predecessor basic blocks.
67 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
68 void LowerPHINode(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator AfterPHIsIt);
71 /// analyzePHINodes - Gather information about the PHI nodes in
72 /// here. In particular, we want to map the number of uses of a virtual
73 /// register which is used in a PHI node. We map that to the BB the
74 /// vreg is coming from. This is used later to determine when the vreg
75 /// is killed in the BB.
77 void analyzePHINodes(const MachineFunction& Fn);
79 /// Split critical edges where necessary for good coalescer performance.
80 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
81 MachineLoopInfo *MLI);
83 // These functions are temporary abstractions around LiveVariables and
84 // LiveIntervals, so they can go away when LiveVariables does.
85 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB);
86 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB);
88 typedef std::pair<unsigned, unsigned> BBVRegPair;
89 typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
91 VRegPHIUse VRegPHIUseCount;
93 // Defs of PHI sources which are implicit_def.
94 SmallPtrSet<MachineInstr*, 4> ImpDefs;
96 // Map reusable lowered PHI node -> incoming join register.
97 typedef DenseMap<MachineInstr*, unsigned,
98 MachineInstrExpressionTrait> LoweredPHIMap;
99 LoweredPHIMap LoweredPHIs;
103 STATISTIC(NumLowered, "Number of phis lowered");
104 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
105 STATISTIC(NumReused, "Number of reused lowered phis");
107 char PHIElimination::ID = 0;
108 char& llvm::PHIEliminationID = PHIElimination::ID;
110 INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
111 "Eliminate PHI nodes for register allocation",
113 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
114 INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
115 "Eliminate PHI nodes for register allocation", false, false)
117 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
118 AU.addPreserved<LiveVariables>();
119 AU.addPreserved<SlotIndexes>();
120 AU.addPreserved<LiveIntervals>();
121 AU.addPreserved<MachineDominatorTree>();
122 AU.addPreserved<MachineLoopInfo>();
123 MachineFunctionPass::getAnalysisUsage(AU);
126 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
127 MRI = &MF.getRegInfo();
128 LV = getAnalysisIfAvailable<LiveVariables>();
129 LIS = getAnalysisIfAvailable<LiveIntervals>();
131 bool Changed = false;
133 // This pass takes the function out of SSA form.
136 // Split critical edges to help the coalescer. This does not yet support
137 // updating LiveIntervals, so we disable it.
138 if (!DisableEdgeSplitting && (LV || LIS)) {
139 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
140 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
141 Changed |= SplitPHIEdges(MF, *I, MLI);
144 // Populate VRegPHIUseCount
147 // Eliminate PHI instructions by inserting copies into predecessor blocks.
148 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
149 Changed |= EliminatePHINodes(MF, *I);
151 // Remove dead IMPLICIT_DEF instructions.
152 for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(),
153 E = ImpDefs.end(); I != E; ++I) {
154 MachineInstr *DefMI = *I;
155 unsigned DefReg = DefMI->getOperand(0).getReg();
156 if (MRI->use_nodbg_empty(DefReg)) {
158 LIS->RemoveMachineInstrFromMaps(DefMI);
159 DefMI->eraseFromParent();
163 // Clean up the lowered PHI instructions.
164 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
167 LIS->RemoveMachineInstrFromMaps(I->first);
168 MF.DeleteMachineInstr(I->first);
173 VRegPHIUseCount.clear();
178 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
179 /// predecessor basic blocks.
181 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
182 MachineBasicBlock &MBB) {
183 if (MBB.empty() || !MBB.front().isPHI())
184 return false; // Quick exit for basic blocks without PHIs.
186 // Get an iterator to the first instruction after the last PHI node (this may
187 // also be the end of the basic block).
188 MachineBasicBlock::iterator AfterPHIsIt = MBB.SkipPHIsAndLabels(MBB.begin());
190 while (MBB.front().isPHI())
191 LowerPHINode(MBB, AfterPHIsIt);
196 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
197 /// This includes registers with no defs.
198 static bool isImplicitlyDefined(unsigned VirtReg,
199 const MachineRegisterInfo *MRI) {
200 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg),
201 DE = MRI->def_end(); DI != DE; ++DI)
202 if (!DI->isImplicitDef())
207 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
208 /// are implicit_def's.
209 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
210 const MachineRegisterInfo *MRI) {
211 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
212 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
218 /// LowerPHINode - Lower the PHI node at the top of the specified block,
220 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
221 MachineBasicBlock::iterator AfterPHIsIt) {
223 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
224 MachineInstr *MPhi = MBB.remove(MBB.begin());
226 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
227 unsigned DestReg = MPhi->getOperand(0).getReg();
228 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
229 bool isDead = MPhi->getOperand(0).isDead();
231 // Create a new register for the incoming PHI arguments.
232 MachineFunction &MF = *MBB.getParent();
233 unsigned IncomingReg = 0;
234 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
236 // Insert a register to register copy at the top of the current block (but
237 // after any remaining phi nodes) which copies the new incoming register
238 // into the phi node destination.
239 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
240 if (isSourceDefinedByImplicitDef(MPhi, MRI))
241 // If all sources of a PHI node are implicit_def, just emit an
242 // implicit_def instead of a copy.
243 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
244 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
246 // Can we reuse an earlier PHI node? This only happens for critical edges,
247 // typically those created by tail duplication.
248 unsigned &entry = LoweredPHIs[MPhi];
250 // An identical PHI node was already lowered. Reuse the incoming register.
252 reusedIncoming = true;
254 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
256 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
257 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
259 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
260 TII->get(TargetOpcode::COPY), DestReg)
261 .addReg(IncomingReg);
264 // Update live variable information if there is any.
266 MachineInstr *PHICopy = prior(AfterPHIsIt);
269 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
271 // Increment use count of the newly created virtual register.
272 LV->setPHIJoin(IncomingReg);
274 // When we are reusing the incoming register, it may already have been
275 // killed in this block. The old kill will also have been inserted at
276 // AfterPHIsIt, so it appears before the current PHICopy.
278 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
279 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
280 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
284 // Add information to LiveVariables to know that the incoming value is
285 // killed. Note that because the value is defined in several places (once
286 // each for each incoming block), the "def" block and instruction fields
287 // for the VarInfo is not filled in.
288 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
291 // Since we are going to be deleting the PHI node, if it is the last use of
292 // any registers, or if the value itself is dead, we need to move this
293 // information over to the new copy we just inserted.
294 LV->removeVirtualRegistersKilled(MPhi);
296 // If the result is dead, update LV.
298 LV->addVirtualRegisterDead(DestReg, PHICopy);
299 LV->removeVirtualRegisterDead(DestReg, MPhi);
303 // Update LiveIntervals for the new copy or implicit def.
305 MachineInstr *NewInstr = prior(AfterPHIsIt);
306 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
308 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
310 // Add the region from the beginning of MBB to the copy instruction to
311 // IncomingReg's live interval.
312 LiveInterval &IncomingLI = LIS->getOrCreateInterval(IncomingReg);
313 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
315 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
316 LIS->getVNInfoAllocator());
317 IncomingLI.addRange(LiveRange(MBBStartIndex,
318 DestCopyIndex.getRegSlot(),
322 LiveInterval &DestLI = LIS->getInterval(DestReg);
323 assert(DestLI.begin() != DestLI.end() &&
324 "PHIs should have nonempty LiveIntervals.");
325 if (DestLI.endIndex().isDead()) {
326 // A dead PHI's live range begins and ends at the start of the MBB, but
327 // the lowered copy, which will still be dead, needs to begin and end at
328 // the copy instruction.
329 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
330 assert(OrigDestVNI && "PHI destination should be live at block entry.");
331 DestLI.removeRange(MBBStartIndex, MBBStartIndex.getDeadSlot());
332 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
333 LIS->getVNInfoAllocator());
334 DestLI.removeValNo(OrigDestVNI);
336 // Otherwise, remove the region from the beginning of MBB to the copy
337 // instruction from DestReg's live interval.
338 DestLI.removeRange(MBBStartIndex, DestCopyIndex.getRegSlot());
339 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
340 assert(DestVNI && "PHI destination should be live at its definition.");
341 DestVNI->def = DestCopyIndex.getRegSlot();
345 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
346 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
347 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
348 MPhi->getOperand(i).getReg())];
350 // Now loop over all of the incoming arguments, changing them to copy into the
351 // IncomingReg register in the corresponding predecessor basic block.
352 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
353 for (int i = NumSrcs - 1; i >= 0; --i) {
354 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
355 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
356 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
357 isImplicitlyDefined(SrcReg, MRI);
358 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
359 "Machine PHI Operands must all be virtual registers!");
361 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
363 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
365 // Check to make sure we haven't already emitted the copy for this block.
366 // This can happen because PHI nodes may have multiple entries for the same
368 if (!MBBsInsertedInto.insert(&opBlock))
369 continue; // If the copy has already been emitted, we're done.
371 // Find a safe location to insert the copy, this may be the first terminator
372 // in the block (or end()).
373 MachineBasicBlock::iterator InsertPos =
374 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
377 MachineInstr *NewSrcInstr = 0;
378 if (!reusedIncoming && IncomingReg) {
380 // The source register is undefined, so there is no need for a real
381 // COPY, but we still need to ensure joint dominance by defs.
382 // Insert an IMPLICIT_DEF instruction.
383 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
384 TII->get(TargetOpcode::IMPLICIT_DEF),
387 // Clean up the old implicit-def, if there even was one.
388 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
389 if (DefMI->isImplicitDef())
390 ImpDefs.insert(DefMI);
392 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
393 TII->get(TargetOpcode::COPY), IncomingReg)
394 .addReg(SrcReg, 0, SrcSubReg);
398 // We only need to update the LiveVariables kill of SrcReg if this was the
399 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
400 // out of the predecessor. We can also ignore undef sources.
401 if (LV && !SrcUndef &&
402 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
403 !LV->isLiveOut(SrcReg, opBlock)) {
404 // We want to be able to insert a kill of the register if this PHI (aka,
405 // the copy we just inserted) is the last use of the source value. Live
406 // variable analysis conservatively handles this by saying that the value
407 // is live until the end of the block the PHI entry lives in. If the value
408 // really is dead at the PHI copy, there will be no successor blocks which
409 // have the value live-in.
411 // Okay, if we now know that the value is not live out of the block, we
412 // can add a kill marker in this block saying that it kills the incoming
415 // In our final twist, we have to decide which instruction kills the
416 // register. In most cases this is the copy, however, terminator
417 // instructions at the end of the block may also use the value. In this
418 // case, we should mark the last such terminator as being the killing
419 // block, not the copy.
420 MachineBasicBlock::iterator KillInst = opBlock.end();
421 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
422 for (MachineBasicBlock::iterator Term = FirstTerm;
423 Term != opBlock.end(); ++Term) {
424 if (Term->readsRegister(SrcReg))
428 if (KillInst == opBlock.end()) {
429 // No terminator uses the register.
431 if (reusedIncoming || !IncomingReg) {
432 // We may have to rewind a bit if we didn't insert a copy this time.
433 KillInst = FirstTerm;
434 while (KillInst != opBlock.begin()) {
436 if (KillInst->isDebugValue())
438 if (KillInst->readsRegister(SrcReg))
442 // We just inserted this copy.
443 KillInst = prior(InsertPos);
446 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
448 // Finally, mark it killed.
449 LV->addVirtualRegisterKilled(SrcReg, KillInst);
451 // This vreg no longer lives all of the way through opBlock.
452 unsigned opBlockNum = opBlock.getNumber();
453 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
458 LIS->InsertMachineInstrInMaps(NewSrcInstr);
459 LIS->addLiveRangeToEndOfBlock(IncomingReg, NewSrcInstr);
463 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
464 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
466 bool isLiveOut = false;
467 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
468 SE = opBlock.succ_end(); SI != SE; ++SI) {
469 SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
470 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
472 // Definitions by other PHIs are not truly live-in for our purposes.
473 if (VNI && VNI->def != startIdx) {
480 MachineBasicBlock::iterator KillInst = opBlock.end();
481 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
482 for (MachineBasicBlock::iterator Term = FirstTerm;
483 Term != opBlock.end(); ++Term) {
484 if (Term->readsRegister(SrcReg))
488 if (KillInst == opBlock.end()) {
489 // No terminator uses the register.
491 if (reusedIncoming || !IncomingReg) {
492 // We may have to rewind a bit if we didn't just insert a copy.
493 KillInst = FirstTerm;
494 while (KillInst != opBlock.begin()) {
496 if (KillInst->isDebugValue())
498 if (KillInst->readsRegister(SrcReg))
502 // We just inserted this copy.
503 KillInst = prior(InsertPos);
506 assert(KillInst->readsRegister(SrcReg) &&
507 "Cannot find kill instruction");
509 SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
510 SrcLI.removeRange(LastUseIndex.getRegSlot(),
511 LIS->getMBBEndIdx(&opBlock));
517 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
518 if (reusedIncoming || !IncomingReg) {
520 LIS->RemoveMachineInstrFromMaps(MPhi);
521 MF.DeleteMachineInstr(MPhi);
525 /// analyzePHINodes - Gather information about the PHI nodes in here. In
526 /// particular, we want to map the number of uses of a virtual register which is
527 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
528 /// used later to determine when the vreg is killed in the BB.
530 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
531 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
533 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
534 BBI != BBE && BBI->isPHI(); ++BBI)
535 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
536 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(),
537 BBI->getOperand(i).getReg())];
540 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
541 MachineBasicBlock &MBB,
542 MachineLoopInfo *MLI) {
543 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
544 return false; // Quick exit for basic blocks without PHIs.
546 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : 0;
547 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
549 bool Changed = false;
550 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
551 BBI != BBE && BBI->isPHI(); ++BBI) {
552 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
553 unsigned Reg = BBI->getOperand(i).getReg();
554 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
555 // Is there a critical edge from PreMBB to MBB?
556 if (PreMBB->succ_size() == 1)
559 // Avoid splitting backedges of loops. It would introduce small
560 // out-of-line blocks into the loop which is very bad for code placement.
561 if (PreMBB == &MBB && !SplitAllCriticalEdges)
563 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : 0;
564 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
567 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
568 // when the source register is live-out for some other reason than a phi
569 // use. That means the copy we will insert in PreMBB won't be a kill, and
570 // there is a risk it may not be coalesced away.
572 // If the copy would be a kill, there is no need to split the edge.
573 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges)
576 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
577 << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
580 // If Reg is not live-in to MBB, it means it must be live-in to some
581 // other PreMBB successor, and we can avoid the interference by splitting
584 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
585 // is likely to be left after coalescing. If we are looking at a loop
586 // exiting edge, split it so we won't insert code in the loop, otherwise
588 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges;
590 // Check for a loop exiting edge.
591 if (!ShouldSplit && CurLoop != PreLoop) {
593 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
594 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
595 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
597 // This edge could be entering a loop, exiting a loop, or it could be
598 // both: Jumping directly form one loop to the header of a sibling
600 // Split unless this edge is entering CurLoop from an outer loop.
601 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
605 if (!PreMBB->SplitCriticalEdge(&MBB, this)) {
606 DEBUG(dbgs() << "Failed to split ciritcal edge.\n");
610 ++NumCriticalEdgesSplit;
616 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) {
617 assert((LV || LIS) &&
618 "isLiveIn() requires either LiveVariables or LiveIntervals");
620 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
622 return LV->isLiveIn(Reg, *MBB);
625 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) {
626 assert((LV || LIS) &&
627 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
628 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
629 // so that a register used only in a PHI is not live out of the block. In
630 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
631 // in the predecessor basic block, so that a register used only in a PHI is live
634 const LiveInterval &LI = LIS->getInterval(Reg);
635 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
636 SE = MBB->succ_end(); SI != SE; ++SI) {
637 if (LI.liveAt(LIS->getMBBStartIdx(*SI)))
642 return LV->isLiveOut(Reg, *MBB);