1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/CodeGen/Passes.h"
17 #include "PHIEliminationUtils.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineLoopInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetSubtargetInfo.h"
37 #define DEBUG_TYPE "phielim"
40 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
41 cl::Hidden, cl::desc("Disable critical edge splitting "
42 "during PHI elimination"));
45 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
46 cl::Hidden, cl::desc("Split all critical edges during "
49 static cl::opt<bool> NoPhiElimLiveOutEarlyExit(
50 "no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden,
51 cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
54 class PHIElimination : public MachineFunctionPass {
55 MachineRegisterInfo *MRI; // Machine register information
60 static char ID; // Pass identification, replacement for typeid
61 PHIElimination() : MachineFunctionPass(ID) {
62 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
65 bool runOnMachineFunction(MachineFunction &Fn) override;
66 void getAnalysisUsage(AnalysisUsage &AU) const override;
69 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
70 /// in predecessor basic blocks.
72 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
73 void LowerPHINode(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator LastPHIIt);
76 /// analyzePHINodes - Gather information about the PHI nodes in
77 /// here. In particular, we want to map the number of uses of a virtual
78 /// register which is used in a PHI node. We map that to the BB the
79 /// vreg is coming from. This is used later to determine when the vreg
80 /// is killed in the BB.
82 void analyzePHINodes(const MachineFunction& Fn);
84 /// Split critical edges where necessary for good coalescer performance.
85 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
86 MachineLoopInfo *MLI);
88 // These functions are temporary abstractions around LiveVariables and
89 // LiveIntervals, so they can go away when LiveVariables does.
90 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB);
91 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB);
93 typedef std::pair<unsigned, unsigned> BBVRegPair;
94 typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
96 VRegPHIUse VRegPHIUseCount;
98 // Defs of PHI sources which are implicit_def.
99 SmallPtrSet<MachineInstr*, 4> ImpDefs;
101 // Map reusable lowered PHI node -> incoming join register.
102 typedef DenseMap<MachineInstr*, unsigned,
103 MachineInstrExpressionTrait> LoweredPHIMap;
104 LoweredPHIMap LoweredPHIs;
108 STATISTIC(NumLowered, "Number of phis lowered");
109 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
110 STATISTIC(NumReused, "Number of reused lowered phis");
112 char PHIElimination::ID = 0;
113 char& llvm::PHIEliminationID = PHIElimination::ID;
115 INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
116 "Eliminate PHI nodes for register allocation",
118 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
119 INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
120 "Eliminate PHI nodes for register allocation", false, false)
122 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
123 AU.addPreserved<LiveVariables>();
124 AU.addPreserved<SlotIndexes>();
125 AU.addPreserved<LiveIntervals>();
126 AU.addPreserved<MachineDominatorTree>();
127 AU.addPreserved<MachineLoopInfo>();
128 MachineFunctionPass::getAnalysisUsage(AU);
131 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
132 MRI = &MF.getRegInfo();
133 LV = getAnalysisIfAvailable<LiveVariables>();
134 LIS = getAnalysisIfAvailable<LiveIntervals>();
136 bool Changed = false;
138 // This pass takes the function out of SSA form.
141 // Split critical edges to help the coalescer. This does not yet support
142 // updating LiveIntervals, so we disable it.
143 if (!DisableEdgeSplitting && (LV || LIS)) {
144 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
145 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
146 Changed |= SplitPHIEdges(MF, *I, MLI);
149 // Populate VRegPHIUseCount
152 // Eliminate PHI instructions by inserting copies into predecessor blocks.
153 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
154 Changed |= EliminatePHINodes(MF, *I);
156 // Remove dead IMPLICIT_DEF instructions.
157 for (MachineInstr *DefMI : ImpDefs) {
158 unsigned DefReg = DefMI->getOperand(0).getReg();
159 if (MRI->use_nodbg_empty(DefReg)) {
161 LIS->RemoveMachineInstrFromMaps(DefMI);
162 DefMI->eraseFromParent();
166 // Clean up the lowered PHI instructions.
167 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
170 LIS->RemoveMachineInstrFromMaps(I->first);
171 MF.DeleteMachineInstr(I->first);
176 VRegPHIUseCount.clear();
181 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
182 /// predecessor basic blocks.
184 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
185 MachineBasicBlock &MBB) {
186 if (MBB.empty() || !MBB.front().isPHI())
187 return false; // Quick exit for basic blocks without PHIs.
189 // Get an iterator to the first instruction after the last PHI node (this may
190 // also be the end of the basic block).
191 MachineBasicBlock::iterator LastPHIIt =
192 std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
194 while (MBB.front().isPHI())
195 LowerPHINode(MBB, LastPHIIt);
200 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
201 /// This includes registers with no defs.
202 static bool isImplicitlyDefined(unsigned VirtReg,
203 const MachineRegisterInfo *MRI) {
204 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
205 if (!DI.isImplicitDef())
210 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
211 /// are implicit_def's.
212 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
213 const MachineRegisterInfo *MRI) {
214 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
215 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
221 /// LowerPHINode - Lower the PHI node at the top of the specified block,
223 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
224 MachineBasicBlock::iterator LastPHIIt) {
227 MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
229 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
230 MachineInstr *MPhi = MBB.remove(MBB.begin());
232 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
233 unsigned DestReg = MPhi->getOperand(0).getReg();
234 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
235 bool isDead = MPhi->getOperand(0).isDead();
237 // Create a new register for the incoming PHI arguments.
238 MachineFunction &MF = *MBB.getParent();
239 unsigned IncomingReg = 0;
240 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
242 // Insert a register to register copy at the top of the current block (but
243 // after any remaining phi nodes) which copies the new incoming register
244 // into the phi node destination.
245 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
246 if (isSourceDefinedByImplicitDef(MPhi, MRI))
247 // If all sources of a PHI node are implicit_def, just emit an
248 // implicit_def instead of a copy.
249 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
250 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
252 // Can we reuse an earlier PHI node? This only happens for critical edges,
253 // typically those created by tail duplication.
254 unsigned &entry = LoweredPHIs[MPhi];
256 // An identical PHI node was already lowered. Reuse the incoming register.
258 reusedIncoming = true;
260 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
262 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
263 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
265 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
266 TII->get(TargetOpcode::COPY), DestReg)
267 .addReg(IncomingReg);
270 // Update live variable information if there is any.
272 MachineInstr *PHICopy = std::prev(AfterPHIsIt);
275 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
277 // Increment use count of the newly created virtual register.
278 LV->setPHIJoin(IncomingReg);
280 // When we are reusing the incoming register, it may already have been
281 // killed in this block. The old kill will also have been inserted at
282 // AfterPHIsIt, so it appears before the current PHICopy.
284 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
285 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
286 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
290 // Add information to LiveVariables to know that the incoming value is
291 // killed. Note that because the value is defined in several places (once
292 // each for each incoming block), the "def" block and instruction fields
293 // for the VarInfo is not filled in.
294 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
297 // Since we are going to be deleting the PHI node, if it is the last use of
298 // any registers, or if the value itself is dead, we need to move this
299 // information over to the new copy we just inserted.
300 LV->removeVirtualRegistersKilled(MPhi);
302 // If the result is dead, update LV.
304 LV->addVirtualRegisterDead(DestReg, PHICopy);
305 LV->removeVirtualRegisterDead(DestReg, MPhi);
309 // Update LiveIntervals for the new copy or implicit def.
311 MachineInstr *NewInstr = std::prev(AfterPHIsIt);
312 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
314 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
316 // Add the region from the beginning of MBB to the copy instruction to
317 // IncomingReg's live interval.
318 LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
319 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
321 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
322 LIS->getVNInfoAllocator());
323 IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
324 DestCopyIndex.getRegSlot(),
328 LiveInterval &DestLI = LIS->getInterval(DestReg);
329 assert(DestLI.begin() != DestLI.end() &&
330 "PHIs should have nonempty LiveIntervals.");
331 if (DestLI.endIndex().isDead()) {
332 // A dead PHI's live range begins and ends at the start of the MBB, but
333 // the lowered copy, which will still be dead, needs to begin and end at
334 // the copy instruction.
335 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
336 assert(OrigDestVNI && "PHI destination should be live at block entry.");
337 DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
338 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
339 LIS->getVNInfoAllocator());
340 DestLI.removeValNo(OrigDestVNI);
342 // Otherwise, remove the region from the beginning of MBB to the copy
343 // instruction from DestReg's live interval.
344 DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
345 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
346 assert(DestVNI && "PHI destination should be live at its definition.");
347 DestVNI->def = DestCopyIndex.getRegSlot();
351 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
352 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
353 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
354 MPhi->getOperand(i).getReg())];
356 // Now loop over all of the incoming arguments, changing them to copy into the
357 // IncomingReg register in the corresponding predecessor basic block.
358 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
359 for (int i = NumSrcs - 1; i >= 0; --i) {
360 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
361 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
362 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
363 isImplicitlyDefined(SrcReg, MRI);
364 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
365 "Machine PHI Operands must all be virtual registers!");
367 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
369 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
371 // Check to make sure we haven't already emitted the copy for this block.
372 // This can happen because PHI nodes may have multiple entries for the same
374 if (!MBBsInsertedInto.insert(&opBlock).second)
375 continue; // If the copy has already been emitted, we're done.
377 // Find a safe location to insert the copy, this may be the first terminator
378 // in the block (or end()).
379 MachineBasicBlock::iterator InsertPos =
380 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
383 MachineInstr *NewSrcInstr = nullptr;
384 if (!reusedIncoming && IncomingReg) {
386 // The source register is undefined, so there is no need for a real
387 // COPY, but we still need to ensure joint dominance by defs.
388 // Insert an IMPLICIT_DEF instruction.
389 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
390 TII->get(TargetOpcode::IMPLICIT_DEF),
393 // Clean up the old implicit-def, if there even was one.
394 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
395 if (DefMI->isImplicitDef())
396 ImpDefs.insert(DefMI);
398 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
399 TII->get(TargetOpcode::COPY), IncomingReg)
400 .addReg(SrcReg, 0, SrcSubReg);
404 // We only need to update the LiveVariables kill of SrcReg if this was the
405 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
406 // out of the predecessor. We can also ignore undef sources.
407 if (LV && !SrcUndef &&
408 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
409 !LV->isLiveOut(SrcReg, opBlock)) {
410 // We want to be able to insert a kill of the register if this PHI (aka,
411 // the copy we just inserted) is the last use of the source value. Live
412 // variable analysis conservatively handles this by saying that the value
413 // is live until the end of the block the PHI entry lives in. If the value
414 // really is dead at the PHI copy, there will be no successor blocks which
415 // have the value live-in.
417 // Okay, if we now know that the value is not live out of the block, we
418 // can add a kill marker in this block saying that it kills the incoming
421 // In our final twist, we have to decide which instruction kills the
422 // register. In most cases this is the copy, however, terminator
423 // instructions at the end of the block may also use the value. In this
424 // case, we should mark the last such terminator as being the killing
425 // block, not the copy.
426 MachineBasicBlock::iterator KillInst = opBlock.end();
427 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
428 for (MachineBasicBlock::iterator Term = FirstTerm;
429 Term != opBlock.end(); ++Term) {
430 if (Term->readsRegister(SrcReg))
434 if (KillInst == opBlock.end()) {
435 // No terminator uses the register.
437 if (reusedIncoming || !IncomingReg) {
438 // We may have to rewind a bit if we didn't insert a copy this time.
439 KillInst = FirstTerm;
440 while (KillInst != opBlock.begin()) {
442 if (KillInst->isDebugValue())
444 if (KillInst->readsRegister(SrcReg))
448 // We just inserted this copy.
449 KillInst = std::prev(InsertPos);
452 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
454 // Finally, mark it killed.
455 LV->addVirtualRegisterKilled(SrcReg, KillInst);
457 // This vreg no longer lives all of the way through opBlock.
458 unsigned opBlockNum = opBlock.getNumber();
459 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
464 LIS->InsertMachineInstrInMaps(NewSrcInstr);
465 LIS->addSegmentToEndOfBlock(IncomingReg, NewSrcInstr);
469 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
470 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
472 bool isLiveOut = false;
473 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
474 SE = opBlock.succ_end(); SI != SE; ++SI) {
475 SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
476 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
478 // Definitions by other PHIs are not truly live-in for our purposes.
479 if (VNI && VNI->def != startIdx) {
486 MachineBasicBlock::iterator KillInst = opBlock.end();
487 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
488 for (MachineBasicBlock::iterator Term = FirstTerm;
489 Term != opBlock.end(); ++Term) {
490 if (Term->readsRegister(SrcReg))
494 if (KillInst == opBlock.end()) {
495 // No terminator uses the register.
497 if (reusedIncoming || !IncomingReg) {
498 // We may have to rewind a bit if we didn't just insert a copy.
499 KillInst = FirstTerm;
500 while (KillInst != opBlock.begin()) {
502 if (KillInst->isDebugValue())
504 if (KillInst->readsRegister(SrcReg))
508 // We just inserted this copy.
509 KillInst = std::prev(InsertPos);
512 assert(KillInst->readsRegister(SrcReg) &&
513 "Cannot find kill instruction");
515 SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
516 SrcLI.removeSegment(LastUseIndex.getRegSlot(),
517 LIS->getMBBEndIdx(&opBlock));
523 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
524 if (reusedIncoming || !IncomingReg) {
526 LIS->RemoveMachineInstrFromMaps(MPhi);
527 MF.DeleteMachineInstr(MPhi);
531 /// analyzePHINodes - Gather information about the PHI nodes in here. In
532 /// particular, we want to map the number of uses of a virtual register which is
533 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
534 /// used later to determine when the vreg is killed in the BB.
536 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
537 for (const auto &MBB : MF)
538 for (const auto &BBI : MBB) {
541 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
542 ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
543 BBI.getOperand(i).getReg())];
547 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
548 MachineBasicBlock &MBB,
549 MachineLoopInfo *MLI) {
550 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
551 return false; // Quick exit for basic blocks without PHIs.
553 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr;
554 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
556 bool Changed = false;
557 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
558 BBI != BBE && BBI->isPHI(); ++BBI) {
559 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
560 unsigned Reg = BBI->getOperand(i).getReg();
561 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
562 // Is there a critical edge from PreMBB to MBB?
563 if (PreMBB->succ_size() == 1)
566 // Avoid splitting backedges of loops. It would introduce small
567 // out-of-line blocks into the loop which is very bad for code placement.
568 if (PreMBB == &MBB && !SplitAllCriticalEdges)
570 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
571 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
574 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
575 // when the source register is live-out for some other reason than a phi
576 // use. That means the copy we will insert in PreMBB won't be a kill, and
577 // there is a risk it may not be coalesced away.
579 // If the copy would be a kill, there is no need to split the edge.
580 bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
581 if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
584 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
585 << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
589 // If Reg is not live-in to MBB, it means it must be live-in to some
590 // other PreMBB successor, and we can avoid the interference by splitting
593 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
594 // is likely to be left after coalescing. If we are looking at a loop
595 // exiting edge, split it so we won't insert code in the loop, otherwise
597 ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);
599 // Check for a loop exiting edge.
600 if (!ShouldSplit && CurLoop != PreLoop) {
602 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
603 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
604 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
606 // This edge could be entering a loop, exiting a loop, or it could be
607 // both: Jumping directly form one loop to the header of a sibling
609 // Split unless this edge is entering CurLoop from an outer loop.
610 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
612 if (!ShouldSplit && !SplitAllCriticalEdges)
614 if (!PreMBB->SplitCriticalEdge(&MBB, this)) {
615 DEBUG(dbgs() << "Failed to split critical edge.\n");
619 ++NumCriticalEdgesSplit;
625 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) {
626 assert((LV || LIS) &&
627 "isLiveIn() requires either LiveVariables or LiveIntervals");
629 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
631 return LV->isLiveIn(Reg, *MBB);
634 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) {
635 assert((LV || LIS) &&
636 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
637 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
638 // so that a register used only in a PHI is not live out of the block. In
639 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
640 // in the predecessor basic block, so that a register used only in a PHI is live
643 const LiveInterval &LI = LIS->getInterval(Reg);
644 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
645 SE = MBB->succ_end(); SI != SE; ++SI) {
646 if (LI.liveAt(LIS->getMBBStartIdx(*SI)))
651 return LV->isLiveOut(Reg, *MBB);