1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "phielim"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Compiler.h"
33 STATISTIC(NumAtomic, "Number of atomic phis lowered");
36 class VISIBILITY_HIDDEN PNE : public MachineFunctionPass {
37 MachineRegisterInfo *MRI; // Machine register information
40 static char ID; // Pass identification, replacement for typeid
41 PNE() : MachineFunctionPass((intptr_t)&ID) {}
43 virtual bool runOnMachineFunction(MachineFunction &Fn);
45 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
46 AU.addPreserved<LiveVariables>();
47 AU.addPreservedID(MachineLoopInfoID);
48 AU.addPreservedID(MachineDominatorsID);
49 MachineFunctionPass::getAnalysisUsage(AU);
53 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
54 /// in predecessor basic blocks.
56 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
57 void LowerAtomicPHINode(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator AfterPHIsIt);
60 /// analyzePHINodes - Gather information about the PHI nodes in
61 /// here. In particular, we want to map the number of uses of a virtual
62 /// register which is used in a PHI node. We map that to the BB the
63 /// vreg is coming from. This is used later to determine when the vreg
64 /// is killed in the BB.
66 void analyzePHINodes(const MachineFunction& Fn);
68 typedef std::pair<const MachineBasicBlock*, unsigned> BBVRegPair;
69 typedef std::map<BBVRegPair, unsigned> VRegPHIUse;
71 VRegPHIUse VRegPHIUseCount;
73 // Defs of PHI sources which are implicit_def.
74 SmallPtrSet<MachineInstr*, 4> ImpDefs;
78 RegisterPass<PNE> X("phi-node-elimination",
79 "Eliminate PHI nodes for register allocation");
82 const PassInfo *llvm::PHIEliminationID = X.getPassInfo();
84 bool PNE::runOnMachineFunction(MachineFunction &Fn) {
85 MRI = &Fn.getRegInfo();
91 // Eliminate PHI instructions by inserting copies into predecessor blocks.
92 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
93 Changed |= EliminatePHINodes(Fn, *I);
95 // Remove dead IMPLICIT_DEF instructions.
96 for (SmallPtrSet<MachineInstr*,4>::iterator I = ImpDefs.begin(),
97 E = ImpDefs.end(); I != E; ++I) {
98 MachineInstr *DefMI = *I;
99 unsigned DefReg = DefMI->getOperand(0).getReg();
100 if (MRI->use_begin(DefReg) == MRI->use_end())
101 DefMI->eraseFromParent();
105 VRegPHIUseCount.clear();
110 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
111 /// predecessor basic blocks.
113 bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
114 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
115 return false; // Quick exit for basic blocks without PHIs.
117 // Get an iterator to the first instruction after the last PHI node (this may
118 // also be the end of the basic block).
119 MachineBasicBlock::iterator AfterPHIsIt = MBB.begin();
120 while (AfterPHIsIt != MBB.end() &&
121 AfterPHIsIt->getOpcode() == TargetInstrInfo::PHI)
122 ++AfterPHIsIt; // Skip over all of the PHI nodes...
124 while (MBB.front().getOpcode() == TargetInstrInfo::PHI)
125 LowerAtomicPHINode(MBB, AfterPHIsIt);
130 static bool isSourceDefinedByImplicitDef(MachineInstr *MPhi,
131 MachineRegisterInfo *MRI) {
132 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
133 unsigned SrcReg = MPhi->getOperand(i).getReg();
134 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
135 if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
141 /// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
142 /// under the assuption that it needs to be lowered in a way that supports
143 /// atomic execution of PHIs. This lowering method is always correct all of the
145 void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
146 MachineBasicBlock::iterator AfterPHIsIt) {
147 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
148 MachineInstr *MPhi = MBB.remove(MBB.begin());
150 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
151 unsigned DestReg = MPhi->getOperand(0).getReg();
153 // Create a new register for the incoming PHI arguments.
154 MachineFunction &MF = *MBB.getParent();
155 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
156 unsigned IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
158 // Insert a register to register copy in the top of the current block (but
159 // after any remaining phi nodes) which copies the new incoming register
160 // into the phi node destination.
162 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
163 if (isSourceDefinedByImplicitDef(MPhi, MRI))
164 // If all sources of a PHI node are implicit_def, just emit an implicit_def
165 // instead of a copy.
166 BuildMI(MBB, AfterPHIsIt, TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
168 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
170 // Update live variable information if there is any...
171 LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
173 MachineInstr *PHICopy = prior(AfterPHIsIt);
175 // Increment use count of the newly created virtual register.
176 LV->getVarInfo(IncomingReg).NumUses++;
178 // Add information to LiveVariables to know that the incoming value is
179 // killed. Note that because the value is defined in several places (once
180 // each for each incoming block), the "def" block and instruction fields
181 // for the VarInfo is not filled in.
183 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
185 // Since we are going to be deleting the PHI node, if it is the last use
186 // of any registers, or if the value itself is dead, we need to move this
187 // information over to the new copy we just inserted.
189 LV->removeVirtualRegistersKilled(MPhi);
191 // If the result is dead, update LV.
192 if (MPhi->registerDefIsDead(DestReg)) {
193 LV->addVirtualRegisterDead(DestReg, PHICopy);
194 LV->removeVirtualRegistersDead(MPhi);
197 LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true;
200 // Adjust the VRegPHIUseCount map to account for the removal of this PHI
202 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
203 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(),
204 MPhi->getOperand(i).getReg())];
206 // Now loop over all of the incoming arguments, changing them to copy into
207 // the IncomingReg register in the corresponding predecessor basic block.
209 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
210 for (int i = NumSrcs - 1; i >= 0; --i) {
211 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
212 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
213 "Machine PHI Operands must all be virtual registers!");
215 // If source is defined by an implicit def, there is no need to insert
216 // a copy unless it's the only source.
217 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
218 if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
219 ImpDefs.insert(DefMI);
223 // Get the MachineBasicBlock equivalent of the BasicBlock that is the
224 // source path the PHI.
225 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
227 // Check to make sure we haven't already emitted the copy for this block.
228 // This can happen because PHI nodes may have multiple entries for the
230 if (!MBBsInsertedInto.insert(&opBlock))
231 continue; // If the copy has already been emitted, we're done.
233 // Find a safe location to insert the copy, this may be the first
234 // terminator in the block (or end()).
235 MachineBasicBlock::iterator InsertPos = opBlock.getFirstTerminator();
238 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
240 // Now update live variable information if we have it. Otherwise we're done
243 // We want to be able to insert a kill of the register if this PHI
244 // (aka, the copy we just inserted) is the last use of the source
245 // value. Live variable analysis conservatively handles this by
246 // saying that the value is live until the end of the block the PHI
247 // entry lives in. If the value really is dead at the PHI copy, there
248 // will be no successor blocks which have the value live-in.
250 // Check to see if the copy is the last use, and if so, update the
251 // live variables information so that it knows the copy source
252 // instruction kills the incoming value.
254 LiveVariables::VarInfo &InRegVI = LV->getVarInfo(SrcReg);
255 InRegVI.UsedBlocks[opBlock.getNumber()] = true;
257 // Loop over all of the successors of the basic block, checking to see
258 // if the value is either live in the block, or if it is killed in the
259 // block. Also check to see if this register is in use by another PHI
260 // node which has not yet been eliminated. If so, it will be killed
261 // at an appropriate point later.
264 // Is it used by any PHI instructions in this block?
265 bool ValueIsLive = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0;
267 std::vector<MachineBasicBlock*> OpSuccBlocks;
269 // Otherwise, scan successors, including the BB the PHI node lives in.
270 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
271 E = opBlock.succ_end(); SI != E && !ValueIsLive; ++SI) {
272 MachineBasicBlock *SuccMBB = *SI;
274 // Is it alive in this successor?
275 unsigned SuccIdx = SuccMBB->getNumber();
276 if (SuccIdx < InRegVI.AliveBlocks.size() &&
277 InRegVI.AliveBlocks[SuccIdx]) {
282 OpSuccBlocks.push_back(SuccMBB);
285 // Check to see if this value is live because there is a use in a successor
288 switch (OpSuccBlocks.size()) {
290 MachineBasicBlock *MBB = OpSuccBlocks[0];
291 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
292 if (InRegVI.Kills[i]->getParent() == MBB) {
299 MachineBasicBlock *MBB1 = OpSuccBlocks[0], *MBB2 = OpSuccBlocks[1];
300 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
301 if (InRegVI.Kills[i]->getParent() == MBB1 ||
302 InRegVI.Kills[i]->getParent() == MBB2) {
309 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
310 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
311 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
312 InRegVI.Kills[i]->getParent())) {
319 // Okay, if we now know that the value is not live out of the block,
320 // we can add a kill marker in this block saying that it kills the incoming
323 // In our final twist, we have to decide which instruction kills the
324 // register. In most cases this is the copy, however, the first
325 // terminator instruction at the end of the block may also use the value.
326 // In this case, we should mark *it* as being the killing block, not the
328 MachineBasicBlock::iterator KillInst = prior(InsertPos);
329 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator();
330 if (Term != opBlock.end()) {
331 if (Term->readsRegister(SrcReg))
334 // Check that no other terminators use values.
336 for (MachineBasicBlock::iterator TI = next(Term); TI != opBlock.end();
338 assert(!TI->readsRegister(SrcReg) &&
339 "Terminator instructions cannot use virtual registers unless"
340 "they are the first terminator in a block!");
345 // Finally, mark it killed.
346 LV->addVirtualRegisterKilled(SrcReg, KillInst);
348 // This vreg no longer lives all of the way through opBlock.
349 unsigned opBlockNum = opBlock.getNumber();
350 if (opBlockNum < InRegVI.AliveBlocks.size())
351 InRegVI.AliveBlocks[opBlockNum] = false;
355 // Really delete the PHI instruction now!
360 /// analyzePHINodes - Gather information about the PHI nodes in here. In
361 /// particular, we want to map the number of uses of a virtual register which is
362 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
363 /// used later to determine when the vreg is killed in the BB.
365 void PNE::analyzePHINodes(const MachineFunction& Fn) {
366 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
368 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
369 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
370 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
371 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(),
372 BBI->getOperand(i).getReg())];