1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "phielim"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Compiler.h"
33 STATISTIC(NumAtomic, "Number of atomic phis lowered");
36 class VISIBILITY_HIDDEN PNE : public MachineFunctionPass {
37 MachineRegisterInfo *MRI; // Machine register information
40 static char ID; // Pass identification, replacement for typeid
41 PNE() : MachineFunctionPass((intptr_t)&ID) {}
43 virtual bool runOnMachineFunction(MachineFunction &Fn);
45 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
46 AU.addPreserved<LiveVariables>();
47 AU.addPreservedID(MachineLoopInfoID);
48 AU.addPreservedID(MachineDominatorsID);
49 MachineFunctionPass::getAnalysisUsage(AU);
53 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
54 /// in predecessor basic blocks.
56 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
57 void LowerAtomicPHINode(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator AfterPHIsIt);
60 /// analyzePHINodes - Gather information about the PHI nodes in
61 /// here. In particular, we want to map the number of uses of a virtual
62 /// register which is used in a PHI node. We map that to the BB the
63 /// vreg is coming from. This is used later to determine when the vreg
64 /// is killed in the BB.
66 void analyzePHINodes(const MachineFunction& Fn);
68 typedef std::pair<const MachineBasicBlock*, unsigned> BBVRegPair;
69 typedef std::map<BBVRegPair, unsigned> VRegPHIUse;
71 VRegPHIUse VRegPHIUseCount;
73 // Defs of PHI sources which are implicit_def.
74 SmallPtrSet<MachineInstr*, 4> ImpDefs;
79 static RegisterPass<PNE>
80 X("phi-node-elimination", "Eliminate PHI nodes for register allocation");
82 const PassInfo *const llvm::PHIEliminationID = &X;
84 bool PNE::runOnMachineFunction(MachineFunction &Fn) {
85 MRI = &Fn.getRegInfo();
91 // Eliminate PHI instructions by inserting copies into predecessor blocks.
92 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
93 Changed |= EliminatePHINodes(Fn, *I);
95 // Remove dead IMPLICIT_DEF instructions.
96 for (SmallPtrSet<MachineInstr*,4>::iterator I = ImpDefs.begin(),
97 E = ImpDefs.end(); I != E; ++I) {
98 MachineInstr *DefMI = *I;
99 unsigned DefReg = DefMI->getOperand(0).getReg();
100 if (MRI->use_empty(DefReg))
101 DefMI->eraseFromParent();
105 VRegPHIUseCount.clear();
110 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
111 /// predecessor basic blocks.
113 bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
114 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
115 return false; // Quick exit for basic blocks without PHIs.
117 // Get an iterator to the first instruction after the last PHI node (this may
118 // also be the end of the basic block).
119 MachineBasicBlock::iterator AfterPHIsIt = MBB.begin();
120 while (AfterPHIsIt != MBB.end() &&
121 AfterPHIsIt->getOpcode() == TargetInstrInfo::PHI)
122 ++AfterPHIsIt; // Skip over all of the PHI nodes...
124 while (MBB.front().getOpcode() == TargetInstrInfo::PHI)
125 LowerAtomicPHINode(MBB, AfterPHIsIt);
130 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
131 /// are implicit_def's.
132 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
133 const MachineRegisterInfo *MRI) {
134 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
135 unsigned SrcReg = MPhi->getOperand(i).getReg();
136 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
137 if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
143 /// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
144 /// under the assuption that it needs to be lowered in a way that supports
145 /// atomic execution of PHIs. This lowering method is always correct all of the
148 void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
149 MachineBasicBlock::iterator AfterPHIsIt) {
150 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
151 MachineInstr *MPhi = MBB.remove(MBB.begin());
153 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
154 unsigned DestReg = MPhi->getOperand(0).getReg();
156 // Create a new register for the incoming PHI arguments.
157 MachineFunction &MF = *MBB.getParent();
158 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
159 unsigned IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
161 // Insert a register to register copy at the top of the current block (but
162 // after any remaining phi nodes) which copies the new incoming register
163 // into the phi node destination.
164 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
165 if (isSourceDefinedByImplicitDef(MPhi, MRI))
166 // If all sources of a PHI node are implicit_def, just emit an implicit_def
167 // instead of a copy.
168 BuildMI(MBB, AfterPHIsIt, TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
170 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
172 // Update live variable information if there is any.
173 LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
175 MachineInstr *PHICopy = prior(AfterPHIsIt);
177 // Increment use count of the newly created virtual register.
178 LV->getVarInfo(IncomingReg).NumUses++;
180 // Add information to LiveVariables to know that the incoming value is
181 // killed. Note that because the value is defined in several places (once
182 // each for each incoming block), the "def" block and instruction fields for
183 // the VarInfo is not filled in.
184 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
186 // Since we are going to be deleting the PHI node, if it is the last use of
187 // any registers, or if the value itself is dead, we need to move this
188 // information over to the new copy we just inserted.
189 LV->removeVirtualRegistersKilled(MPhi);
191 // If the result is dead, update LV.
192 if (MPhi->registerDefIsDead(DestReg)) {
193 LV->addVirtualRegisterDead(DestReg, PHICopy);
194 LV->removeVirtualRegistersDead(MPhi);
197 LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true;
200 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
201 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
202 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(),
203 MPhi->getOperand(i).getReg())];
205 // Now loop over all of the incoming arguments, changing them to copy into the
206 // IncomingReg register in the corresponding predecessor basic block.
207 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
208 for (int i = NumSrcs - 1; i >= 0; --i) {
209 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
210 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
211 "Machine PHI Operands must all be virtual registers!");
213 // If source is defined by an implicit def, there is no need to insert a
214 // copy unless it's the only source.
215 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
216 if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
217 ImpDefs.insert(DefMI);
221 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
223 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
225 // Check to make sure we haven't already emitted the copy for this block.
226 // This can happen because PHI nodes may have multiple entries for the same
228 if (!MBBsInsertedInto.insert(&opBlock))
229 continue; // If the copy has already been emitted, we're done.
231 // Find a safe location to insert the copy, this may be the first terminator
232 // in the block (or end()).
233 MachineBasicBlock::iterator InsertPos = opBlock.getFirstTerminator();
236 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
238 // Now update live variable information if we have it. Otherwise we're done
241 // We want to be able to insert a kill of the register if this PHI (aka, the
242 // copy we just inserted) is the last use of the source value. Live
243 // variable analysis conservatively handles this by saying that the value is
244 // live until the end of the block the PHI entry lives in. If the value
245 // really is dead at the PHI copy, there will be no successor blocks which
246 // have the value live-in.
248 // Check to see if the copy is the last use, and if so, update the live
249 // variables information so that it knows the copy source instruction kills
250 // the incoming value.
251 LiveVariables::VarInfo &InRegVI = LV->getVarInfo(SrcReg);
252 InRegVI.UsedBlocks[opBlock.getNumber()] = true;
254 // Loop over all of the successors of the basic block, checking to see if
255 // the value is either live in the block, or if it is killed in the block.
256 // Also check to see if this register is in use by another PHI node which
257 // has not yet been eliminated. If so, it will be killed at an appropriate
260 // Is it used by any PHI instructions in this block?
261 bool ValueIsLive = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0;
263 std::vector<MachineBasicBlock*> OpSuccBlocks;
265 // Otherwise, scan successors, including the BB the PHI node lives in.
266 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
267 E = opBlock.succ_end(); SI != E && !ValueIsLive; ++SI) {
268 MachineBasicBlock *SuccMBB = *SI;
270 // Is it alive in this successor?
271 unsigned SuccIdx = SuccMBB->getNumber();
272 if (SuccIdx < InRegVI.AliveBlocks.size() &&
273 InRegVI.AliveBlocks[SuccIdx]) {
278 OpSuccBlocks.push_back(SuccMBB);
281 // Check to see if this value is live because there is a use in a successor
284 switch (OpSuccBlocks.size()) {
286 MachineBasicBlock *MBB = OpSuccBlocks[0];
287 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
288 if (InRegVI.Kills[i]->getParent() == MBB) {
295 MachineBasicBlock *MBB1 = OpSuccBlocks[0], *MBB2 = OpSuccBlocks[1];
296 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
297 if (InRegVI.Kills[i]->getParent() == MBB1 ||
298 InRegVI.Kills[i]->getParent() == MBB2) {
305 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
306 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
307 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
308 InRegVI.Kills[i]->getParent())) {
315 // Okay, if we now know that the value is not live out of the block, we can
316 // add a kill marker in this block saying that it kills the incoming value!
318 // In our final twist, we have to decide which instruction kills the
319 // register. In most cases this is the copy, however, the first
320 // terminator instruction at the end of the block may also use the value.
321 // In this case, we should mark *it* as being the killing block, not the
323 MachineBasicBlock::iterator KillInst = prior(InsertPos);
324 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator();
325 if (Term != opBlock.end()) {
326 if (Term->readsRegister(SrcReg))
329 // Check that no other terminators use values.
331 for (MachineBasicBlock::iterator TI = next(Term); TI != opBlock.end();
333 assert(!TI->readsRegister(SrcReg) &&
334 "Terminator instructions cannot use virtual registers unless"
335 "they are the first terminator in a block!");
340 // Finally, mark it killed.
341 LV->addVirtualRegisterKilled(SrcReg, KillInst);
343 // This vreg no longer lives all of the way through opBlock.
344 unsigned opBlockNum = opBlock.getNumber();
345 if (opBlockNum < InRegVI.AliveBlocks.size())
346 InRegVI.AliveBlocks[opBlockNum] = false;
350 // Really delete the PHI instruction now!
355 /// analyzePHINodes - Gather information about the PHI nodes in here. In
356 /// particular, we want to map the number of uses of a virtual register which is
357 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
358 /// used later to determine when the vreg is killed in the BB.
360 void PNE::analyzePHINodes(const MachineFunction& Fn) {
361 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
363 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
364 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
365 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
366 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(),
367 BBI->getOperand(i).getReg())];