1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/CodeGen/Passes.h"
17 #include "PHIEliminationUtils.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineLoopInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
38 #define DEBUG_TYPE "phielim"
41 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
42 cl::Hidden, cl::desc("Disable critical edge splitting "
43 "during PHI elimination"));
46 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
47 cl::Hidden, cl::desc("Split all critical edges during "
51 class PHIElimination : public MachineFunctionPass {
52 MachineRegisterInfo *MRI; // Machine register information
57 static char ID; // Pass identification, replacement for typeid
58 PHIElimination() : MachineFunctionPass(ID) {
59 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
62 bool runOnMachineFunction(MachineFunction &Fn) override;
63 void getAnalysisUsage(AnalysisUsage &AU) const override;
66 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
67 /// in predecessor basic blocks.
69 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
70 void LowerPHINode(MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator LastPHIIt);
73 /// analyzePHINodes - Gather information about the PHI nodes in
74 /// here. In particular, we want to map the number of uses of a virtual
75 /// register which is used in a PHI node. We map that to the BB the
76 /// vreg is coming from. This is used later to determine when the vreg
77 /// is killed in the BB.
79 void analyzePHINodes(const MachineFunction& Fn);
81 /// Split critical edges where necessary for good coalescer performance.
82 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
83 MachineLoopInfo *MLI);
85 // These functions are temporary abstractions around LiveVariables and
86 // LiveIntervals, so they can go away when LiveVariables does.
87 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB);
88 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB);
90 typedef std::pair<unsigned, unsigned> BBVRegPair;
91 typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
93 VRegPHIUse VRegPHIUseCount;
95 // Defs of PHI sources which are implicit_def.
96 SmallPtrSet<MachineInstr*, 4> ImpDefs;
98 // Map reusable lowered PHI node -> incoming join register.
99 typedef DenseMap<MachineInstr*, unsigned,
100 MachineInstrExpressionTrait> LoweredPHIMap;
101 LoweredPHIMap LoweredPHIs;
105 STATISTIC(NumLowered, "Number of phis lowered");
106 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
107 STATISTIC(NumReused, "Number of reused lowered phis");
109 char PHIElimination::ID = 0;
110 char& llvm::PHIEliminationID = PHIElimination::ID;
112 INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
113 "Eliminate PHI nodes for register allocation",
115 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
116 INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
117 "Eliminate PHI nodes for register allocation", false, false)
119 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
120 AU.addPreserved<LiveVariables>();
121 AU.addPreserved<SlotIndexes>();
122 AU.addPreserved<LiveIntervals>();
123 AU.addPreserved<MachineDominatorTree>();
124 AU.addPreserved<MachineLoopInfo>();
125 MachineFunctionPass::getAnalysisUsage(AU);
128 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
129 MRI = &MF.getRegInfo();
130 LV = getAnalysisIfAvailable<LiveVariables>();
131 LIS = getAnalysisIfAvailable<LiveIntervals>();
133 bool Changed = false;
135 // This pass takes the function out of SSA form.
138 // Split critical edges to help the coalescer. This does not yet support
139 // updating LiveIntervals, so we disable it.
140 if (!DisableEdgeSplitting && (LV || LIS)) {
141 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
142 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
143 Changed |= SplitPHIEdges(MF, *I, MLI);
146 // Populate VRegPHIUseCount
149 // Eliminate PHI instructions by inserting copies into predecessor blocks.
150 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
151 Changed |= EliminatePHINodes(MF, *I);
153 // Remove dead IMPLICIT_DEF instructions.
154 for (MachineInstr *DefMI : ImpDefs) {
155 unsigned DefReg = DefMI->getOperand(0).getReg();
156 if (MRI->use_nodbg_empty(DefReg)) {
158 LIS->RemoveMachineInstrFromMaps(DefMI);
159 DefMI->eraseFromParent();
163 // Clean up the lowered PHI instructions.
164 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
167 LIS->RemoveMachineInstrFromMaps(I->first);
168 MF.DeleteMachineInstr(I->first);
173 VRegPHIUseCount.clear();
178 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
179 /// predecessor basic blocks.
181 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
182 MachineBasicBlock &MBB) {
183 if (MBB.empty() || !MBB.front().isPHI())
184 return false; // Quick exit for basic blocks without PHIs.
186 // Get an iterator to the first instruction after the last PHI node (this may
187 // also be the end of the basic block).
188 MachineBasicBlock::iterator LastPHIIt =
189 std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
191 while (MBB.front().isPHI())
192 LowerPHINode(MBB, LastPHIIt);
197 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
198 /// This includes registers with no defs.
199 static bool isImplicitlyDefined(unsigned VirtReg,
200 const MachineRegisterInfo *MRI) {
201 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
202 if (!DI.isImplicitDef())
207 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
208 /// are implicit_def's.
209 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
210 const MachineRegisterInfo *MRI) {
211 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
212 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
218 /// LowerPHINode - Lower the PHI node at the top of the specified block,
220 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
221 MachineBasicBlock::iterator LastPHIIt) {
224 MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
226 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
227 MachineInstr *MPhi = MBB.remove(MBB.begin());
229 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
230 unsigned DestReg = MPhi->getOperand(0).getReg();
231 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
232 bool isDead = MPhi->getOperand(0).isDead();
234 // Create a new register for the incoming PHI arguments.
235 MachineFunction &MF = *MBB.getParent();
236 unsigned IncomingReg = 0;
237 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
239 // Insert a register to register copy at the top of the current block (but
240 // after any remaining phi nodes) which copies the new incoming register
241 // into the phi node destination.
242 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
243 if (isSourceDefinedByImplicitDef(MPhi, MRI))
244 // If all sources of a PHI node are implicit_def, just emit an
245 // implicit_def instead of a copy.
246 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
247 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
249 // Can we reuse an earlier PHI node? This only happens for critical edges,
250 // typically those created by tail duplication.
251 unsigned &entry = LoweredPHIs[MPhi];
253 // An identical PHI node was already lowered. Reuse the incoming register.
255 reusedIncoming = true;
257 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
259 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
260 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
262 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
263 TII->get(TargetOpcode::COPY), DestReg)
264 .addReg(IncomingReg);
267 // Update live variable information if there is any.
269 MachineInstr *PHICopy = std::prev(AfterPHIsIt);
272 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
274 // Increment use count of the newly created virtual register.
275 LV->setPHIJoin(IncomingReg);
277 // When we are reusing the incoming register, it may already have been
278 // killed in this block. The old kill will also have been inserted at
279 // AfterPHIsIt, so it appears before the current PHICopy.
281 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
282 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
283 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
287 // Add information to LiveVariables to know that the incoming value is
288 // killed. Note that because the value is defined in several places (once
289 // each for each incoming block), the "def" block and instruction fields
290 // for the VarInfo is not filled in.
291 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
294 // Since we are going to be deleting the PHI node, if it is the last use of
295 // any registers, or if the value itself is dead, we need to move this
296 // information over to the new copy we just inserted.
297 LV->removeVirtualRegistersKilled(MPhi);
299 // If the result is dead, update LV.
301 LV->addVirtualRegisterDead(DestReg, PHICopy);
302 LV->removeVirtualRegisterDead(DestReg, MPhi);
306 // Update LiveIntervals for the new copy or implicit def.
308 MachineInstr *NewInstr = std::prev(AfterPHIsIt);
309 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
311 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
313 // Add the region from the beginning of MBB to the copy instruction to
314 // IncomingReg's live interval.
315 LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
316 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
318 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
319 LIS->getVNInfoAllocator());
320 IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
321 DestCopyIndex.getRegSlot(),
325 LiveInterval &DestLI = LIS->getInterval(DestReg);
326 assert(DestLI.begin() != DestLI.end() &&
327 "PHIs should have nonempty LiveIntervals.");
328 if (DestLI.endIndex().isDead()) {
329 // A dead PHI's live range begins and ends at the start of the MBB, but
330 // the lowered copy, which will still be dead, needs to begin and end at
331 // the copy instruction.
332 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
333 assert(OrigDestVNI && "PHI destination should be live at block entry.");
334 DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
335 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
336 LIS->getVNInfoAllocator());
337 DestLI.removeValNo(OrigDestVNI);
339 // Otherwise, remove the region from the beginning of MBB to the copy
340 // instruction from DestReg's live interval.
341 DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
342 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
343 assert(DestVNI && "PHI destination should be live at its definition.");
344 DestVNI->def = DestCopyIndex.getRegSlot();
348 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
349 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
350 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
351 MPhi->getOperand(i).getReg())];
353 // Now loop over all of the incoming arguments, changing them to copy into the
354 // IncomingReg register in the corresponding predecessor basic block.
355 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
356 for (int i = NumSrcs - 1; i >= 0; --i) {
357 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
358 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
359 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
360 isImplicitlyDefined(SrcReg, MRI);
361 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
362 "Machine PHI Operands must all be virtual registers!");
364 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
366 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
368 // Check to make sure we haven't already emitted the copy for this block.
369 // This can happen because PHI nodes may have multiple entries for the same
371 if (!MBBsInsertedInto.insert(&opBlock))
372 continue; // If the copy has already been emitted, we're done.
374 // Find a safe location to insert the copy, this may be the first terminator
375 // in the block (or end()).
376 MachineBasicBlock::iterator InsertPos =
377 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
380 MachineInstr *NewSrcInstr = nullptr;
381 if (!reusedIncoming && IncomingReg) {
383 // The source register is undefined, so there is no need for a real
384 // COPY, but we still need to ensure joint dominance by defs.
385 // Insert an IMPLICIT_DEF instruction.
386 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
387 TII->get(TargetOpcode::IMPLICIT_DEF),
390 // Clean up the old implicit-def, if there even was one.
391 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
392 if (DefMI->isImplicitDef())
393 ImpDefs.insert(DefMI);
395 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
396 TII->get(TargetOpcode::COPY), IncomingReg)
397 .addReg(SrcReg, 0, SrcSubReg);
401 // We only need to update the LiveVariables kill of SrcReg if this was the
402 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
403 // out of the predecessor. We can also ignore undef sources.
404 if (LV && !SrcUndef &&
405 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
406 !LV->isLiveOut(SrcReg, opBlock)) {
407 // We want to be able to insert a kill of the register if this PHI (aka,
408 // the copy we just inserted) is the last use of the source value. Live
409 // variable analysis conservatively handles this by saying that the value
410 // is live until the end of the block the PHI entry lives in. If the value
411 // really is dead at the PHI copy, there will be no successor blocks which
412 // have the value live-in.
414 // Okay, if we now know that the value is not live out of the block, we
415 // can add a kill marker in this block saying that it kills the incoming
418 // In our final twist, we have to decide which instruction kills the
419 // register. In most cases this is the copy, however, terminator
420 // instructions at the end of the block may also use the value. In this
421 // case, we should mark the last such terminator as being the killing
422 // block, not the copy.
423 MachineBasicBlock::iterator KillInst = opBlock.end();
424 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
425 for (MachineBasicBlock::iterator Term = FirstTerm;
426 Term != opBlock.end(); ++Term) {
427 if (Term->readsRegister(SrcReg))
431 if (KillInst == opBlock.end()) {
432 // No terminator uses the register.
434 if (reusedIncoming || !IncomingReg) {
435 // We may have to rewind a bit if we didn't insert a copy this time.
436 KillInst = FirstTerm;
437 while (KillInst != opBlock.begin()) {
439 if (KillInst->isDebugValue())
441 if (KillInst->readsRegister(SrcReg))
445 // We just inserted this copy.
446 KillInst = std::prev(InsertPos);
449 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
451 // Finally, mark it killed.
452 LV->addVirtualRegisterKilled(SrcReg, KillInst);
454 // This vreg no longer lives all of the way through opBlock.
455 unsigned opBlockNum = opBlock.getNumber();
456 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
461 LIS->InsertMachineInstrInMaps(NewSrcInstr);
462 LIS->addSegmentToEndOfBlock(IncomingReg, NewSrcInstr);
466 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
467 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
469 bool isLiveOut = false;
470 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
471 SE = opBlock.succ_end(); SI != SE; ++SI) {
472 SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
473 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
475 // Definitions by other PHIs are not truly live-in for our purposes.
476 if (VNI && VNI->def != startIdx) {
483 MachineBasicBlock::iterator KillInst = opBlock.end();
484 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
485 for (MachineBasicBlock::iterator Term = FirstTerm;
486 Term != opBlock.end(); ++Term) {
487 if (Term->readsRegister(SrcReg))
491 if (KillInst == opBlock.end()) {
492 // No terminator uses the register.
494 if (reusedIncoming || !IncomingReg) {
495 // We may have to rewind a bit if we didn't just insert a copy.
496 KillInst = FirstTerm;
497 while (KillInst != opBlock.begin()) {
499 if (KillInst->isDebugValue())
501 if (KillInst->readsRegister(SrcReg))
505 // We just inserted this copy.
506 KillInst = std::prev(InsertPos);
509 assert(KillInst->readsRegister(SrcReg) &&
510 "Cannot find kill instruction");
512 SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
513 SrcLI.removeSegment(LastUseIndex.getRegSlot(),
514 LIS->getMBBEndIdx(&opBlock));
520 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
521 if (reusedIncoming || !IncomingReg) {
523 LIS->RemoveMachineInstrFromMaps(MPhi);
524 MF.DeleteMachineInstr(MPhi);
528 /// analyzePHINodes - Gather information about the PHI nodes in here. In
529 /// particular, we want to map the number of uses of a virtual register which is
530 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
531 /// used later to determine when the vreg is killed in the BB.
533 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
534 for (const auto &MBB : MF)
535 for (const auto &BBI : MBB) {
538 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
539 ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
540 BBI.getOperand(i).getReg())];
544 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
545 MachineBasicBlock &MBB,
546 MachineLoopInfo *MLI) {
547 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
548 return false; // Quick exit for basic blocks without PHIs.
550 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr;
551 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
553 bool Changed = false;
554 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
555 BBI != BBE && BBI->isPHI(); ++BBI) {
556 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
557 unsigned Reg = BBI->getOperand(i).getReg();
558 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
559 // Is there a critical edge from PreMBB to MBB?
560 if (PreMBB->succ_size() == 1)
563 // Avoid splitting backedges of loops. It would introduce small
564 // out-of-line blocks into the loop which is very bad for code placement.
565 if (PreMBB == &MBB && !SplitAllCriticalEdges)
567 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
568 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
571 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
572 // when the source register is live-out for some other reason than a phi
573 // use. That means the copy we will insert in PreMBB won't be a kill, and
574 // there is a risk it may not be coalesced away.
576 // If the copy would be a kill, there is no need to split the edge.
577 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges)
580 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
581 << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
584 // If Reg is not live-in to MBB, it means it must be live-in to some
585 // other PreMBB successor, and we can avoid the interference by splitting
588 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
589 // is likely to be left after coalescing. If we are looking at a loop
590 // exiting edge, split it so we won't insert code in the loop, otherwise
592 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges;
594 // Check for a loop exiting edge.
595 if (!ShouldSplit && CurLoop != PreLoop) {
597 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
598 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
599 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
601 // This edge could be entering a loop, exiting a loop, or it could be
602 // both: Jumping directly form one loop to the header of a sibling
604 // Split unless this edge is entering CurLoop from an outer loop.
605 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
609 if (!PreMBB->SplitCriticalEdge(&MBB, this)) {
610 DEBUG(dbgs() << "Failed to split critical edge.\n");
614 ++NumCriticalEdgesSplit;
620 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) {
621 assert((LV || LIS) &&
622 "isLiveIn() requires either LiveVariables or LiveIntervals");
624 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
626 return LV->isLiveIn(Reg, *MBB);
629 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) {
630 assert((LV || LIS) &&
631 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
632 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
633 // so that a register used only in a PHI is not live out of the block. In
634 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
635 // in the predecessor basic block, so that a register used only in a PHI is live
638 const LiveInterval &LI = LIS->getInterval(Reg);
639 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
640 SE = MBB->succ_end(); SI != SE; ++SI) {
641 if (LI.liveAt(LIS->getMBBStartIdx(*SI)))
646 return LV->isLiveOut(Reg, *MBB);