1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "phielim"
17 #include "llvm/CodeGen/Passes.h"
18 #include "PHIEliminationUtils.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
39 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
40 cl::Hidden, cl::desc("Disable critical edge splitting "
41 "during PHI elimination"));
44 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
45 cl::Hidden, cl::desc("Split all critical edges during "
49 class PHIElimination : public MachineFunctionPass {
50 MachineRegisterInfo *MRI; // Machine register information
55 static char ID; // Pass identification, replacement for typeid
56 PHIElimination() : MachineFunctionPass(ID) {
57 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
60 bool runOnMachineFunction(MachineFunction &Fn) override;
61 void getAnalysisUsage(AnalysisUsage &AU) const override;
64 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
65 /// in predecessor basic blocks.
67 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
68 void LowerPHINode(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator LastPHIIt);
71 /// analyzePHINodes - Gather information about the PHI nodes in
72 /// here. In particular, we want to map the number of uses of a virtual
73 /// register which is used in a PHI node. We map that to the BB the
74 /// vreg is coming from. This is used later to determine when the vreg
75 /// is killed in the BB.
77 void analyzePHINodes(const MachineFunction& Fn);
79 /// Split critical edges where necessary for good coalescer performance.
80 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
81 MachineLoopInfo *MLI);
83 // These functions are temporary abstractions around LiveVariables and
84 // LiveIntervals, so they can go away when LiveVariables does.
85 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB);
86 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB);
88 typedef std::pair<unsigned, unsigned> BBVRegPair;
89 typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
91 VRegPHIUse VRegPHIUseCount;
93 // Defs of PHI sources which are implicit_def.
94 SmallPtrSet<MachineInstr*, 4> ImpDefs;
96 // Map reusable lowered PHI node -> incoming join register.
97 typedef DenseMap<MachineInstr*, unsigned,
98 MachineInstrExpressionTrait> LoweredPHIMap;
99 LoweredPHIMap LoweredPHIs;
103 STATISTIC(NumLowered, "Number of phis lowered");
104 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
105 STATISTIC(NumReused, "Number of reused lowered phis");
107 char PHIElimination::ID = 0;
108 char& llvm::PHIEliminationID = PHIElimination::ID;
110 INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
111 "Eliminate PHI nodes for register allocation",
113 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
114 INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
115 "Eliminate PHI nodes for register allocation", false, false)
117 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
118 AU.addPreserved<LiveVariables>();
119 AU.addPreserved<SlotIndexes>();
120 AU.addPreserved<LiveIntervals>();
121 AU.addPreserved<MachineDominatorTree>();
122 AU.addPreserved<MachineLoopInfo>();
123 MachineFunctionPass::getAnalysisUsage(AU);
126 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
127 MRI = &MF.getRegInfo();
128 LV = getAnalysisIfAvailable<LiveVariables>();
129 LIS = getAnalysisIfAvailable<LiveIntervals>();
131 bool Changed = false;
133 // This pass takes the function out of SSA form.
136 // Split critical edges to help the coalescer. This does not yet support
137 // updating LiveIntervals, so we disable it.
138 if (!DisableEdgeSplitting && (LV || LIS)) {
139 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
140 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
141 Changed |= SplitPHIEdges(MF, *I, MLI);
144 // Populate VRegPHIUseCount
147 // Eliminate PHI instructions by inserting copies into predecessor blocks.
148 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
149 Changed |= EliminatePHINodes(MF, *I);
151 // Remove dead IMPLICIT_DEF instructions.
152 for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(),
153 E = ImpDefs.end(); I != E; ++I) {
154 MachineInstr *DefMI = *I;
155 unsigned DefReg = DefMI->getOperand(0).getReg();
156 if (MRI->use_nodbg_empty(DefReg)) {
158 LIS->RemoveMachineInstrFromMaps(DefMI);
159 DefMI->eraseFromParent();
163 // Clean up the lowered PHI instructions.
164 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
167 LIS->RemoveMachineInstrFromMaps(I->first);
168 MF.DeleteMachineInstr(I->first);
173 VRegPHIUseCount.clear();
178 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
179 /// predecessor basic blocks.
181 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
182 MachineBasicBlock &MBB) {
183 if (MBB.empty() || !MBB.front().isPHI())
184 return false; // Quick exit for basic blocks without PHIs.
186 // Get an iterator to the first instruction after the last PHI node (this may
187 // also be the end of the basic block).
188 MachineBasicBlock::iterator LastPHIIt =
189 std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
191 while (MBB.front().isPHI())
192 LowerPHINode(MBB, LastPHIIt);
197 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
198 /// This includes registers with no defs.
199 static bool isImplicitlyDefined(unsigned VirtReg,
200 const MachineRegisterInfo *MRI) {
201 for (MachineRegisterInfo::def_instr_iterator
202 DI = MRI->def_instr_begin(VirtReg), DE = MRI->def_instr_end();
204 if (!DI->isImplicitDef())
209 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
210 /// are implicit_def's.
211 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
212 const MachineRegisterInfo *MRI) {
213 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
214 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
220 /// LowerPHINode - Lower the PHI node at the top of the specified block,
222 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
223 MachineBasicBlock::iterator LastPHIIt) {
226 MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
228 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
229 MachineInstr *MPhi = MBB.remove(MBB.begin());
231 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
232 unsigned DestReg = MPhi->getOperand(0).getReg();
233 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
234 bool isDead = MPhi->getOperand(0).isDead();
236 // Create a new register for the incoming PHI arguments.
237 MachineFunction &MF = *MBB.getParent();
238 unsigned IncomingReg = 0;
239 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
241 // Insert a register to register copy at the top of the current block (but
242 // after any remaining phi nodes) which copies the new incoming register
243 // into the phi node destination.
244 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
245 if (isSourceDefinedByImplicitDef(MPhi, MRI))
246 // If all sources of a PHI node are implicit_def, just emit an
247 // implicit_def instead of a copy.
248 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
249 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
251 // Can we reuse an earlier PHI node? This only happens for critical edges,
252 // typically those created by tail duplication.
253 unsigned &entry = LoweredPHIs[MPhi];
255 // An identical PHI node was already lowered. Reuse the incoming register.
257 reusedIncoming = true;
259 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
261 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
262 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
264 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
265 TII->get(TargetOpcode::COPY), DestReg)
266 .addReg(IncomingReg);
269 // Update live variable information if there is any.
271 MachineInstr *PHICopy = std::prev(AfterPHIsIt);
274 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
276 // Increment use count of the newly created virtual register.
277 LV->setPHIJoin(IncomingReg);
279 // When we are reusing the incoming register, it may already have been
280 // killed in this block. The old kill will also have been inserted at
281 // AfterPHIsIt, so it appears before the current PHICopy.
283 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
284 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
285 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
289 // Add information to LiveVariables to know that the incoming value is
290 // killed. Note that because the value is defined in several places (once
291 // each for each incoming block), the "def" block and instruction fields
292 // for the VarInfo is not filled in.
293 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
296 // Since we are going to be deleting the PHI node, if it is the last use of
297 // any registers, or if the value itself is dead, we need to move this
298 // information over to the new copy we just inserted.
299 LV->removeVirtualRegistersKilled(MPhi);
301 // If the result is dead, update LV.
303 LV->addVirtualRegisterDead(DestReg, PHICopy);
304 LV->removeVirtualRegisterDead(DestReg, MPhi);
308 // Update LiveIntervals for the new copy or implicit def.
310 MachineInstr *NewInstr = std::prev(AfterPHIsIt);
311 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
313 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
315 // Add the region from the beginning of MBB to the copy instruction to
316 // IncomingReg's live interval.
317 LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
318 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
320 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
321 LIS->getVNInfoAllocator());
322 IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
323 DestCopyIndex.getRegSlot(),
327 LiveInterval &DestLI = LIS->getInterval(DestReg);
328 assert(DestLI.begin() != DestLI.end() &&
329 "PHIs should have nonempty LiveIntervals.");
330 if (DestLI.endIndex().isDead()) {
331 // A dead PHI's live range begins and ends at the start of the MBB, but
332 // the lowered copy, which will still be dead, needs to begin and end at
333 // the copy instruction.
334 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
335 assert(OrigDestVNI && "PHI destination should be live at block entry.");
336 DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
337 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
338 LIS->getVNInfoAllocator());
339 DestLI.removeValNo(OrigDestVNI);
341 // Otherwise, remove the region from the beginning of MBB to the copy
342 // instruction from DestReg's live interval.
343 DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
344 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
345 assert(DestVNI && "PHI destination should be live at its definition.");
346 DestVNI->def = DestCopyIndex.getRegSlot();
350 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
351 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
352 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
353 MPhi->getOperand(i).getReg())];
355 // Now loop over all of the incoming arguments, changing them to copy into the
356 // IncomingReg register in the corresponding predecessor basic block.
357 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
358 for (int i = NumSrcs - 1; i >= 0; --i) {
359 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
360 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
361 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
362 isImplicitlyDefined(SrcReg, MRI);
363 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
364 "Machine PHI Operands must all be virtual registers!");
366 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
368 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
370 // Check to make sure we haven't already emitted the copy for this block.
371 // This can happen because PHI nodes may have multiple entries for the same
373 if (!MBBsInsertedInto.insert(&opBlock))
374 continue; // If the copy has already been emitted, we're done.
376 // Find a safe location to insert the copy, this may be the first terminator
377 // in the block (or end()).
378 MachineBasicBlock::iterator InsertPos =
379 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
382 MachineInstr *NewSrcInstr = 0;
383 if (!reusedIncoming && IncomingReg) {
385 // The source register is undefined, so there is no need for a real
386 // COPY, but we still need to ensure joint dominance by defs.
387 // Insert an IMPLICIT_DEF instruction.
388 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
389 TII->get(TargetOpcode::IMPLICIT_DEF),
392 // Clean up the old implicit-def, if there even was one.
393 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
394 if (DefMI->isImplicitDef())
395 ImpDefs.insert(DefMI);
397 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
398 TII->get(TargetOpcode::COPY), IncomingReg)
399 .addReg(SrcReg, 0, SrcSubReg);
403 // We only need to update the LiveVariables kill of SrcReg if this was the
404 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
405 // out of the predecessor. We can also ignore undef sources.
406 if (LV && !SrcUndef &&
407 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
408 !LV->isLiveOut(SrcReg, opBlock)) {
409 // We want to be able to insert a kill of the register if this PHI (aka,
410 // the copy we just inserted) is the last use of the source value. Live
411 // variable analysis conservatively handles this by saying that the value
412 // is live until the end of the block the PHI entry lives in. If the value
413 // really is dead at the PHI copy, there will be no successor blocks which
414 // have the value live-in.
416 // Okay, if we now know that the value is not live out of the block, we
417 // can add a kill marker in this block saying that it kills the incoming
420 // In our final twist, we have to decide which instruction kills the
421 // register. In most cases this is the copy, however, terminator
422 // instructions at the end of the block may also use the value. In this
423 // case, we should mark the last such terminator as being the killing
424 // block, not the copy.
425 MachineBasicBlock::iterator KillInst = opBlock.end();
426 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
427 for (MachineBasicBlock::iterator Term = FirstTerm;
428 Term != opBlock.end(); ++Term) {
429 if (Term->readsRegister(SrcReg))
433 if (KillInst == opBlock.end()) {
434 // No terminator uses the register.
436 if (reusedIncoming || !IncomingReg) {
437 // We may have to rewind a bit if we didn't insert a copy this time.
438 KillInst = FirstTerm;
439 while (KillInst != opBlock.begin()) {
441 if (KillInst->isDebugValue())
443 if (KillInst->readsRegister(SrcReg))
447 // We just inserted this copy.
448 KillInst = std::prev(InsertPos);
451 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
453 // Finally, mark it killed.
454 LV->addVirtualRegisterKilled(SrcReg, KillInst);
456 // This vreg no longer lives all of the way through opBlock.
457 unsigned opBlockNum = opBlock.getNumber();
458 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
463 LIS->InsertMachineInstrInMaps(NewSrcInstr);
464 LIS->addSegmentToEndOfBlock(IncomingReg, NewSrcInstr);
468 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
469 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
471 bool isLiveOut = false;
472 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
473 SE = opBlock.succ_end(); SI != SE; ++SI) {
474 SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
475 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
477 // Definitions by other PHIs are not truly live-in for our purposes.
478 if (VNI && VNI->def != startIdx) {
485 MachineBasicBlock::iterator KillInst = opBlock.end();
486 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
487 for (MachineBasicBlock::iterator Term = FirstTerm;
488 Term != opBlock.end(); ++Term) {
489 if (Term->readsRegister(SrcReg))
493 if (KillInst == opBlock.end()) {
494 // No terminator uses the register.
496 if (reusedIncoming || !IncomingReg) {
497 // We may have to rewind a bit if we didn't just insert a copy.
498 KillInst = FirstTerm;
499 while (KillInst != opBlock.begin()) {
501 if (KillInst->isDebugValue())
503 if (KillInst->readsRegister(SrcReg))
507 // We just inserted this copy.
508 KillInst = std::prev(InsertPos);
511 assert(KillInst->readsRegister(SrcReg) &&
512 "Cannot find kill instruction");
514 SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
515 SrcLI.removeSegment(LastUseIndex.getRegSlot(),
516 LIS->getMBBEndIdx(&opBlock));
522 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
523 if (reusedIncoming || !IncomingReg) {
525 LIS->RemoveMachineInstrFromMaps(MPhi);
526 MF.DeleteMachineInstr(MPhi);
530 /// analyzePHINodes - Gather information about the PHI nodes in here. In
531 /// particular, we want to map the number of uses of a virtual register which is
532 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
533 /// used later to determine when the vreg is killed in the BB.
535 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
536 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
538 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
539 BBI != BBE && BBI->isPHI(); ++BBI)
540 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
541 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(),
542 BBI->getOperand(i).getReg())];
545 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
546 MachineBasicBlock &MBB,
547 MachineLoopInfo *MLI) {
548 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
549 return false; // Quick exit for basic blocks without PHIs.
551 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : 0;
552 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
554 bool Changed = false;
555 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
556 BBI != BBE && BBI->isPHI(); ++BBI) {
557 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
558 unsigned Reg = BBI->getOperand(i).getReg();
559 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
560 // Is there a critical edge from PreMBB to MBB?
561 if (PreMBB->succ_size() == 1)
564 // Avoid splitting backedges of loops. It would introduce small
565 // out-of-line blocks into the loop which is very bad for code placement.
566 if (PreMBB == &MBB && !SplitAllCriticalEdges)
568 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : 0;
569 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
572 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
573 // when the source register is live-out for some other reason than a phi
574 // use. That means the copy we will insert in PreMBB won't be a kill, and
575 // there is a risk it may not be coalesced away.
577 // If the copy would be a kill, there is no need to split the edge.
578 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges)
581 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
582 << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
585 // If Reg is not live-in to MBB, it means it must be live-in to some
586 // other PreMBB successor, and we can avoid the interference by splitting
589 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
590 // is likely to be left after coalescing. If we are looking at a loop
591 // exiting edge, split it so we won't insert code in the loop, otherwise
593 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges;
595 // Check for a loop exiting edge.
596 if (!ShouldSplit && CurLoop != PreLoop) {
598 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
599 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
600 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
602 // This edge could be entering a loop, exiting a loop, or it could be
603 // both: Jumping directly form one loop to the header of a sibling
605 // Split unless this edge is entering CurLoop from an outer loop.
606 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
610 if (!PreMBB->SplitCriticalEdge(&MBB, this)) {
611 DEBUG(dbgs() << "Failed to split critical edge.\n");
615 ++NumCriticalEdgesSplit;
621 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) {
622 assert((LV || LIS) &&
623 "isLiveIn() requires either LiveVariables or LiveIntervals");
625 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
627 return LV->isLiveIn(Reg, *MBB);
630 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) {
631 assert((LV || LIS) &&
632 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
633 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
634 // so that a register used only in a PHI is not live out of the block. In
635 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
636 // in the predecessor basic block, so that a register used only in a PHI is live
639 const LiveInterval &LI = LIS->getInterval(Reg);
640 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
641 SE = MBB->succ_end(); SI != SE; ++SI) {
642 if (LI.liveAt(LIS->getMBBStartIdx(*SI)))
647 return LV->isLiveOut(Reg, *MBB);