1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "phielim"
17 #include "PHIElimination.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegAllocRegistry.h"
25 #include "llvm/Function.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/ADT/SmallPtrSet.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
37 STATISTIC(NumAtomic, "Number of atomic phis lowered");
38 STATISTIC(NumSplits, "Number of critical edges split on demand");
41 SplitEdges("split-phi-edges",
42 cl::desc("Split critical edges during phi elimination"),
43 cl::init(false), cl::Hidden);
45 char PHIElimination::ID = 0;
46 static RegisterPass<PHIElimination>
47 X("phi-node-elimination", "Eliminate PHI nodes for register allocation");
49 const PassInfo *const llvm::PHIEliminationID = &X;
51 namespace llvm { FunctionPass *createLocalRegisterAllocator(); }
53 // Should we run edge splitting?
54 static bool shouldSplitEdges() {
55 // Edge splitting breaks the local register allocator. It cannot tolerate
56 // LiveVariables being run.
57 if (RegisterRegAlloc::getDefault() == createLocalRegisterAllocator)
62 void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.addPreserved<LiveVariables>();
64 AU.addPreserved<MachineDominatorTree>();
65 if (shouldSplitEdges()) {
66 AU.addRequired<LiveVariables>();
69 AU.addPreservedID(MachineLoopInfoID);
71 MachineFunctionPass::getAnalysisUsage(AU);
74 bool llvm::PHIElimination::runOnMachineFunction(MachineFunction &Fn) {
75 MRI = &Fn.getRegInfo();
81 // Split critical edges to help the coalescer
82 if (shouldSplitEdges())
83 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
84 Changed |= SplitPHIEdges(Fn, *I);
86 // Populate VRegPHIUseCount
89 // Eliminate PHI instructions by inserting copies into predecessor blocks.
90 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
91 Changed |= EliminatePHINodes(Fn, *I);
93 // Remove dead IMPLICIT_DEF instructions.
94 for (SmallPtrSet<MachineInstr*,4>::iterator I = ImpDefs.begin(),
95 E = ImpDefs.end(); I != E; ++I) {
96 MachineInstr *DefMI = *I;
97 unsigned DefReg = DefMI->getOperand(0).getReg();
98 if (MRI->use_empty(DefReg))
99 DefMI->eraseFromParent();
103 VRegPHIUseCount.clear();
107 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
108 /// predecessor basic blocks.
110 bool llvm::PHIElimination::EliminatePHINodes(MachineFunction &MF,
111 MachineBasicBlock &MBB) {
112 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
113 return false; // Quick exit for basic blocks without PHIs.
115 // Get an iterator to the first instruction after the last PHI node (this may
116 // also be the end of the basic block).
117 MachineBasicBlock::iterator AfterPHIsIt = SkipPHIsAndLabels(MBB, MBB.begin());
119 while (MBB.front().getOpcode() == TargetInstrInfo::PHI)
120 LowerAtomicPHINode(MBB, AfterPHIsIt);
125 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
126 /// are implicit_def's.
127 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
128 const MachineRegisterInfo *MRI) {
129 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
130 unsigned SrcReg = MPhi->getOperand(i).getReg();
131 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
132 if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
138 // FindCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
139 // when following the CFG edge to SuccMBB. This needs to be after any def of
140 // SrcReg, but before any subsequent point where control flow might jump out of
142 MachineBasicBlock::iterator
143 llvm::PHIElimination::FindCopyInsertPoint(MachineBasicBlock &MBB,
144 MachineBasicBlock &SuccMBB,
146 // Handle the trivial case trivially.
150 // Usually, we just want to insert the copy before the first terminator
151 // instruction. However, for the edge going to a landing pad, we must insert
152 // the copy before the call/invoke instruction.
153 if (!SuccMBB.isLandingPad())
154 return MBB.getFirstTerminator();
156 // Discover any defs/uses in this basic block.
157 SmallPtrSet<MachineInstr*, 8> DefUsesInMBB;
158 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
159 RE = MRI->reg_end(); RI != RE; ++RI) {
160 MachineInstr *DefUseMI = &*RI;
161 if (DefUseMI->getParent() == &MBB)
162 DefUsesInMBB.insert(DefUseMI);
165 MachineBasicBlock::iterator InsertPoint;
166 if (DefUsesInMBB.empty()) {
167 // No defs. Insert the copy at the start of the basic block.
168 InsertPoint = MBB.begin();
169 } else if (DefUsesInMBB.size() == 1) {
170 // Insert the copy immediately after the def/use.
171 InsertPoint = *DefUsesInMBB.begin();
174 // Insert the copy immediately after the last def/use.
175 InsertPoint = MBB.end();
176 while (!DefUsesInMBB.count(&*--InsertPoint)) {}
180 // Make sure the copy goes after any phi nodes however.
181 return SkipPHIsAndLabels(MBB, InsertPoint);
184 /// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
185 /// under the assuption that it needs to be lowered in a way that supports
186 /// atomic execution of PHIs. This lowering method is always correct all of the
189 void llvm::PHIElimination::LowerAtomicPHINode(
190 MachineBasicBlock &MBB,
191 MachineBasicBlock::iterator AfterPHIsIt) {
192 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
193 MachineInstr *MPhi = MBB.remove(MBB.begin());
195 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
196 unsigned DestReg = MPhi->getOperand(0).getReg();
197 bool isDead = MPhi->getOperand(0).isDead();
199 // Create a new register for the incoming PHI arguments.
200 MachineFunction &MF = *MBB.getParent();
201 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
202 unsigned IncomingReg = 0;
204 // Insert a register to register copy at the top of the current block (but
205 // after any remaining phi nodes) which copies the new incoming register
206 // into the phi node destination.
207 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
208 if (isSourceDefinedByImplicitDef(MPhi, MRI))
209 // If all sources of a PHI node are implicit_def, just emit an
210 // implicit_def instead of a copy.
211 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
212 TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
214 IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
215 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
219 assert(!hasPHIDef(DestReg) && "Vreg has multiple phi-defs?");
220 PHIDefs[DestReg] = &MBB;
222 // Update live variable information if there is any.
223 LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>();
225 MachineInstr *PHICopy = prior(AfterPHIsIt);
228 // Increment use count of the newly created virtual register.
229 LV->getVarInfo(IncomingReg).NumUses++;
231 // Add information to LiveVariables to know that the incoming value is
232 // killed. Note that because the value is defined in several places (once
233 // each for each incoming block), the "def" block and instruction fields
234 // for the VarInfo is not filled in.
235 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
238 // Since we are going to be deleting the PHI node, if it is the last use of
239 // any registers, or if the value itself is dead, we need to move this
240 // information over to the new copy we just inserted.
241 LV->removeVirtualRegistersKilled(MPhi);
243 // If the result is dead, update LV.
245 LV->addVirtualRegisterDead(DestReg, PHICopy);
246 LV->removeVirtualRegisterDead(DestReg, MPhi);
250 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
251 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
252 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(),
253 MPhi->getOperand(i).getReg())];
255 // Now loop over all of the incoming arguments, changing them to copy into the
256 // IncomingReg register in the corresponding predecessor basic block.
257 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
258 for (int i = NumSrcs - 1; i >= 0; --i) {
259 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
260 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
261 "Machine PHI Operands must all be virtual registers!");
263 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
265 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
268 PHIKills[SrcReg].insert(&opBlock);
270 // If source is defined by an implicit def, there is no need to insert a
272 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
273 if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
274 ImpDefs.insert(DefMI);
278 // Check to make sure we haven't already emitted the copy for this block.
279 // This can happen because PHI nodes may have multiple entries for the same
281 if (!MBBsInsertedInto.insert(&opBlock))
282 continue; // If the copy has already been emitted, we're done.
284 // Find a safe location to insert the copy, this may be the first terminator
285 // in the block (or end()).
286 MachineBasicBlock::iterator InsertPos =
287 FindCopyInsertPoint(opBlock, MBB, SrcReg);
290 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
292 // Now update live variable information if we have it. Otherwise we're done
295 // We want to be able to insert a kill of the register if this PHI (aka, the
296 // copy we just inserted) is the last use of the source value. Live
297 // variable analysis conservatively handles this by saying that the value is
298 // live until the end of the block the PHI entry lives in. If the value
299 // really is dead at the PHI copy, there will be no successor blocks which
300 // have the value live-in.
302 // Also check to see if this register is in use by another PHI node which
303 // has not yet been eliminated. If so, it will be killed at an appropriate
306 // Is it used by any PHI instructions in this block?
307 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0;
309 // Okay, if we now know that the value is not live out of the block, we can
310 // add a kill marker in this block saying that it kills the incoming value!
311 if (!ValueIsUsed && !isLiveOut(SrcReg, opBlock, *LV)) {
312 // In our final twist, we have to decide which instruction kills the
313 // register. In most cases this is the copy, however, the first
314 // terminator instruction at the end of the block may also use the value.
315 // In this case, we should mark *it* as being the killing block, not the
317 MachineBasicBlock::iterator KillInst = prior(InsertPos);
318 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator();
319 if (Term != opBlock.end()) {
320 if (Term->readsRegister(SrcReg))
323 // Check that no other terminators use values.
325 for (MachineBasicBlock::iterator TI = next(Term); TI != opBlock.end();
327 assert(!TI->readsRegister(SrcReg) &&
328 "Terminator instructions cannot use virtual registers unless"
329 "they are the first terminator in a block!");
334 // Finally, mark it killed.
335 LV->addVirtualRegisterKilled(SrcReg, KillInst);
337 // This vreg no longer lives all of the way through opBlock.
338 unsigned opBlockNum = opBlock.getNumber();
339 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
343 // Really delete the PHI instruction now!
344 MF.DeleteMachineInstr(MPhi);
348 /// analyzePHINodes - Gather information about the PHI nodes in here. In
349 /// particular, we want to map the number of uses of a virtual register which is
350 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
351 /// used later to determine when the vreg is killed in the BB.
353 void llvm::PHIElimination::analyzePHINodes(const MachineFunction& Fn) {
354 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
356 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
357 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
358 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
359 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(),
360 BBI->getOperand(i).getReg())];
363 bool llvm::PHIElimination::SplitPHIEdges(MachineFunction &MF,
364 MachineBasicBlock &MBB) {
365 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
366 return false; // Quick exit for basic blocks without PHIs.
367 LiveVariables &LV = getAnalysis<LiveVariables>();
368 for (MachineBasicBlock::const_iterator BBI = MBB.begin(), BBE = MBB.end();
369 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
370 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
371 unsigned Reg = BBI->getOperand(i).getReg();
372 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
373 // We break edges when registers are live out from the predecessor block
374 // (not considering PHI nodes). If the register is live in to this block
375 // anyway, we would gain nothing from splitting.
376 if (isLiveOut(Reg, *PreMBB, LV) && !isLiveIn(Reg, MBB, LV))
377 SplitCriticalEdge(PreMBB, &MBB);
383 bool llvm::PHIElimination::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB,
385 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
387 // Loop over all of the successors of the basic block, checking to see if
388 // the value is either live in the block, or if it is killed in the block.
389 std::vector<MachineBasicBlock*> OpSuccBlocks;
390 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
391 E = MBB.succ_end(); SI != E; ++SI) {
392 MachineBasicBlock *SuccMBB = *SI;
394 // Is it alive in this successor?
395 unsigned SuccIdx = SuccMBB->getNumber();
396 if (VI.AliveBlocks.test(SuccIdx))
398 OpSuccBlocks.push_back(SuccMBB);
401 // Check to see if this value is live because there is a use in a successor
403 switch (OpSuccBlocks.size()) {
405 MachineBasicBlock *SuccMBB = OpSuccBlocks[0];
406 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
407 if (VI.Kills[i]->getParent() == SuccMBB)
412 MachineBasicBlock *SuccMBB1 = OpSuccBlocks[0], *SuccMBB2 = OpSuccBlocks[1];
413 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
414 if (VI.Kills[i]->getParent() == SuccMBB1 ||
415 VI.Kills[i]->getParent() == SuccMBB2)
420 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
421 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
422 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
423 VI.Kills[i]->getParent()))
429 bool llvm::PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock &MBB,
431 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
433 if (VI.AliveBlocks.test(MBB.getNumber()))
437 const MachineInstr *Def = MRI->getVRegDef(Reg);
438 if (Def && Def->getParent() == &MBB)
442 return VI.findKill(&MBB);
445 MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
446 MachineBasicBlock *B) {
447 assert(A && B && "Missing MBB end point");
449 MachineFunction *MF = A->getParent();
451 // We may need to update A's terminator, but we can't do that if AnalyzeBranch
453 if (A->isLayoutSuccessor(B)) {
454 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
455 MachineBasicBlock *TBB = 0, *FBB = 0;
456 SmallVector<MachineOperand, 4> Cond;
457 if (!TII->AnalyzeBranch(*A, TBB, FBB, Cond))
463 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
465 DEBUG(errs() << "PHIElimination splitting critical edge:"
466 " BB#" << A->getNumber()
467 << " -- BB#" << NMBB->getNumber()
468 << " -- BB#" << B->getNumber() << '\n');
470 A->ReplaceUsesOfBlockWith(B, NMBB);
471 // If A may fall through to B, we may have to insert a branch.
472 if (A->isLayoutSuccessor(B))
473 A->updateTerminator();
475 // Insert unconditional "jump B" instruction in NMBB.
476 NMBB->addSuccessor(B);
477 SmallVector<MachineOperand, 4> Cond;
478 MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond);
480 // Fix PHI nodes in B so they refer to NMBB instead of A
481 for (MachineBasicBlock::iterator i = B->begin(), e = B->end();
482 i != e && i->getOpcode() == TargetInstrInfo::PHI; ++i)
483 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
484 if (i->getOperand(ni+1).getMBB() == A)
485 i->getOperand(ni+1).setMBB(NMBB);
487 if (LiveVariables *LV=getAnalysisIfAvailable<LiveVariables>())
488 LV->addNewBlock(NMBB, A);
490 if (MachineDominatorTree *MDT=getAnalysisIfAvailable<MachineDominatorTree>())
491 MDT->addNewBlock(NMBB, A);