1 //===-- Passes.cpp - Target independent code generation passes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
13 //===---------------------------------------------------------------------===//
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Analysis/Passes.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/RegAllocRegistry.h"
19 #include "llvm/IR/IRPrintingPasses.h"
20 #include "llvm/IR/Verifier.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/Target/TargetSubtargetInfo.h"
28 #include "llvm/Transforms/Scalar.h"
29 #include "llvm/Transforms/Utils/SymbolRewriter.h"
33 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
34 cl::desc("Disable Post Regalloc"));
35 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
36 cl::desc("Disable branch folding"));
37 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
38 cl::desc("Disable tail duplication"));
39 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
40 cl::desc("Disable pre-register allocation tail duplication"));
41 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
42 cl::Hidden, cl::desc("Disable probability-driven block placement"));
43 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
44 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
45 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
46 cl::desc("Disable Stack Slot Coloring"));
47 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
48 cl::desc("Disable Machine Dead Code Elimination"));
49 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
50 cl::desc("Disable Early If-conversion"));
51 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52 cl::desc("Disable Machine LICM"));
53 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
54 cl::desc("Disable Machine Common Subexpression Elimination"));
55 static cl::opt<cl::boolOrDefault>
56 OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
57 cl::desc("Enable optimized register allocation compilation path."));
58 static cl::opt<cl::boolOrDefault>
59 EnableMachineSched("enable-misched",
60 cl::desc("Enable the machine instruction scheduling pass."));
61 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
63 cl::desc("Disable Machine LICM"));
64 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
65 cl::desc("Disable Machine Sinking"));
66 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
67 cl::desc("Disable Loop Strength Reduction Pass"));
68 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
69 cl::Hidden, cl::desc("Disable ConstantHoisting"));
70 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
71 cl::desc("Disable Codegen Prepare"));
72 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
73 cl::desc("Disable Copy Propagation pass"));
74 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
75 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
76 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
77 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
78 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
79 cl::desc("Print LLVM IR input to isel pass"));
80 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
81 cl::desc("Dump garbage collector data"));
82 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
83 cl::desc("Verify generated machine code"),
84 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=nullptr));
85 static cl::opt<std::string>
86 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
87 cl::desc("Print machine instrs"),
88 cl::value_desc("pass-name"), cl::init("option-unspecified"));
90 // Temporary option to allow experimenting with MachineScheduler as a post-RA
91 // scheduler. Targets can "properly" enable this with
92 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); Ideally it
93 // wouldn't be part of the standard pass pipeline, and the target would just add
94 // a PostRA scheduling pass wherever it wants.
95 static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
96 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
98 // Experimental option to run live interval analysis early.
99 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
100 cl::desc("Run live interval analysis earlier in the pipeline"));
102 static cl::opt<bool> UseCFLAA("use-cfl-aa-in-codegen",
103 cl::init(false), cl::Hidden,
104 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"));
106 /// Allow standard passes to be disabled by command line options. This supports
107 /// simple binary flags that either suppress the pass or do nothing.
108 /// i.e. -disable-mypass=false has no effect.
109 /// These should be converted to boolOrDefault in order to use applyOverride.
110 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
113 return IdentifyingPassPtr();
117 /// Allow Pass selection to be overriden by command line options. This supports
118 /// flags with ternary conditions. TargetID is passed through by default. The
119 /// pass is suppressed when the option is false. When the option is true, the
120 /// StandardID is selected if the target provides no default.
121 static IdentifyingPassPtr applyOverride(IdentifyingPassPtr TargetID,
122 cl::boolOrDefault Override,
123 AnalysisID StandardID) {
128 if (TargetID.isValid())
130 if (StandardID == nullptr)
131 report_fatal_error("Target cannot enable pass");
134 return IdentifyingPassPtr();
136 llvm_unreachable("Invalid command line option state");
139 /// Allow standard passes to be disabled by the command line, regardless of who
140 /// is adding the pass.
142 /// StandardID is the pass identified in the standard pass pipeline and provided
143 /// to addPass(). It may be a target-specific ID in the case that the target
144 /// directly adds its own pass, but in that case we harmlessly fall through.
146 /// TargetID is the pass that the target has configured to override StandardID.
148 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
149 /// pass to run. This allows multiple options to control a single pass depending
150 /// on where in the pipeline that pass is added.
151 static IdentifyingPassPtr overridePass(AnalysisID StandardID,
152 IdentifyingPassPtr TargetID) {
153 if (StandardID == &PostRASchedulerID)
154 return applyDisable(TargetID, DisablePostRA);
156 if (StandardID == &BranchFolderPassID)
157 return applyDisable(TargetID, DisableBranchFold);
159 if (StandardID == &TailDuplicateID)
160 return applyDisable(TargetID, DisableTailDuplicate);
162 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
163 return applyDisable(TargetID, DisableEarlyTailDup);
165 if (StandardID == &MachineBlockPlacementID)
166 return applyDisable(TargetID, DisableBlockPlacement);
168 if (StandardID == &StackSlotColoringID)
169 return applyDisable(TargetID, DisableSSC);
171 if (StandardID == &DeadMachineInstructionElimID)
172 return applyDisable(TargetID, DisableMachineDCE);
174 if (StandardID == &EarlyIfConverterID)
175 return applyDisable(TargetID, DisableEarlyIfConversion);
177 if (StandardID == &MachineLICMID)
178 return applyDisable(TargetID, DisableMachineLICM);
180 if (StandardID == &MachineCSEID)
181 return applyDisable(TargetID, DisableMachineCSE);
183 if (StandardID == &MachineSchedulerID)
184 return applyOverride(TargetID, EnableMachineSched, StandardID);
186 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
187 return applyDisable(TargetID, DisablePostRAMachineLICM);
189 if (StandardID == &MachineSinkingID)
190 return applyDisable(TargetID, DisableMachineSink);
192 if (StandardID == &MachineCopyPropagationID)
193 return applyDisable(TargetID, DisableCopyProp);
198 //===---------------------------------------------------------------------===//
200 //===---------------------------------------------------------------------===//
202 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
203 "Target Pass Configuration", false, false)
204 char TargetPassConfig::ID = 0;
207 char TargetPassConfig::EarlyTailDuplicateID = 0;
208 char TargetPassConfig::PostRAMachineLICMID = 0;
211 class PassConfigImpl {
213 // List of passes explicitly substituted by this target. Normally this is
214 // empty, but it is a convenient way to suppress or replace specific passes
215 // that are part of a standard pass pipeline without overridding the entire
216 // pipeline. This mechanism allows target options to inherit a standard pass's
217 // user interface. For example, a target may disable a standard pass by
218 // default by substituting a pass ID of zero, and the user may still enable
219 // that standard pass with an explicit command line option.
220 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
222 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
223 /// is inserted after each instance of the first one.
224 SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses;
228 // Out of line virtual method.
229 TargetPassConfig::~TargetPassConfig() {
233 // Out of line constructor provides default values for pass options and
234 // registers all common codegen passes.
235 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
236 : ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr),
237 Started(true), Stopped(false), AddingMachinePasses(false), TM(tm),
238 Impl(nullptr), Initialized(false), DisableVerify(false),
239 EnableTailMerge(true) {
241 Impl = new PassConfigImpl();
243 // Register all target independent codegen passes to activate their PassIDs,
244 // including this pass itself.
245 initializeCodeGen(*PassRegistry::getPassRegistry());
247 // Substitute Pseudo Pass IDs for real ones.
248 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
249 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
251 // Temporarily disable experimental passes.
252 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
253 if (!ST.useMachineScheduler())
254 disablePass(&MachineSchedulerID);
257 /// Insert InsertedPassID pass after TargetPassID.
258 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
259 IdentifyingPassPtr InsertedPassID) {
260 assert(((!InsertedPassID.isInstance() &&
261 TargetPassID != InsertedPassID.getID()) ||
262 (InsertedPassID.isInstance() &&
263 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
264 "Insert a pass after itself!");
265 std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID);
266 Impl->InsertedPasses.push_back(P);
269 /// createPassConfig - Create a pass configuration object to be used by
270 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
272 /// Targets may override this to extend TargetPassConfig.
273 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
274 return new TargetPassConfig(this, PM);
277 TargetPassConfig::TargetPassConfig()
278 : ImmutablePass(ID), PM(nullptr) {
279 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
282 // Helper to verify the analysis is really immutable.
283 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
284 assert(!Initialized && "PassConfig is immutable");
288 void TargetPassConfig::substitutePass(AnalysisID StandardID,
289 IdentifyingPassPtr TargetID) {
290 Impl->TargetPasses[StandardID] = TargetID;
293 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
294 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
295 I = Impl->TargetPasses.find(ID);
296 if (I == Impl->TargetPasses.end())
301 /// Add a pass to the PassManager if that pass is supposed to be run. If the
302 /// Started/Stopped flags indicate either that the compilation should start at
303 /// a later pass or that it should stop after an earlier pass, then do not add
304 /// the pass. Finally, compare the current pass against the StartAfter
305 /// and StopAfter options and change the Started/Stopped flags accordingly.
306 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
307 assert(!Initialized && "PassConfig is immutable");
309 // Cache the Pass ID here in case the pass manager finds this pass is
310 // redundant with ones already scheduled / available, and deletes it.
311 // Fundamentally, once we add the pass to the manager, we no longer own it
312 // and shouldn't reference it.
313 AnalysisID PassID = P->getPassID();
315 if (Started && !Stopped) {
317 // Construct banner message before PM->add() as that may delete the pass.
318 if (AddingMachinePasses && (printAfter || verifyAfter))
319 Banner = std::string("After ") + std::string(P->getPassName());
321 if (AddingMachinePasses) {
323 addPrintPass(Banner);
325 addVerifyPass(Banner);
330 if (StopAfter == PassID)
332 if (StartAfter == PassID)
334 if (Stopped && !Started)
335 report_fatal_error("Cannot stop compilation after pass that is not run");
338 /// Add a CodeGen pass at this point in the pipeline after checking for target
339 /// and command line overrides.
341 /// addPass cannot return a pointer to the pass instance because is internal the
342 /// PassManager and the instance we create here may already be freed.
343 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
345 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
346 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
347 if (!FinalPtr.isValid())
351 if (FinalPtr.isInstance())
352 P = FinalPtr.getInstance();
354 P = Pass::createPass(FinalPtr.getID());
356 llvm_unreachable("Pass ID not registered");
358 AnalysisID FinalID = P->getPassID();
359 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
361 // Add the passes after the pass P if there is any.
362 for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
363 I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
365 if ((*I).first == PassID) {
366 assert((*I).second.isValid() && "Illegal Pass ID!");
368 if ((*I).second.isInstance())
369 NP = (*I).second.getInstance();
371 NP = Pass::createPass((*I).second.getID());
372 assert(NP && "Pass ID not registered");
374 addPass(NP, false, false);
380 void TargetPassConfig::printAndVerify(const std::string &Banner) {
381 addPrintPass(Banner);
382 addVerifyPass(Banner);
385 void TargetPassConfig::addPrintPass(const std::string &Banner) {
386 if (TM->shouldPrintMachineCode())
387 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
390 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
391 if (VerifyMachineCode)
392 PM->add(createMachineVerifierPass(Banner));
395 /// Add common target configurable passes that perform LLVM IR to IR transforms
396 /// following machine independent optimization.
397 void TargetPassConfig::addIRPasses() {
398 // Basic AliasAnalysis support.
399 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
400 // BasicAliasAnalysis wins if they disagree. This is intended to help
401 // support "obvious" type-punning idioms.
403 addPass(createCFLAliasAnalysisPass());
404 addPass(createTypeBasedAliasAnalysisPass());
405 addPass(createScopedNoAliasAAPass());
406 addPass(createBasicAliasAnalysisPass());
408 // Before running any passes, run the verifier to determine if the input
409 // coming from the front-end and/or optimizer is valid.
410 if (!DisableVerify) {
411 addPass(createVerifierPass());
412 addPass(createDebugInfoVerifierPass());
415 // Run loop strength reduction before anything else.
416 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
417 addPass(createLoopStrengthReducePass());
419 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
422 addPass(createGCLoweringPass());
424 // Make sure that no unreachable blocks are instruction selected.
425 addPass(createUnreachableBlockEliminationPass());
427 // Prepare expensive constants for SelectionDAG.
428 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
429 addPass(createConstantHoistingPass());
431 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
432 addPass(createPartiallyInlineLibCallsPass());
435 /// Turn exception handling constructs into something the code generators can
437 void TargetPassConfig::addPassesToHandleExceptions() {
438 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
439 case ExceptionHandling::SjLj:
440 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
441 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
442 // catch info can get misplaced when a selector ends up more than one block
443 // removed from the parent invoke(s). This could happen when a landing
444 // pad is shared by multiple invokes and is also a target of a normal
445 // edge from elsewhere.
446 addPass(createSjLjEHPreparePass(TM));
448 case ExceptionHandling::DwarfCFI:
449 case ExceptionHandling::ARM:
450 case ExceptionHandling::WinEH:
451 addPass(createDwarfEHPass(TM));
453 case ExceptionHandling::None:
454 addPass(createLowerInvokePass());
456 // The lower invoke pass may create unreachable code. Remove it.
457 addPass(createUnreachableBlockEliminationPass());
462 /// Add pass to prepare the LLVM IR for code generation. This should be done
463 /// before exception handling preparation passes.
464 void TargetPassConfig::addCodeGenPrepare() {
465 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
466 addPass(createCodeGenPreparePass(TM));
467 addPass(createRewriteSymbolsPass());
470 /// Add common passes that perform LLVM IR to IR transforms in preparation for
471 /// instruction selection.
472 void TargetPassConfig::addISelPrepare() {
475 // Need to verify DebugInfo *before* creating the stack protector analysis.
476 // It's a function pass, and verifying between it and its users causes a
479 addPass(createDebugInfoVerifierPass());
481 addPass(createStackProtectorPass(TM));
484 addPass(createPrintFunctionPass(
485 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
487 // All passes which modify the LLVM IR are now complete; run the verifier
488 // to ensure that the IR is valid.
490 addPass(createVerifierPass());
493 /// Add the complete set of target-independent postISel code generator passes.
495 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
496 /// with nontrivial configuration or multiple passes are broken out below in
497 /// add%Stage routines.
499 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
500 /// addPre/Post methods with empty header implementations allow injecting
501 /// target-specific fixups just before or after major stages. Additionally,
502 /// targets have the flexibility to change pass order within a stage by
503 /// overriding default implementation of add%Stage routines below. Each
504 /// technique has maintainability tradeoffs because alternate pass orders are
505 /// not well supported. addPre/Post works better if the target pass is easily
506 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
507 /// the target should override the stage instead.
509 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
510 /// before/after any target-independent pass. But it's currently overkill.
511 void TargetPassConfig::addMachinePasses() {
512 AddingMachinePasses = true;
514 // Insert a machine instr printer pass after the specified pass.
515 // If -print-machineinstrs specified, print machineinstrs after all passes.
516 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
517 TM->Options.PrintMachineCode = true;
518 else if (!StringRef(PrintMachineInstrs.getValue())
519 .equals("option-unspecified")) {
520 const PassRegistry *PR = PassRegistry::getPassRegistry();
521 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
522 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
523 assert (TPI && IPI && "Pass ID not registered!");
524 const char *TID = (const char *)(TPI->getTypeInfo());
525 const char *IID = (const char *)(IPI->getTypeInfo());
526 insertPass(TID, IID);
529 // Print the instruction selected machine code...
530 printAndVerify("After Instruction Selection");
532 // Expand pseudo-instructions emitted by ISel.
533 addPass(&ExpandISelPseudosID);
535 // Add passes that optimize machine instructions in SSA form.
536 if (getOptLevel() != CodeGenOpt::None) {
537 addMachineSSAOptimization();
539 // If the target requests it, assign local variables to stack slots relative
540 // to one another and simplify frame index references where possible.
541 addPass(&LocalStackSlotAllocationID, false);
544 // Run pre-ra passes.
547 // Run register allocation and passes that are tightly coupled with it,
548 // including phi elimination and scheduling.
549 if (getOptimizeRegAlloc())
550 addOptimizedRegAlloc(createRegAllocPass(true));
552 addFastRegAlloc(createRegAllocPass(false));
554 // Run post-ra passes.
557 // Insert prolog/epilog code. Eliminate abstract frame index references...
558 addPass(&PrologEpilogCodeInserterID);
560 /// Add passes that optimize machine instructions after register allocation.
561 if (getOptLevel() != CodeGenOpt::None)
562 addMachineLateOptimization();
564 // Expand pseudo instructions before second scheduling pass.
565 addPass(&ExpandPostRAPseudosID);
567 // Run pre-sched2 passes.
570 // Second pass scheduler.
571 if (getOptLevel() != CodeGenOpt::None) {
573 addPass(&PostMachineSchedulerID);
575 addPass(&PostRASchedulerID);
581 addPass(createGCInfoPrinter(dbgs()), false, false);
584 // Basic block placement.
585 if (getOptLevel() != CodeGenOpt::None)
590 addPass(&StackMapLivenessID, false);
592 AddingMachinePasses = false;
595 /// Add passes that optimize machine instructions in SSA form.
596 void TargetPassConfig::addMachineSSAOptimization() {
597 // Pre-ra tail duplication.
598 addPass(&EarlyTailDuplicateID);
600 // Optimize PHIs before DCE: removing dead PHI cycles may make more
601 // instructions dead.
602 addPass(&OptimizePHIsID, false);
604 // This pass merges large allocas. StackSlotColoring is a different pass
605 // which merges spill slots.
606 addPass(&StackColoringID, false);
608 // If the target requests it, assign local variables to stack slots relative
609 // to one another and simplify frame index references where possible.
610 addPass(&LocalStackSlotAllocationID, false);
612 // With optimization, dead code should already be eliminated. However
613 // there is one known exception: lowered code for arguments that are only
614 // used by tail calls, where the tail calls reuse the incoming stack
615 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
616 addPass(&DeadMachineInstructionElimID);
618 // Allow targets to insert passes that improve instruction level parallelism,
619 // like if-conversion. Such passes will typically need dominator trees and
620 // loop info, just like LICM and CSE below.
623 addPass(&MachineLICMID, false);
624 addPass(&MachineCSEID, false);
625 addPass(&MachineSinkingID);
627 addPass(&PeepholeOptimizerID, false);
628 // Clean-up the dead code that may have been generated by peephole
630 addPass(&DeadMachineInstructionElimID);
633 //===---------------------------------------------------------------------===//
634 /// Register Allocation Pass Configuration
635 //===---------------------------------------------------------------------===//
637 bool TargetPassConfig::getOptimizeRegAlloc() const {
638 switch (OptimizeRegAlloc) {
639 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
640 case cl::BOU_TRUE: return true;
641 case cl::BOU_FALSE: return false;
643 llvm_unreachable("Invalid optimize-regalloc state");
646 /// RegisterRegAlloc's global Registry tracks allocator registration.
647 MachinePassRegistry RegisterRegAlloc::Registry;
649 /// A dummy default pass factory indicates whether the register allocator is
650 /// overridden on the command line.
651 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
652 static RegisterRegAlloc
653 defaultRegAlloc("default",
654 "pick register allocator based on -O option",
655 useDefaultRegisterAllocator);
657 /// -regalloc=... command line option.
658 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
659 RegisterPassParser<RegisterRegAlloc> >
661 cl::init(&useDefaultRegisterAllocator),
662 cl::desc("Register allocator to use"));
665 /// Instantiate the default register allocator pass for this target for either
666 /// the optimized or unoptimized allocation path. This will be added to the pass
667 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
668 /// in the optimized case.
670 /// A target that uses the standard regalloc pass order for fast or optimized
671 /// allocation may still override this for per-target regalloc
672 /// selection. But -regalloc=... always takes precedence.
673 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
675 return createGreedyRegisterAllocator();
677 return createFastRegisterAllocator();
680 /// Find and instantiate the register allocation pass requested by this target
681 /// at the current optimization level. Different register allocators are
682 /// defined as separate passes because they may require different analysis.
684 /// This helper ensures that the regalloc= option is always available,
685 /// even for targets that override the default allocator.
687 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
688 /// this can be folded into addPass.
689 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
690 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
692 // Initialize the global default.
695 RegisterRegAlloc::setDefault(RegAlloc);
697 if (Ctor != useDefaultRegisterAllocator)
700 // With no -regalloc= override, ask the target for a regalloc pass.
701 return createTargetRegisterAllocator(Optimized);
704 /// Return true if the default global register allocator is in use and
705 /// has not be overriden on the command line with '-regalloc=...'
706 bool TargetPassConfig::usingDefaultRegAlloc() const {
707 return RegAlloc.getNumOccurrences() == 0;
710 /// Add the minimum set of target-independent passes that are required for
711 /// register allocation. No coalescing or scheduling.
712 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
713 addPass(&PHIEliminationID, false);
714 addPass(&TwoAddressInstructionPassID, false);
716 addPass(RegAllocPass);
719 /// Add standard target-independent passes that are tightly coupled with
720 /// optimized register allocation, including coalescing, machine instruction
721 /// scheduling, and register allocation itself.
722 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
723 addPass(&ProcessImplicitDefsID, false);
725 // LiveVariables currently requires pure SSA form.
727 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
728 // LiveVariables can be removed completely, and LiveIntervals can be directly
729 // computed. (We still either need to regenerate kill flags after regalloc, or
730 // preferably fix the scavenger to not depend on them).
731 addPass(&LiveVariablesID, false);
733 // Edge splitting is smarter with machine loop info.
734 addPass(&MachineLoopInfoID, false);
735 addPass(&PHIEliminationID, false);
737 // Eventually, we want to run LiveIntervals before PHI elimination.
738 if (EarlyLiveIntervals)
739 addPass(&LiveIntervalsID, false);
741 addPass(&TwoAddressInstructionPassID, false);
742 addPass(&RegisterCoalescerID);
744 // PreRA instruction scheduling.
745 addPass(&MachineSchedulerID);
747 // Add the selected register allocation pass.
748 addPass(RegAllocPass);
750 // Allow targets to change the register assignments before rewriting.
753 // Finally rewrite virtual registers.
754 addPass(&VirtRegRewriterID);
756 // Perform stack slot coloring and post-ra machine LICM.
758 // FIXME: Re-enable coloring with register when it's capable of adding
760 addPass(&StackSlotColoringID);
762 // Run post-ra machine LICM to hoist reloads / remats.
764 // FIXME: can this move into MachineLateOptimization?
765 addPass(&PostRAMachineLICMID);
768 //===---------------------------------------------------------------------===//
769 /// Post RegAlloc Pass Configuration
770 //===---------------------------------------------------------------------===//
772 /// Add passes that optimize machine instructions after register allocation.
773 void TargetPassConfig::addMachineLateOptimization() {
774 // Branch folding must be run after regalloc and prolog/epilog insertion.
775 addPass(&BranchFolderPassID);
778 // Note that duplicating tail just increases code size and degrades
779 // performance for targets that require Structured Control Flow.
780 // In addition it can also make CFG irreducible. Thus we disable it.
781 if (!TM->requiresStructuredCFG())
782 addPass(&TailDuplicateID);
785 addPass(&MachineCopyPropagationID);
788 /// Add standard GC passes.
789 bool TargetPassConfig::addGCPasses() {
790 addPass(&GCMachineCodeAnalysisID, false);
794 /// Add standard basic block placement passes.
795 void TargetPassConfig::addBlockPlacement() {
796 if (addPass(&MachineBlockPlacementID, false)) {
797 // Run a separate pass to collect block placement statistics.
798 if (EnableBlockPlacementStats)
799 addPass(&MachineBlockPlacementStatsID);