1 //===-- Passes.cpp - Target independent code generation passes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
13 //===---------------------------------------------------------------------===//
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Analysis/Passes.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/RegAllocRegistry.h"
19 #include "llvm/IR/IRPrintingPasses.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/IR/Verifier.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/Target/TargetSubtargetInfo.h"
28 #include "llvm/Transforms/Scalar.h"
29 #include "llvm/Transforms/Utils/SymbolRewriter.h"
33 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
34 cl::desc("Disable Post Regalloc"));
35 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
36 cl::desc("Disable branch folding"));
37 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
38 cl::desc("Disable tail duplication"));
39 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
40 cl::desc("Disable pre-register allocation tail duplication"));
41 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
42 cl::Hidden, cl::desc("Disable probability-driven block placement"));
43 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
44 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
45 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
46 cl::desc("Disable Stack Slot Coloring"));
47 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
48 cl::desc("Disable Machine Dead Code Elimination"));
49 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
50 cl::desc("Disable Early If-conversion"));
51 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52 cl::desc("Disable Machine LICM"));
53 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
54 cl::desc("Disable Machine Common Subexpression Elimination"));
55 static cl::opt<cl::boolOrDefault>
56 OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
57 cl::desc("Enable optimized register allocation compilation path."));
58 static cl::opt<cl::boolOrDefault>
59 EnableMachineSched("enable-misched",
60 cl::desc("Enable the machine instruction scheduling pass."));
61 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
63 cl::desc("Disable Machine LICM"));
64 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
65 cl::desc("Disable Machine Sinking"));
66 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
67 cl::desc("Disable Loop Strength Reduction Pass"));
68 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
69 cl::Hidden, cl::desc("Disable ConstantHoisting"));
70 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
71 cl::desc("Disable Codegen Prepare"));
72 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
73 cl::desc("Disable Copy Propagation pass"));
74 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
75 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
76 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
77 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
78 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
79 cl::desc("Print LLVM IR input to isel pass"));
80 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
81 cl::desc("Dump garbage collector data"));
82 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
83 cl::desc("Verify generated machine code"),
87 static cl::opt<std::string>
88 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
89 cl::desc("Print machine instrs"),
90 cl::value_desc("pass-name"), cl::init("option-unspecified"));
92 // Temporary option to allow experimenting with MachineScheduler as a post-RA
93 // scheduler. Targets can "properly" enable this with
94 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); Ideally it
95 // wouldn't be part of the standard pass pipeline, and the target would just add
96 // a PostRA scheduling pass wherever it wants.
97 static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
98 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
100 // Experimental option to run live interval analysis early.
101 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
102 cl::desc("Run live interval analysis earlier in the pipeline"));
104 static cl::opt<bool> UseCFLAA("use-cfl-aa-in-codegen",
105 cl::init(false), cl::Hidden,
106 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"));
108 /// Allow standard passes to be disabled by command line options. This supports
109 /// simple binary flags that either suppress the pass or do nothing.
110 /// i.e. -disable-mypass=false has no effect.
111 /// These should be converted to boolOrDefault in order to use applyOverride.
112 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
115 return IdentifyingPassPtr();
119 /// Allow Pass selection to be overriden by command line options. This supports
120 /// flags with ternary conditions. TargetID is passed through by default. The
121 /// pass is suppressed when the option is false. When the option is true, the
122 /// StandardID is selected if the target provides no default.
123 static IdentifyingPassPtr applyOverride(IdentifyingPassPtr TargetID,
124 cl::boolOrDefault Override,
125 AnalysisID StandardID) {
130 if (TargetID.isValid())
132 if (StandardID == nullptr)
133 report_fatal_error("Target cannot enable pass");
136 return IdentifyingPassPtr();
138 llvm_unreachable("Invalid command line option state");
141 /// Allow standard passes to be disabled by the command line, regardless of who
142 /// is adding the pass.
144 /// StandardID is the pass identified in the standard pass pipeline and provided
145 /// to addPass(). It may be a target-specific ID in the case that the target
146 /// directly adds its own pass, but in that case we harmlessly fall through.
148 /// TargetID is the pass that the target has configured to override StandardID.
150 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
151 /// pass to run. This allows multiple options to control a single pass depending
152 /// on where in the pipeline that pass is added.
153 static IdentifyingPassPtr overridePass(AnalysisID StandardID,
154 IdentifyingPassPtr TargetID) {
155 if (StandardID == &PostRASchedulerID)
156 return applyDisable(TargetID, DisablePostRA);
158 if (StandardID == &BranchFolderPassID)
159 return applyDisable(TargetID, DisableBranchFold);
161 if (StandardID == &TailDuplicateID)
162 return applyDisable(TargetID, DisableTailDuplicate);
164 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
165 return applyDisable(TargetID, DisableEarlyTailDup);
167 if (StandardID == &MachineBlockPlacementID)
168 return applyDisable(TargetID, DisableBlockPlacement);
170 if (StandardID == &StackSlotColoringID)
171 return applyDisable(TargetID, DisableSSC);
173 if (StandardID == &DeadMachineInstructionElimID)
174 return applyDisable(TargetID, DisableMachineDCE);
176 if (StandardID == &EarlyIfConverterID)
177 return applyDisable(TargetID, DisableEarlyIfConversion);
179 if (StandardID == &MachineLICMID)
180 return applyDisable(TargetID, DisableMachineLICM);
182 if (StandardID == &MachineCSEID)
183 return applyDisable(TargetID, DisableMachineCSE);
185 if (StandardID == &MachineSchedulerID)
186 return applyOverride(TargetID, EnableMachineSched, StandardID);
188 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
189 return applyDisable(TargetID, DisablePostRAMachineLICM);
191 if (StandardID == &MachineSinkingID)
192 return applyDisable(TargetID, DisableMachineSink);
194 if (StandardID == &MachineCopyPropagationID)
195 return applyDisable(TargetID, DisableCopyProp);
200 //===---------------------------------------------------------------------===//
202 //===---------------------------------------------------------------------===//
204 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
205 "Target Pass Configuration", false, false)
206 char TargetPassConfig::ID = 0;
209 char TargetPassConfig::EarlyTailDuplicateID = 0;
210 char TargetPassConfig::PostRAMachineLICMID = 0;
213 class PassConfigImpl {
215 // List of passes explicitly substituted by this target. Normally this is
216 // empty, but it is a convenient way to suppress or replace specific passes
217 // that are part of a standard pass pipeline without overridding the entire
218 // pipeline. This mechanism allows target options to inherit a standard pass's
219 // user interface. For example, a target may disable a standard pass by
220 // default by substituting a pass ID of zero, and the user may still enable
221 // that standard pass with an explicit command line option.
222 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
224 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
225 /// is inserted after each instance of the first one.
226 SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses;
230 // Out of line virtual method.
231 TargetPassConfig::~TargetPassConfig() {
235 // Out of line constructor provides default values for pass options and
236 // registers all common codegen passes.
237 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
238 : ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr),
239 Started(true), Stopped(false), AddingMachinePasses(false), TM(tm),
240 Impl(nullptr), Initialized(false), DisableVerify(false),
241 EnableTailMerge(true) {
243 Impl = new PassConfigImpl();
245 // Register all target independent codegen passes to activate their PassIDs,
246 // including this pass itself.
247 initializeCodeGen(*PassRegistry::getPassRegistry());
249 // Substitute Pseudo Pass IDs for real ones.
250 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
251 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
253 // Temporarily disable experimental passes.
254 const TargetSubtargetInfo &ST = *TM->getSubtargetImpl();
255 if (!ST.useMachineScheduler())
256 disablePass(&MachineSchedulerID);
259 /// Insert InsertedPassID pass after TargetPassID.
260 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
261 IdentifyingPassPtr InsertedPassID) {
262 assert(((!InsertedPassID.isInstance() &&
263 TargetPassID != InsertedPassID.getID()) ||
264 (InsertedPassID.isInstance() &&
265 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
266 "Insert a pass after itself!");
267 std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID);
268 Impl->InsertedPasses.push_back(P);
271 /// createPassConfig - Create a pass configuration object to be used by
272 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
274 /// Targets may override this to extend TargetPassConfig.
275 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
276 return new TargetPassConfig(this, PM);
279 TargetPassConfig::TargetPassConfig()
280 : ImmutablePass(ID), PM(nullptr) {
281 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
284 // Helper to verify the analysis is really immutable.
285 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
286 assert(!Initialized && "PassConfig is immutable");
290 void TargetPassConfig::substitutePass(AnalysisID StandardID,
291 IdentifyingPassPtr TargetID) {
292 Impl->TargetPasses[StandardID] = TargetID;
295 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
296 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
297 I = Impl->TargetPasses.find(ID);
298 if (I == Impl->TargetPasses.end())
303 /// Add a pass to the PassManager if that pass is supposed to be run. If the
304 /// Started/Stopped flags indicate either that the compilation should start at
305 /// a later pass or that it should stop after an earlier pass, then do not add
306 /// the pass. Finally, compare the current pass against the StartAfter
307 /// and StopAfter options and change the Started/Stopped flags accordingly.
308 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
309 assert(!Initialized && "PassConfig is immutable");
311 // Cache the Pass ID here in case the pass manager finds this pass is
312 // redundant with ones already scheduled / available, and deletes it.
313 // Fundamentally, once we add the pass to the manager, we no longer own it
314 // and shouldn't reference it.
315 AnalysisID PassID = P->getPassID();
317 if (Started && !Stopped) {
319 // Construct banner message before PM->add() as that may delete the pass.
320 if (AddingMachinePasses && (printAfter || verifyAfter))
321 Banner = std::string("After ") + std::string(P->getPassName());
323 if (AddingMachinePasses) {
325 addPrintPass(Banner);
327 addVerifyPass(Banner);
332 if (StopAfter == PassID)
334 if (StartAfter == PassID)
336 if (Stopped && !Started)
337 report_fatal_error("Cannot stop compilation after pass that is not run");
340 /// Add a CodeGen pass at this point in the pipeline after checking for target
341 /// and command line overrides.
343 /// addPass cannot return a pointer to the pass instance because is internal the
344 /// PassManager and the instance we create here may already be freed.
345 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
347 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
348 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
349 if (!FinalPtr.isValid())
353 if (FinalPtr.isInstance())
354 P = FinalPtr.getInstance();
356 P = Pass::createPass(FinalPtr.getID());
358 llvm_unreachable("Pass ID not registered");
360 AnalysisID FinalID = P->getPassID();
361 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
363 // Add the passes after the pass P if there is any.
364 for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
365 I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
367 if ((*I).first == PassID) {
368 assert((*I).second.isValid() && "Illegal Pass ID!");
370 if ((*I).second.isInstance())
371 NP = (*I).second.getInstance();
373 NP = Pass::createPass((*I).second.getID());
374 assert(NP && "Pass ID not registered");
376 addPass(NP, false, false);
382 void TargetPassConfig::printAndVerify(const std::string &Banner) {
383 addPrintPass(Banner);
384 addVerifyPass(Banner);
387 void TargetPassConfig::addPrintPass(const std::string &Banner) {
388 if (TM->shouldPrintMachineCode())
389 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
392 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
393 if (VerifyMachineCode)
394 PM->add(createMachineVerifierPass(Banner));
397 /// Add common target configurable passes that perform LLVM IR to IR transforms
398 /// following machine independent optimization.
399 void TargetPassConfig::addIRPasses() {
400 // Basic AliasAnalysis support.
401 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
402 // BasicAliasAnalysis wins if they disagree. This is intended to help
403 // support "obvious" type-punning idioms.
405 addPass(createCFLAliasAnalysisPass());
406 addPass(createTypeBasedAliasAnalysisPass());
407 addPass(createScopedNoAliasAAPass());
408 addPass(createBasicAliasAnalysisPass());
410 // Before running any passes, run the verifier to determine if the input
411 // coming from the front-end and/or optimizer is valid.
412 if (!DisableVerify) {
413 addPass(createVerifierPass());
414 addPass(createDebugInfoVerifierPass());
417 // Run loop strength reduction before anything else.
418 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
419 addPass(createLoopStrengthReducePass());
421 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
424 // Run GC lowering passes for builtin collectors
425 // TODO: add a pass insertion point here
426 addPass(createGCLoweringPass());
427 addPass(createShadowStackGCLoweringPass());
429 // Make sure that no unreachable blocks are instruction selected.
430 addPass(createUnreachableBlockEliminationPass());
432 // Prepare expensive constants for SelectionDAG.
433 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
434 addPass(createConstantHoistingPass());
436 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
437 addPass(createPartiallyInlineLibCallsPass());
440 /// Turn exception handling constructs into something the code generators can
442 void TargetPassConfig::addPassesToHandleExceptions() {
443 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
444 case ExceptionHandling::SjLj:
445 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
446 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
447 // catch info can get misplaced when a selector ends up more than one block
448 // removed from the parent invoke(s). This could happen when a landing
449 // pad is shared by multiple invokes and is also a target of a normal
450 // edge from elsewhere.
451 addPass(createSjLjEHPreparePass(TM));
453 case ExceptionHandling::DwarfCFI:
454 case ExceptionHandling::ARM:
455 addPass(createDwarfEHPass(TM));
457 case ExceptionHandling::WinEH:
458 addPass(createWinEHPass(TM));
460 case ExceptionHandling::None:
461 addPass(createLowerInvokePass());
463 // The lower invoke pass may create unreachable code. Remove it.
464 addPass(createUnreachableBlockEliminationPass());
469 /// Add pass to prepare the LLVM IR for code generation. This should be done
470 /// before exception handling preparation passes.
471 void TargetPassConfig::addCodeGenPrepare() {
472 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
473 addPass(createCodeGenPreparePass(TM));
474 addPass(createRewriteSymbolsPass());
477 /// Add common passes that perform LLVM IR to IR transforms in preparation for
478 /// instruction selection.
479 void TargetPassConfig::addISelPrepare() {
482 // Need to verify DebugInfo *before* creating the stack protector analysis.
483 // It's a function pass, and verifying between it and its users causes a
486 addPass(createDebugInfoVerifierPass());
488 addPass(createStackProtectorPass(TM));
491 addPass(createPrintFunctionPass(
492 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
494 // All passes which modify the LLVM IR are now complete; run the verifier
495 // to ensure that the IR is valid.
497 addPass(createVerifierPass());
500 /// Add the complete set of target-independent postISel code generator passes.
502 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
503 /// with nontrivial configuration or multiple passes are broken out below in
504 /// add%Stage routines.
506 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
507 /// addPre/Post methods with empty header implementations allow injecting
508 /// target-specific fixups just before or after major stages. Additionally,
509 /// targets have the flexibility to change pass order within a stage by
510 /// overriding default implementation of add%Stage routines below. Each
511 /// technique has maintainability tradeoffs because alternate pass orders are
512 /// not well supported. addPre/Post works better if the target pass is easily
513 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
514 /// the target should override the stage instead.
516 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
517 /// before/after any target-independent pass. But it's currently overkill.
518 void TargetPassConfig::addMachinePasses() {
519 AddingMachinePasses = true;
521 // Insert a machine instr printer pass after the specified pass.
522 // If -print-machineinstrs specified, print machineinstrs after all passes.
523 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
524 TM->Options.PrintMachineCode = true;
525 else if (!StringRef(PrintMachineInstrs.getValue())
526 .equals("option-unspecified")) {
527 const PassRegistry *PR = PassRegistry::getPassRegistry();
528 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
529 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
530 assert (TPI && IPI && "Pass ID not registered!");
531 const char *TID = (const char *)(TPI->getTypeInfo());
532 const char *IID = (const char *)(IPI->getTypeInfo());
533 insertPass(TID, IID);
536 // Print the instruction selected machine code...
537 printAndVerify("After Instruction Selection");
539 // Expand pseudo-instructions emitted by ISel.
540 addPass(&ExpandISelPseudosID);
542 // Add passes that optimize machine instructions in SSA form.
543 if (getOptLevel() != CodeGenOpt::None) {
544 addMachineSSAOptimization();
546 // If the target requests it, assign local variables to stack slots relative
547 // to one another and simplify frame index references where possible.
548 addPass(&LocalStackSlotAllocationID, false);
551 // Run pre-ra passes.
554 // Run register allocation and passes that are tightly coupled with it,
555 // including phi elimination and scheduling.
556 if (getOptimizeRegAlloc())
557 addOptimizedRegAlloc(createRegAllocPass(true));
559 addFastRegAlloc(createRegAllocPass(false));
561 // Run post-ra passes.
564 // Insert prolog/epilog code. Eliminate abstract frame index references...
565 addPass(&PrologEpilogCodeInserterID);
567 /// Add passes that optimize machine instructions after register allocation.
568 if (getOptLevel() != CodeGenOpt::None)
569 addMachineLateOptimization();
571 // Expand pseudo instructions before second scheduling pass.
572 addPass(&ExpandPostRAPseudosID);
574 // Run pre-sched2 passes.
577 // Second pass scheduler.
578 if (getOptLevel() != CodeGenOpt::None) {
580 addPass(&PostMachineSchedulerID);
582 addPass(&PostRASchedulerID);
588 addPass(createGCInfoPrinter(dbgs()), false, false);
591 // Basic block placement.
592 if (getOptLevel() != CodeGenOpt::None)
597 addPass(&StackMapLivenessID, false);
599 AddingMachinePasses = false;
602 /// Add passes that optimize machine instructions in SSA form.
603 void TargetPassConfig::addMachineSSAOptimization() {
604 // Pre-ra tail duplication.
605 addPass(&EarlyTailDuplicateID);
607 // Optimize PHIs before DCE: removing dead PHI cycles may make more
608 // instructions dead.
609 addPass(&OptimizePHIsID, false);
611 // This pass merges large allocas. StackSlotColoring is a different pass
612 // which merges spill slots.
613 addPass(&StackColoringID, false);
615 // If the target requests it, assign local variables to stack slots relative
616 // to one another and simplify frame index references where possible.
617 addPass(&LocalStackSlotAllocationID, false);
619 // With optimization, dead code should already be eliminated. However
620 // there is one known exception: lowered code for arguments that are only
621 // used by tail calls, where the tail calls reuse the incoming stack
622 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
623 addPass(&DeadMachineInstructionElimID);
625 // Allow targets to insert passes that improve instruction level parallelism,
626 // like if-conversion. Such passes will typically need dominator trees and
627 // loop info, just like LICM and CSE below.
630 addPass(&MachineLICMID, false);
631 addPass(&MachineCSEID, false);
632 addPass(&MachineSinkingID);
634 addPass(&PeepholeOptimizerID, false);
635 // Clean-up the dead code that may have been generated by peephole
637 addPass(&DeadMachineInstructionElimID);
640 //===---------------------------------------------------------------------===//
641 /// Register Allocation Pass Configuration
642 //===---------------------------------------------------------------------===//
644 bool TargetPassConfig::getOptimizeRegAlloc() const {
645 switch (OptimizeRegAlloc) {
646 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
647 case cl::BOU_TRUE: return true;
648 case cl::BOU_FALSE: return false;
650 llvm_unreachable("Invalid optimize-regalloc state");
653 /// RegisterRegAlloc's global Registry tracks allocator registration.
654 MachinePassRegistry RegisterRegAlloc::Registry;
656 /// A dummy default pass factory indicates whether the register allocator is
657 /// overridden on the command line.
658 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
659 static RegisterRegAlloc
660 defaultRegAlloc("default",
661 "pick register allocator based on -O option",
662 useDefaultRegisterAllocator);
664 /// -regalloc=... command line option.
665 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
666 RegisterPassParser<RegisterRegAlloc> >
668 cl::init(&useDefaultRegisterAllocator),
669 cl::desc("Register allocator to use"));
672 /// Instantiate the default register allocator pass for this target for either
673 /// the optimized or unoptimized allocation path. This will be added to the pass
674 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
675 /// in the optimized case.
677 /// A target that uses the standard regalloc pass order for fast or optimized
678 /// allocation may still override this for per-target regalloc
679 /// selection. But -regalloc=... always takes precedence.
680 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
682 return createGreedyRegisterAllocator();
684 return createFastRegisterAllocator();
687 /// Find and instantiate the register allocation pass requested by this target
688 /// at the current optimization level. Different register allocators are
689 /// defined as separate passes because they may require different analysis.
691 /// This helper ensures that the regalloc= option is always available,
692 /// even for targets that override the default allocator.
694 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
695 /// this can be folded into addPass.
696 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
697 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
699 // Initialize the global default.
702 RegisterRegAlloc::setDefault(RegAlloc);
704 if (Ctor != useDefaultRegisterAllocator)
707 // With no -regalloc= override, ask the target for a regalloc pass.
708 return createTargetRegisterAllocator(Optimized);
711 /// Return true if the default global register allocator is in use and
712 /// has not be overriden on the command line with '-regalloc=...'
713 bool TargetPassConfig::usingDefaultRegAlloc() const {
714 return RegAlloc.getNumOccurrences() == 0;
717 /// Add the minimum set of target-independent passes that are required for
718 /// register allocation. No coalescing or scheduling.
719 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
720 addPass(&PHIEliminationID, false);
721 addPass(&TwoAddressInstructionPassID, false);
723 addPass(RegAllocPass);
726 /// Add standard target-independent passes that are tightly coupled with
727 /// optimized register allocation, including coalescing, machine instruction
728 /// scheduling, and register allocation itself.
729 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
730 addPass(&ProcessImplicitDefsID, false);
732 // LiveVariables currently requires pure SSA form.
734 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
735 // LiveVariables can be removed completely, and LiveIntervals can be directly
736 // computed. (We still either need to regenerate kill flags after regalloc, or
737 // preferably fix the scavenger to not depend on them).
738 addPass(&LiveVariablesID, false);
740 // Edge splitting is smarter with machine loop info.
741 addPass(&MachineLoopInfoID, false);
742 addPass(&PHIEliminationID, false);
744 // Eventually, we want to run LiveIntervals before PHI elimination.
745 if (EarlyLiveIntervals)
746 addPass(&LiveIntervalsID, false);
748 addPass(&TwoAddressInstructionPassID, false);
749 addPass(&RegisterCoalescerID);
751 // PreRA instruction scheduling.
752 addPass(&MachineSchedulerID);
754 // Add the selected register allocation pass.
755 addPass(RegAllocPass);
757 // Allow targets to change the register assignments before rewriting.
760 // Finally rewrite virtual registers.
761 addPass(&VirtRegRewriterID);
763 // Perform stack slot coloring and post-ra machine LICM.
765 // FIXME: Re-enable coloring with register when it's capable of adding
767 addPass(&StackSlotColoringID);
769 // Run post-ra machine LICM to hoist reloads / remats.
771 // FIXME: can this move into MachineLateOptimization?
772 addPass(&PostRAMachineLICMID);
775 //===---------------------------------------------------------------------===//
776 /// Post RegAlloc Pass Configuration
777 //===---------------------------------------------------------------------===//
779 /// Add passes that optimize machine instructions after register allocation.
780 void TargetPassConfig::addMachineLateOptimization() {
781 // Branch folding must be run after regalloc and prolog/epilog insertion.
782 addPass(&BranchFolderPassID);
785 // Note that duplicating tail just increases code size and degrades
786 // performance for targets that require Structured Control Flow.
787 // In addition it can also make CFG irreducible. Thus we disable it.
788 if (!TM->requiresStructuredCFG())
789 addPass(&TailDuplicateID);
792 addPass(&MachineCopyPropagationID);
795 /// Add standard GC passes.
796 bool TargetPassConfig::addGCPasses() {
797 addPass(&GCMachineCodeAnalysisID, false);
801 /// Add standard basic block placement passes.
802 void TargetPassConfig::addBlockPlacement() {
803 if (addPass(&MachineBlockPlacementID, false)) {
804 // Run a separate pass to collect block placement statistics.
805 if (EnableBlockPlacementStats)
806 addPass(&MachineBlockPlacementStatsID);