1 //===-- Passes.cpp - Target independent code generation passes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
13 //===---------------------------------------------------------------------===//
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Analysis/Passes.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/RegAllocRegistry.h"
19 #include "llvm/IR/IRPrintingPasses.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/IR/Verifier.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/Target/TargetSubtargetInfo.h"
28 #include "llvm/Transforms/Scalar.h"
29 #include "llvm/Transforms/Utils/SymbolRewriter.h"
33 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
34 cl::desc("Disable Post Regalloc"));
35 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
36 cl::desc("Disable branch folding"));
37 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
38 cl::desc("Disable tail duplication"));
39 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
40 cl::desc("Disable pre-register allocation tail duplication"));
41 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
42 cl::Hidden, cl::desc("Disable probability-driven block placement"));
43 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
44 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
45 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
46 cl::desc("Disable Stack Slot Coloring"));
47 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
48 cl::desc("Disable Machine Dead Code Elimination"));
49 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
50 cl::desc("Disable Early If-conversion"));
51 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52 cl::desc("Disable Machine LICM"));
53 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
54 cl::desc("Disable Machine Common Subexpression Elimination"));
55 static cl::opt<cl::boolOrDefault>
56 OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
57 cl::desc("Enable optimized register allocation compilation path."));
58 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
60 cl::desc("Disable Machine LICM"));
61 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
62 cl::desc("Disable Machine Sinking"));
63 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
64 cl::desc("Disable Loop Strength Reduction Pass"));
65 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
66 cl::Hidden, cl::desc("Disable ConstantHoisting"));
67 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
68 cl::desc("Disable Codegen Prepare"));
69 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
70 cl::desc("Disable Copy Propagation pass"));
71 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
72 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
73 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
74 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
75 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
76 cl::desc("Print LLVM IR input to isel pass"));
77 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
78 cl::desc("Dump garbage collector data"));
79 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
80 cl::desc("Verify generated machine code"),
84 static cl::opt<std::string>
85 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
86 cl::desc("Print machine instrs"),
87 cl::value_desc("pass-name"), cl::init("option-unspecified"));
89 // Temporary option to allow experimenting with MachineScheduler as a post-RA
90 // scheduler. Targets can "properly" enable this with
91 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); Ideally it
92 // wouldn't be part of the standard pass pipeline, and the target would just add
93 // a PostRA scheduling pass wherever it wants.
94 static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
95 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
97 // Experimental option to run live interval analysis early.
98 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
99 cl::desc("Run live interval analysis earlier in the pipeline"));
101 static cl::opt<bool> UseCFLAA("use-cfl-aa-in-codegen",
102 cl::init(false), cl::Hidden,
103 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"));
105 /// Allow standard passes to be disabled by command line options. This supports
106 /// simple binary flags that either suppress the pass or do nothing.
107 /// i.e. -disable-mypass=false has no effect.
108 /// These should be converted to boolOrDefault in order to use applyOverride.
109 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
112 return IdentifyingPassPtr();
116 /// Allow standard passes to be disabled by the command line, regardless of who
117 /// is adding the pass.
119 /// StandardID is the pass identified in the standard pass pipeline and provided
120 /// to addPass(). It may be a target-specific ID in the case that the target
121 /// directly adds its own pass, but in that case we harmlessly fall through.
123 /// TargetID is the pass that the target has configured to override StandardID.
125 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
126 /// pass to run. This allows multiple options to control a single pass depending
127 /// on where in the pipeline that pass is added.
128 static IdentifyingPassPtr overridePass(AnalysisID StandardID,
129 IdentifyingPassPtr TargetID) {
130 if (StandardID == &PostRASchedulerID)
131 return applyDisable(TargetID, DisablePostRA);
133 if (StandardID == &BranchFolderPassID)
134 return applyDisable(TargetID, DisableBranchFold);
136 if (StandardID == &TailDuplicateID)
137 return applyDisable(TargetID, DisableTailDuplicate);
139 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
140 return applyDisable(TargetID, DisableEarlyTailDup);
142 if (StandardID == &MachineBlockPlacementID)
143 return applyDisable(TargetID, DisableBlockPlacement);
145 if (StandardID == &StackSlotColoringID)
146 return applyDisable(TargetID, DisableSSC);
148 if (StandardID == &DeadMachineInstructionElimID)
149 return applyDisable(TargetID, DisableMachineDCE);
151 if (StandardID == &EarlyIfConverterID)
152 return applyDisable(TargetID, DisableEarlyIfConversion);
154 if (StandardID == &MachineLICMID)
155 return applyDisable(TargetID, DisableMachineLICM);
157 if (StandardID == &MachineCSEID)
158 return applyDisable(TargetID, DisableMachineCSE);
160 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
161 return applyDisable(TargetID, DisablePostRAMachineLICM);
163 if (StandardID == &MachineSinkingID)
164 return applyDisable(TargetID, DisableMachineSink);
166 if (StandardID == &MachineCopyPropagationID)
167 return applyDisable(TargetID, DisableCopyProp);
172 //===---------------------------------------------------------------------===//
174 //===---------------------------------------------------------------------===//
176 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
177 "Target Pass Configuration", false, false)
178 char TargetPassConfig::ID = 0;
181 char TargetPassConfig::EarlyTailDuplicateID = 0;
182 char TargetPassConfig::PostRAMachineLICMID = 0;
185 class PassConfigImpl {
187 // List of passes explicitly substituted by this target. Normally this is
188 // empty, but it is a convenient way to suppress or replace specific passes
189 // that are part of a standard pass pipeline without overridding the entire
190 // pipeline. This mechanism allows target options to inherit a standard pass's
191 // user interface. For example, a target may disable a standard pass by
192 // default by substituting a pass ID of zero, and the user may still enable
193 // that standard pass with an explicit command line option.
194 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
196 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
197 /// is inserted after each instance of the first one.
198 SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses;
202 // Out of line virtual method.
203 TargetPassConfig::~TargetPassConfig() {
207 // Out of line constructor provides default values for pass options and
208 // registers all common codegen passes.
209 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
210 : ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr),
211 Started(true), Stopped(false), AddingMachinePasses(false), TM(tm),
212 Impl(nullptr), Initialized(false), DisableVerify(false),
213 EnableTailMerge(true) {
215 Impl = new PassConfigImpl();
217 // Register all target independent codegen passes to activate their PassIDs,
218 // including this pass itself.
219 initializeCodeGen(*PassRegistry::getPassRegistry());
221 // Substitute Pseudo Pass IDs for real ones.
222 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
223 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
226 /// Insert InsertedPassID pass after TargetPassID.
227 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
228 IdentifyingPassPtr InsertedPassID) {
229 assert(((!InsertedPassID.isInstance() &&
230 TargetPassID != InsertedPassID.getID()) ||
231 (InsertedPassID.isInstance() &&
232 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
233 "Insert a pass after itself!");
234 std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID);
235 Impl->InsertedPasses.push_back(P);
238 /// createPassConfig - Create a pass configuration object to be used by
239 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
241 /// Targets may override this to extend TargetPassConfig.
242 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
243 return new TargetPassConfig(this, PM);
246 TargetPassConfig::TargetPassConfig()
247 : ImmutablePass(ID), PM(nullptr) {
248 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
251 // Helper to verify the analysis is really immutable.
252 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
253 assert(!Initialized && "PassConfig is immutable");
257 void TargetPassConfig::substitutePass(AnalysisID StandardID,
258 IdentifyingPassPtr TargetID) {
259 Impl->TargetPasses[StandardID] = TargetID;
262 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
263 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
264 I = Impl->TargetPasses.find(ID);
265 if (I == Impl->TargetPasses.end())
270 /// Add a pass to the PassManager if that pass is supposed to be run. If the
271 /// Started/Stopped flags indicate either that the compilation should start at
272 /// a later pass or that it should stop after an earlier pass, then do not add
273 /// the pass. Finally, compare the current pass against the StartAfter
274 /// and StopAfter options and change the Started/Stopped flags accordingly.
275 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
276 assert(!Initialized && "PassConfig is immutable");
278 // Cache the Pass ID here in case the pass manager finds this pass is
279 // redundant with ones already scheduled / available, and deletes it.
280 // Fundamentally, once we add the pass to the manager, we no longer own it
281 // and shouldn't reference it.
282 AnalysisID PassID = P->getPassID();
284 if (Started && !Stopped) {
286 // Construct banner message before PM->add() as that may delete the pass.
287 if (AddingMachinePasses && (printAfter || verifyAfter))
288 Banner = std::string("After ") + std::string(P->getPassName());
290 if (AddingMachinePasses) {
292 addPrintPass(Banner);
294 addVerifyPass(Banner);
299 if (StopAfter == PassID)
301 if (StartAfter == PassID)
303 if (Stopped && !Started)
304 report_fatal_error("Cannot stop compilation after pass that is not run");
307 /// Add a CodeGen pass at this point in the pipeline after checking for target
308 /// and command line overrides.
310 /// addPass cannot return a pointer to the pass instance because is internal the
311 /// PassManager and the instance we create here may already be freed.
312 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
314 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
315 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
316 if (!FinalPtr.isValid())
320 if (FinalPtr.isInstance())
321 P = FinalPtr.getInstance();
323 P = Pass::createPass(FinalPtr.getID());
325 llvm_unreachable("Pass ID not registered");
327 AnalysisID FinalID = P->getPassID();
328 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
330 // Add the passes after the pass P if there is any.
331 for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
332 I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
334 if ((*I).first == PassID) {
335 assert((*I).second.isValid() && "Illegal Pass ID!");
337 if ((*I).second.isInstance())
338 NP = (*I).second.getInstance();
340 NP = Pass::createPass((*I).second.getID());
341 assert(NP && "Pass ID not registered");
343 addPass(NP, false, false);
349 void TargetPassConfig::printAndVerify(const std::string &Banner) {
350 addPrintPass(Banner);
351 addVerifyPass(Banner);
354 void TargetPassConfig::addPrintPass(const std::string &Banner) {
355 if (TM->shouldPrintMachineCode())
356 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
359 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
360 if (VerifyMachineCode)
361 PM->add(createMachineVerifierPass(Banner));
364 /// Add common target configurable passes that perform LLVM IR to IR transforms
365 /// following machine independent optimization.
366 void TargetPassConfig::addIRPasses() {
367 // Basic AliasAnalysis support.
368 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
369 // BasicAliasAnalysis wins if they disagree. This is intended to help
370 // support "obvious" type-punning idioms.
372 addPass(createCFLAliasAnalysisPass());
373 addPass(createTypeBasedAliasAnalysisPass());
374 addPass(createScopedNoAliasAAPass());
375 addPass(createBasicAliasAnalysisPass());
377 // Before running any passes, run the verifier to determine if the input
378 // coming from the front-end and/or optimizer is valid.
379 if (!DisableVerify) {
380 addPass(createVerifierPass());
381 addPass(createDebugInfoVerifierPass());
384 // Run loop strength reduction before anything else.
385 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
386 addPass(createLoopStrengthReducePass());
388 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
391 // Run GC lowering passes for builtin collectors
392 // TODO: add a pass insertion point here
393 addPass(createGCLoweringPass());
394 addPass(createShadowStackGCLoweringPass());
396 // Make sure that no unreachable blocks are instruction selected.
397 addPass(createUnreachableBlockEliminationPass());
399 // Prepare expensive constants for SelectionDAG.
400 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
401 addPass(createConstantHoistingPass());
403 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
404 addPass(createPartiallyInlineLibCallsPass());
407 /// Turn exception handling constructs into something the code generators can
409 void TargetPassConfig::addPassesToHandleExceptions() {
410 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
411 case ExceptionHandling::SjLj:
412 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
413 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
414 // catch info can get misplaced when a selector ends up more than one block
415 // removed from the parent invoke(s). This could happen when a landing
416 // pad is shared by multiple invokes and is also a target of a normal
417 // edge from elsewhere.
418 addPass(createSjLjEHPreparePass(TM));
420 case ExceptionHandling::DwarfCFI:
421 case ExceptionHandling::ARM:
422 addPass(createDwarfEHPass(TM));
424 case ExceptionHandling::WinEH:
425 // We support using both GCC-style and MSVC-style exceptions on Windows, so
426 // add both preparation passes. Each pass will only actually run if it
427 // recognizes the personality function.
428 addPass(createWinEHPass(TM));
429 addPass(createDwarfEHPass(TM));
431 case ExceptionHandling::None:
432 addPass(createLowerInvokePass());
434 // The lower invoke pass may create unreachable code. Remove it.
435 addPass(createUnreachableBlockEliminationPass());
440 /// Add pass to prepare the LLVM IR for code generation. This should be done
441 /// before exception handling preparation passes.
442 void TargetPassConfig::addCodeGenPrepare() {
443 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
444 addPass(createCodeGenPreparePass(TM));
445 addPass(createRewriteSymbolsPass());
448 /// Add common passes that perform LLVM IR to IR transforms in preparation for
449 /// instruction selection.
450 void TargetPassConfig::addISelPrepare() {
453 // Need to verify DebugInfo *before* creating the stack protector analysis.
454 // It's a function pass, and verifying between it and its users causes a
457 addPass(createDebugInfoVerifierPass());
459 addPass(createStackProtectorPass(TM));
462 addPass(createPrintFunctionPass(
463 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
465 // All passes which modify the LLVM IR are now complete; run the verifier
466 // to ensure that the IR is valid.
468 addPass(createVerifierPass());
471 /// Add the complete set of target-independent postISel code generator passes.
473 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
474 /// with nontrivial configuration or multiple passes are broken out below in
475 /// add%Stage routines.
477 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
478 /// addPre/Post methods with empty header implementations allow injecting
479 /// target-specific fixups just before or after major stages. Additionally,
480 /// targets have the flexibility to change pass order within a stage by
481 /// overriding default implementation of add%Stage routines below. Each
482 /// technique has maintainability tradeoffs because alternate pass orders are
483 /// not well supported. addPre/Post works better if the target pass is easily
484 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
485 /// the target should override the stage instead.
487 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
488 /// before/after any target-independent pass. But it's currently overkill.
489 void TargetPassConfig::addMachinePasses() {
490 AddingMachinePasses = true;
492 // Insert a machine instr printer pass after the specified pass.
493 // If -print-machineinstrs specified, print machineinstrs after all passes.
494 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
495 TM->Options.PrintMachineCode = true;
496 else if (!StringRef(PrintMachineInstrs.getValue())
497 .equals("option-unspecified")) {
498 const PassRegistry *PR = PassRegistry::getPassRegistry();
499 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
500 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
501 assert (TPI && IPI && "Pass ID not registered!");
502 const char *TID = (const char *)(TPI->getTypeInfo());
503 const char *IID = (const char *)(IPI->getTypeInfo());
504 insertPass(TID, IID);
507 // Print the instruction selected machine code...
508 printAndVerify("After Instruction Selection");
510 // Expand pseudo-instructions emitted by ISel.
511 addPass(&ExpandISelPseudosID);
513 // Add passes that optimize machine instructions in SSA form.
514 if (getOptLevel() != CodeGenOpt::None) {
515 addMachineSSAOptimization();
517 // If the target requests it, assign local variables to stack slots relative
518 // to one another and simplify frame index references where possible.
519 addPass(&LocalStackSlotAllocationID, false);
522 // Run pre-ra passes.
525 // Run register allocation and passes that are tightly coupled with it,
526 // including phi elimination and scheduling.
527 if (getOptimizeRegAlloc())
528 addOptimizedRegAlloc(createRegAllocPass(true));
530 addFastRegAlloc(createRegAllocPass(false));
532 // Run post-ra passes.
535 // Insert prolog/epilog code. Eliminate abstract frame index references...
536 addPass(&PrologEpilogCodeInserterID);
538 /// Add passes that optimize machine instructions after register allocation.
539 if (getOptLevel() != CodeGenOpt::None)
540 addMachineLateOptimization();
542 // Expand pseudo instructions before second scheduling pass.
543 addPass(&ExpandPostRAPseudosID);
545 // Run pre-sched2 passes.
548 // Second pass scheduler.
549 if (getOptLevel() != CodeGenOpt::None) {
551 addPass(&PostMachineSchedulerID);
553 addPass(&PostRASchedulerID);
559 addPass(createGCInfoPrinter(dbgs()), false, false);
562 // Basic block placement.
563 if (getOptLevel() != CodeGenOpt::None)
568 addPass(&StackMapLivenessID, false);
570 AddingMachinePasses = false;
573 /// Add passes that optimize machine instructions in SSA form.
574 void TargetPassConfig::addMachineSSAOptimization() {
575 // Pre-ra tail duplication.
576 addPass(&EarlyTailDuplicateID);
578 // Optimize PHIs before DCE: removing dead PHI cycles may make more
579 // instructions dead.
580 addPass(&OptimizePHIsID, false);
582 // This pass merges large allocas. StackSlotColoring is a different pass
583 // which merges spill slots.
584 addPass(&StackColoringID, false);
586 // If the target requests it, assign local variables to stack slots relative
587 // to one another and simplify frame index references where possible.
588 addPass(&LocalStackSlotAllocationID, false);
590 // With optimization, dead code should already be eliminated. However
591 // there is one known exception: lowered code for arguments that are only
592 // used by tail calls, where the tail calls reuse the incoming stack
593 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
594 addPass(&DeadMachineInstructionElimID);
596 // Allow targets to insert passes that improve instruction level parallelism,
597 // like if-conversion. Such passes will typically need dominator trees and
598 // loop info, just like LICM and CSE below.
601 addPass(&MachineLICMID, false);
602 addPass(&MachineCSEID, false);
603 addPass(&MachineSinkingID);
605 addPass(&PeepholeOptimizerID, false);
606 // Clean-up the dead code that may have been generated by peephole
608 addPass(&DeadMachineInstructionElimID);
611 //===---------------------------------------------------------------------===//
612 /// Register Allocation Pass Configuration
613 //===---------------------------------------------------------------------===//
615 bool TargetPassConfig::getOptimizeRegAlloc() const {
616 switch (OptimizeRegAlloc) {
617 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
618 case cl::BOU_TRUE: return true;
619 case cl::BOU_FALSE: return false;
621 llvm_unreachable("Invalid optimize-regalloc state");
624 /// RegisterRegAlloc's global Registry tracks allocator registration.
625 MachinePassRegistry RegisterRegAlloc::Registry;
627 /// A dummy default pass factory indicates whether the register allocator is
628 /// overridden on the command line.
629 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
630 static RegisterRegAlloc
631 defaultRegAlloc("default",
632 "pick register allocator based on -O option",
633 useDefaultRegisterAllocator);
635 /// -regalloc=... command line option.
636 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
637 RegisterPassParser<RegisterRegAlloc> >
639 cl::init(&useDefaultRegisterAllocator),
640 cl::desc("Register allocator to use"));
643 /// Instantiate the default register allocator pass for this target for either
644 /// the optimized or unoptimized allocation path. This will be added to the pass
645 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
646 /// in the optimized case.
648 /// A target that uses the standard regalloc pass order for fast or optimized
649 /// allocation may still override this for per-target regalloc
650 /// selection. But -regalloc=... always takes precedence.
651 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
653 return createGreedyRegisterAllocator();
655 return createFastRegisterAllocator();
658 /// Find and instantiate the register allocation pass requested by this target
659 /// at the current optimization level. Different register allocators are
660 /// defined as separate passes because they may require different analysis.
662 /// This helper ensures that the regalloc= option is always available,
663 /// even for targets that override the default allocator.
665 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
666 /// this can be folded into addPass.
667 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
668 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
670 // Initialize the global default.
673 RegisterRegAlloc::setDefault(RegAlloc);
675 if (Ctor != useDefaultRegisterAllocator)
678 // With no -regalloc= override, ask the target for a regalloc pass.
679 return createTargetRegisterAllocator(Optimized);
682 /// Return true if the default global register allocator is in use and
683 /// has not be overriden on the command line with '-regalloc=...'
684 bool TargetPassConfig::usingDefaultRegAlloc() const {
685 return RegAlloc.getNumOccurrences() == 0;
688 /// Add the minimum set of target-independent passes that are required for
689 /// register allocation. No coalescing or scheduling.
690 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
691 addPass(&PHIEliminationID, false);
692 addPass(&TwoAddressInstructionPassID, false);
694 addPass(RegAllocPass);
697 /// Add standard target-independent passes that are tightly coupled with
698 /// optimized register allocation, including coalescing, machine instruction
699 /// scheduling, and register allocation itself.
700 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
701 addPass(&ProcessImplicitDefsID, false);
703 // LiveVariables currently requires pure SSA form.
705 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
706 // LiveVariables can be removed completely, and LiveIntervals can be directly
707 // computed. (We still either need to regenerate kill flags after regalloc, or
708 // preferably fix the scavenger to not depend on them).
709 addPass(&LiveVariablesID, false);
711 // Edge splitting is smarter with machine loop info.
712 addPass(&MachineLoopInfoID, false);
713 addPass(&PHIEliminationID, false);
715 // Eventually, we want to run LiveIntervals before PHI elimination.
716 if (EarlyLiveIntervals)
717 addPass(&LiveIntervalsID, false);
719 addPass(&TwoAddressInstructionPassID, false);
720 addPass(&RegisterCoalescerID);
722 // PreRA instruction scheduling.
723 addPass(&MachineSchedulerID);
725 // Add the selected register allocation pass.
726 addPass(RegAllocPass);
728 // Allow targets to change the register assignments before rewriting.
731 // Finally rewrite virtual registers.
732 addPass(&VirtRegRewriterID);
734 // Perform stack slot coloring and post-ra machine LICM.
736 // FIXME: Re-enable coloring with register when it's capable of adding
738 addPass(&StackSlotColoringID);
740 // Run post-ra machine LICM to hoist reloads / remats.
742 // FIXME: can this move into MachineLateOptimization?
743 addPass(&PostRAMachineLICMID);
746 //===---------------------------------------------------------------------===//
747 /// Post RegAlloc Pass Configuration
748 //===---------------------------------------------------------------------===//
750 /// Add passes that optimize machine instructions after register allocation.
751 void TargetPassConfig::addMachineLateOptimization() {
752 // Branch folding must be run after regalloc and prolog/epilog insertion.
753 addPass(&BranchFolderPassID);
756 // Note that duplicating tail just increases code size and degrades
757 // performance for targets that require Structured Control Flow.
758 // In addition it can also make CFG irreducible. Thus we disable it.
759 if (!TM->requiresStructuredCFG())
760 addPass(&TailDuplicateID);
763 addPass(&MachineCopyPropagationID);
766 /// Add standard GC passes.
767 bool TargetPassConfig::addGCPasses() {
768 addPass(&GCMachineCodeAnalysisID, false);
772 /// Add standard basic block placement passes.
773 void TargetPassConfig::addBlockPlacement() {
774 if (addPass(&MachineBlockPlacementID, false)) {
775 // Run a separate pass to collect block placement statistics.
776 if (EnableBlockPlacementStats)
777 addPass(&MachineBlockPlacementStatsID);