1 //===-- Passes.cpp - Target independent code generation passes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
13 //===---------------------------------------------------------------------===//
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Analysis/Passes.h"
17 #include "llvm/CodeGen/GCStrategy.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/RegAllocRegistry.h"
20 #include "llvm/IR/IRPrintingPasses.h"
21 #include "llvm/IR/Verifier.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/PassManager.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
29 #include "llvm/Transforms/Scalar.h"
34 extern cl::opt<bool> EnableStackMapLiveness;
35 extern cl::opt<bool> EnablePatchPointLiveness;
38 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
39 cl::desc("Disable Post Regalloc"));
40 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
41 cl::desc("Disable branch folding"));
42 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
43 cl::desc("Disable tail duplication"));
44 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
45 cl::desc("Disable pre-register allocation tail duplication"));
46 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
47 cl::Hidden, cl::desc("Disable probability-driven block placement"));
48 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
49 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
50 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
51 cl::desc("Disable Stack Slot Coloring"));
52 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
53 cl::desc("Disable Machine Dead Code Elimination"));
54 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
55 cl::desc("Disable Early If-conversion"));
56 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
57 cl::desc("Disable Machine LICM"));
58 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
59 cl::desc("Disable Machine Common Subexpression Elimination"));
60 static cl::opt<cl::boolOrDefault>
61 OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
62 cl::desc("Enable optimized register allocation compilation path."));
63 static cl::opt<cl::boolOrDefault>
64 EnableMachineSched("enable-misched",
65 cl::desc("Enable the machine instruction scheduling pass."));
66 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
68 cl::desc("Disable Machine LICM"));
69 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
70 cl::desc("Disable Machine Sinking"));
71 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
72 cl::desc("Disable Loop Strength Reduction Pass"));
73 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
74 cl::Hidden, cl::desc("Disable ConstantHoisting"));
75 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
76 cl::desc("Disable Codegen Prepare"));
77 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
78 cl::desc("Disable Copy Propagation pass"));
79 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
80 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
81 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
82 cl::desc("Print LLVM IR input to isel pass"));
83 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
84 cl::desc("Dump garbage collector data"));
85 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
86 cl::desc("Verify generated machine code"),
87 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=nullptr));
88 static cl::opt<std::string>
89 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
90 cl::desc("Print machine instrs"),
91 cl::value_desc("pass-name"), cl::init("option-unspecified"));
93 // Temporary option to allow experimenting with MachineScheduler as a post-RA
94 // scheduler. Targets can "properly" enable this with
95 // substitutePass(&PostRASchedulerID, &MachineSchedulerID); Ideally it wouldn't
96 // be part of the standard pass pipeline, and the target would just add a PostRA
97 // scheduling pass wherever it wants.
98 static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
99 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
101 // Experimental option to run live interval analysis early.
102 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
103 cl::desc("Run live interval analysis earlier in the pipeline"));
105 /// Allow standard passes to be disabled by command line options. This supports
106 /// simple binary flags that either suppress the pass or do nothing.
107 /// i.e. -disable-mypass=false has no effect.
108 /// These should be converted to boolOrDefault in order to use applyOverride.
109 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
112 return IdentifyingPassPtr();
116 /// Allow Pass selection to be overriden by command line options. This supports
117 /// flags with ternary conditions. TargetID is passed through by default. The
118 /// pass is suppressed when the option is false. When the option is true, the
119 /// StandardID is selected if the target provides no default.
120 static IdentifyingPassPtr applyOverride(IdentifyingPassPtr TargetID,
121 cl::boolOrDefault Override,
122 AnalysisID StandardID) {
127 if (TargetID.isValid())
129 if (StandardID == nullptr)
130 report_fatal_error("Target cannot enable pass");
133 return IdentifyingPassPtr();
135 llvm_unreachable("Invalid command line option state");
138 /// Allow standard passes to be disabled by the command line, regardless of who
139 /// is adding the pass.
141 /// StandardID is the pass identified in the standard pass pipeline and provided
142 /// to addPass(). It may be a target-specific ID in the case that the target
143 /// directly adds its own pass, but in that case we harmlessly fall through.
145 /// TargetID is the pass that the target has configured to override StandardID.
147 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
148 /// pass to run. This allows multiple options to control a single pass depending
149 /// on where in the pipeline that pass is added.
150 static IdentifyingPassPtr overridePass(AnalysisID StandardID,
151 IdentifyingPassPtr TargetID) {
152 if (StandardID == &PostRASchedulerID)
153 return applyDisable(TargetID, DisablePostRA);
155 if (StandardID == &BranchFolderPassID)
156 return applyDisable(TargetID, DisableBranchFold);
158 if (StandardID == &TailDuplicateID)
159 return applyDisable(TargetID, DisableTailDuplicate);
161 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
162 return applyDisable(TargetID, DisableEarlyTailDup);
164 if (StandardID == &MachineBlockPlacementID)
165 return applyDisable(TargetID, DisableBlockPlacement);
167 if (StandardID == &StackSlotColoringID)
168 return applyDisable(TargetID, DisableSSC);
170 if (StandardID == &DeadMachineInstructionElimID)
171 return applyDisable(TargetID, DisableMachineDCE);
173 if (StandardID == &EarlyIfConverterID)
174 return applyDisable(TargetID, DisableEarlyIfConversion);
176 if (StandardID == &MachineLICMID)
177 return applyDisable(TargetID, DisableMachineLICM);
179 if (StandardID == &MachineCSEID)
180 return applyDisable(TargetID, DisableMachineCSE);
182 if (StandardID == &MachineSchedulerID)
183 return applyOverride(TargetID, EnableMachineSched, StandardID);
185 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
186 return applyDisable(TargetID, DisablePostRAMachineLICM);
188 if (StandardID == &MachineSinkingID)
189 return applyDisable(TargetID, DisableMachineSink);
191 if (StandardID == &MachineCopyPropagationID)
192 return applyDisable(TargetID, DisableCopyProp);
197 //===---------------------------------------------------------------------===//
199 //===---------------------------------------------------------------------===//
201 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
202 "Target Pass Configuration", false, false)
203 char TargetPassConfig::ID = 0;
206 char TargetPassConfig::EarlyTailDuplicateID = 0;
207 char TargetPassConfig::PostRAMachineLICMID = 0;
210 class PassConfigImpl {
212 // List of passes explicitly substituted by this target. Normally this is
213 // empty, but it is a convenient way to suppress or replace specific passes
214 // that are part of a standard pass pipeline without overridding the entire
215 // pipeline. This mechanism allows target options to inherit a standard pass's
216 // user interface. For example, a target may disable a standard pass by
217 // default by substituting a pass ID of zero, and the user may still enable
218 // that standard pass with an explicit command line option.
219 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
221 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
222 /// is inserted after each instance of the first one.
223 SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses;
227 // Out of line virtual method.
228 TargetPassConfig::~TargetPassConfig() {
232 // Out of line constructor provides default values for pass options and
233 // registers all common codegen passes.
234 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
235 : ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr),
236 Started(true), Stopped(false), TM(tm), Impl(nullptr), Initialized(false),
237 DisableVerify(false),
238 EnableTailMerge(true) {
240 Impl = new PassConfigImpl();
242 // Register all target independent codegen passes to activate their PassIDs,
243 // including this pass itself.
244 initializeCodeGen(*PassRegistry::getPassRegistry());
246 // Substitute Pseudo Pass IDs for real ones.
247 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
248 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
250 // Temporarily disable experimental passes.
251 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
252 if (!ST.useMachineScheduler())
253 disablePass(&MachineSchedulerID);
256 /// Insert InsertedPassID pass after TargetPassID.
257 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
258 IdentifyingPassPtr InsertedPassID) {
259 assert(((!InsertedPassID.isInstance() &&
260 TargetPassID != InsertedPassID.getID()) ||
261 (InsertedPassID.isInstance() &&
262 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
263 "Insert a pass after itself!");
264 std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID);
265 Impl->InsertedPasses.push_back(P);
268 /// createPassConfig - Create a pass configuration object to be used by
269 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
271 /// Targets may override this to extend TargetPassConfig.
272 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
273 return new TargetPassConfig(this, PM);
276 TargetPassConfig::TargetPassConfig()
277 : ImmutablePass(ID), PM(nullptr) {
278 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
281 // Helper to verify the analysis is really immutable.
282 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
283 assert(!Initialized && "PassConfig is immutable");
287 void TargetPassConfig::substitutePass(AnalysisID StandardID,
288 IdentifyingPassPtr TargetID) {
289 Impl->TargetPasses[StandardID] = TargetID;
292 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
293 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
294 I = Impl->TargetPasses.find(ID);
295 if (I == Impl->TargetPasses.end())
300 /// Add a pass to the PassManager if that pass is supposed to be run. If the
301 /// Started/Stopped flags indicate either that the compilation should start at
302 /// a later pass or that it should stop after an earlier pass, then do not add
303 /// the pass. Finally, compare the current pass against the StartAfter
304 /// and StopAfter options and change the Started/Stopped flags accordingly.
305 void TargetPassConfig::addPass(Pass *P) {
306 assert(!Initialized && "PassConfig is immutable");
308 // Cache the Pass ID here in case the pass manager finds this pass is
309 // redundant with ones already scheduled / available, and deletes it.
310 // Fundamentally, once we add the pass to the manager, we no longer own it
311 // and shouldn't reference it.
312 AnalysisID PassID = P->getPassID();
314 if (Started && !Stopped)
318 if (StopAfter == PassID)
320 if (StartAfter == PassID)
322 if (Stopped && !Started)
323 report_fatal_error("Cannot stop compilation after pass that is not run");
326 /// Add a CodeGen pass at this point in the pipeline after checking for target
327 /// and command line overrides.
329 /// addPass cannot return a pointer to the pass instance because is internal the
330 /// PassManager and the instance we create here may already be freed.
331 AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
332 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
333 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
334 if (!FinalPtr.isValid())
338 if (FinalPtr.isInstance())
339 P = FinalPtr.getInstance();
341 P = Pass::createPass(FinalPtr.getID());
343 llvm_unreachable("Pass ID not registered");
345 AnalysisID FinalID = P->getPassID();
346 addPass(P); // Ends the lifetime of P.
348 // Add the passes after the pass P if there is any.
349 for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
350 I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
352 if ((*I).first == PassID) {
353 assert((*I).second.isValid() && "Illegal Pass ID!");
355 if ((*I).second.isInstance())
356 NP = (*I).second.getInstance();
358 NP = Pass::createPass((*I).second.getID());
359 assert(NP && "Pass ID not registered");
367 void TargetPassConfig::printAndVerify(const char *Banner) {
368 if (TM->shouldPrintMachineCode())
369 addPass(createMachineFunctionPrinterPass(dbgs(), Banner));
371 if (VerifyMachineCode)
372 addPass(createMachineVerifierPass(Banner));
375 /// Add common target configurable passes that perform LLVM IR to IR transforms
376 /// following machine independent optimization.
377 void TargetPassConfig::addIRPasses() {
378 // Basic AliasAnalysis support.
379 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
380 // BasicAliasAnalysis wins if they disagree. This is intended to help
381 // support "obvious" type-punning idioms.
382 addPass(createTypeBasedAliasAnalysisPass());
383 addPass(createBasicAliasAnalysisPass());
385 // Before running any passes, run the verifier to determine if the input
386 // coming from the front-end and/or optimizer is valid.
387 if (!DisableVerify) {
388 addPass(createVerifierPass());
389 addPass(createDebugInfoVerifierPass());
392 // Run loop strength reduction before anything else.
393 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
394 addPass(createLoopStrengthReducePass());
396 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
399 addPass(createGCLoweringPass());
401 // Make sure that no unreachable blocks are instruction selected.
402 addPass(createUnreachableBlockEliminationPass());
404 // Prepare expensive constants for SelectionDAG.
405 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
406 addPass(createConstantHoistingPass());
409 /// Turn exception handling constructs into something the code generators can
411 void TargetPassConfig::addPassesToHandleExceptions() {
412 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
413 case ExceptionHandling::SjLj:
414 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
415 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
416 // catch info can get misplaced when a selector ends up more than one block
417 // removed from the parent invoke(s). This could happen when a landing
418 // pad is shared by multiple invokes and is also a target of a normal
419 // edge from elsewhere.
420 addPass(createSjLjEHPreparePass(TM));
422 case ExceptionHandling::DwarfCFI:
423 case ExceptionHandling::ARM:
424 case ExceptionHandling::Win64:
425 addPass(createDwarfEHPass(TM));
427 case ExceptionHandling::None:
428 addPass(createLowerInvokePass());
430 // The lower invoke pass may create unreachable code. Remove it.
431 addPass(createUnreachableBlockEliminationPass());
436 /// Add pass to prepare the LLVM IR for code generation. This should be done
437 /// before exception handling preparation passes.
438 void TargetPassConfig::addCodeGenPrepare() {
439 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
440 addPass(createCodeGenPreparePass(TM));
443 /// Add common passes that perform LLVM IR to IR transforms in preparation for
444 /// instruction selection.
445 void TargetPassConfig::addISelPrepare() {
448 // Need to verify DebugInfo *before* creating the stack protector analysis.
449 // It's a function pass, and verifying between it and its users causes a
452 addPass(createDebugInfoVerifierPass());
454 addPass(createStackProtectorPass(TM));
457 addPass(createPrintFunctionPass(
458 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
460 // All passes which modify the LLVM IR are now complete; run the verifier
461 // to ensure that the IR is valid.
463 addPass(createVerifierPass());
466 /// Add the complete set of target-independent postISel code generator passes.
468 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
469 /// with nontrivial configuration or multiple passes are broken out below in
470 /// add%Stage routines.
472 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
473 /// addPre/Post methods with empty header implementations allow injecting
474 /// target-specific fixups just before or after major stages. Additionally,
475 /// targets have the flexibility to change pass order within a stage by
476 /// overriding default implementation of add%Stage routines below. Each
477 /// technique has maintainability tradeoffs because alternate pass orders are
478 /// not well supported. addPre/Post works better if the target pass is easily
479 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
480 /// the target should override the stage instead.
482 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
483 /// before/after any target-independent pass. But it's currently overkill.
484 void TargetPassConfig::addMachinePasses() {
485 // Insert a machine instr printer pass after the specified pass.
486 // If -print-machineinstrs specified, print machineinstrs after all passes.
487 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
488 TM->Options.PrintMachineCode = true;
489 else if (!StringRef(PrintMachineInstrs.getValue())
490 .equals("option-unspecified")) {
491 const PassRegistry *PR = PassRegistry::getPassRegistry();
492 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
493 const PassInfo *IPI = PR->getPassInfo(StringRef("print-machineinstrs"));
494 assert (TPI && IPI && "Pass ID not registered!");
495 const char *TID = (const char *)(TPI->getTypeInfo());
496 const char *IID = (const char *)(IPI->getTypeInfo());
497 insertPass(TID, IID);
500 // Print the instruction selected machine code...
501 printAndVerify("After Instruction Selection");
503 // Expand pseudo-instructions emitted by ISel.
504 if (addPass(&ExpandISelPseudosID))
505 printAndVerify("After ExpandISelPseudos");
507 // Add passes that optimize machine instructions in SSA form.
508 if (getOptLevel() != CodeGenOpt::None) {
509 addMachineSSAOptimization();
511 // If the target requests it, assign local variables to stack slots relative
512 // to one another and simplify frame index references where possible.
513 addPass(&LocalStackSlotAllocationID);
516 // Run pre-ra passes.
517 if (addPreRegAlloc())
518 printAndVerify("After PreRegAlloc passes");
520 // Run register allocation and passes that are tightly coupled with it,
521 // including phi elimination and scheduling.
522 if (getOptimizeRegAlloc())
523 addOptimizedRegAlloc(createRegAllocPass(true));
525 addFastRegAlloc(createRegAllocPass(false));
527 // Run post-ra passes.
528 if (addPostRegAlloc())
529 printAndVerify("After PostRegAlloc passes");
531 // Insert prolog/epilog code. Eliminate abstract frame index references...
532 addPass(&PrologEpilogCodeInserterID);
533 printAndVerify("After PrologEpilogCodeInserter");
535 /// Add passes that optimize machine instructions after register allocation.
536 if (getOptLevel() != CodeGenOpt::None)
537 addMachineLateOptimization();
539 // Expand pseudo instructions before second scheduling pass.
540 addPass(&ExpandPostRAPseudosID);
541 printAndVerify("After ExpandPostRAPseudos");
543 // Run pre-sched2 passes.
545 printAndVerify("After PreSched2 passes");
547 // Second pass scheduler.
548 if (getOptLevel() != CodeGenOpt::None) {
550 addPass(&PostMachineSchedulerID);
552 addPass(&PostRASchedulerID);
553 printAndVerify("After PostRAScheduler");
559 addPass(createGCInfoPrinter(dbgs()));
562 // Basic block placement.
563 if (getOptLevel() != CodeGenOpt::None)
566 if (addPreEmitPass())
567 printAndVerify("After PreEmit passes");
569 if (EnableStackMapLiveness || EnablePatchPointLiveness)
570 addPass(&StackMapLivenessID);
573 /// Add passes that optimize machine instructions in SSA form.
574 void TargetPassConfig::addMachineSSAOptimization() {
575 // Pre-ra tail duplication.
576 if (addPass(&EarlyTailDuplicateID))
577 printAndVerify("After Pre-RegAlloc TailDuplicate");
579 // Optimize PHIs before DCE: removing dead PHI cycles may make more
580 // instructions dead.
581 addPass(&OptimizePHIsID);
583 // This pass merges large allocas. StackSlotColoring is a different pass
584 // which merges spill slots.
585 addPass(&StackColoringID);
587 // If the target requests it, assign local variables to stack slots relative
588 // to one another and simplify frame index references where possible.
589 addPass(&LocalStackSlotAllocationID);
591 // With optimization, dead code should already be eliminated. However
592 // there is one known exception: lowered code for arguments that are only
593 // used by tail calls, where the tail calls reuse the incoming stack
594 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
595 addPass(&DeadMachineInstructionElimID);
596 printAndVerify("After codegen DCE pass");
598 // Allow targets to insert passes that improve instruction level parallelism,
599 // like if-conversion. Such passes will typically need dominator trees and
600 // loop info, just like LICM and CSE below.
602 printAndVerify("After ILP optimizations");
604 addPass(&MachineLICMID);
605 addPass(&MachineCSEID);
606 addPass(&MachineSinkingID);
607 printAndVerify("After Machine LICM, CSE and Sinking passes");
609 addPass(&PeepholeOptimizerID);
610 printAndVerify("After codegen peephole optimization pass");
613 //===---------------------------------------------------------------------===//
614 /// Register Allocation Pass Configuration
615 //===---------------------------------------------------------------------===//
617 bool TargetPassConfig::getOptimizeRegAlloc() const {
618 switch (OptimizeRegAlloc) {
619 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
620 case cl::BOU_TRUE: return true;
621 case cl::BOU_FALSE: return false;
623 llvm_unreachable("Invalid optimize-regalloc state");
626 /// RegisterRegAlloc's global Registry tracks allocator registration.
627 MachinePassRegistry RegisterRegAlloc::Registry;
629 /// A dummy default pass factory indicates whether the register allocator is
630 /// overridden on the command line.
631 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
632 static RegisterRegAlloc
633 defaultRegAlloc("default",
634 "pick register allocator based on -O option",
635 useDefaultRegisterAllocator);
637 /// -regalloc=... command line option.
638 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
639 RegisterPassParser<RegisterRegAlloc> >
641 cl::init(&useDefaultRegisterAllocator),
642 cl::desc("Register allocator to use"));
645 /// Instantiate the default register allocator pass for this target for either
646 /// the optimized or unoptimized allocation path. This will be added to the pass
647 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
648 /// in the optimized case.
650 /// A target that uses the standard regalloc pass order for fast or optimized
651 /// allocation may still override this for per-target regalloc
652 /// selection. But -regalloc=... always takes precedence.
653 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
655 return createGreedyRegisterAllocator();
657 return createFastRegisterAllocator();
660 /// Find and instantiate the register allocation pass requested by this target
661 /// at the current optimization level. Different register allocators are
662 /// defined as separate passes because they may require different analysis.
664 /// This helper ensures that the regalloc= option is always available,
665 /// even for targets that override the default allocator.
667 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
668 /// this can be folded into addPass.
669 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
670 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
672 // Initialize the global default.
675 RegisterRegAlloc::setDefault(RegAlloc);
677 if (Ctor != useDefaultRegisterAllocator)
680 // With no -regalloc= override, ask the target for a regalloc pass.
681 return createTargetRegisterAllocator(Optimized);
684 /// Add the minimum set of target-independent passes that are required for
685 /// register allocation. No coalescing or scheduling.
686 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
687 addPass(&PHIEliminationID);
688 addPass(&TwoAddressInstructionPassID);
690 addPass(RegAllocPass);
691 printAndVerify("After Register Allocation");
694 /// Add standard target-independent passes that are tightly coupled with
695 /// optimized register allocation, including coalescing, machine instruction
696 /// scheduling, and register allocation itself.
697 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
698 addPass(&ProcessImplicitDefsID);
700 // LiveVariables currently requires pure SSA form.
702 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
703 // LiveVariables can be removed completely, and LiveIntervals can be directly
704 // computed. (We still either need to regenerate kill flags after regalloc, or
705 // preferably fix the scavenger to not depend on them).
706 addPass(&LiveVariablesID);
708 // Edge splitting is smarter with machine loop info.
709 addPass(&MachineLoopInfoID);
710 addPass(&PHIEliminationID);
712 // Eventually, we want to run LiveIntervals before PHI elimination.
713 if (EarlyLiveIntervals)
714 addPass(&LiveIntervalsID);
716 addPass(&TwoAddressInstructionPassID);
717 addPass(&RegisterCoalescerID);
719 // PreRA instruction scheduling.
720 if (addPass(&MachineSchedulerID))
721 printAndVerify("After Machine Scheduling");
723 // Add the selected register allocation pass.
724 addPass(RegAllocPass);
725 printAndVerify("After Register Allocation, before rewriter");
727 // Allow targets to change the register assignments before rewriting.
729 printAndVerify("After pre-rewrite passes");
731 // Finally rewrite virtual registers.
732 addPass(&VirtRegRewriterID);
733 printAndVerify("After Virtual Register Rewriter");
735 // Perform stack slot coloring and post-ra machine LICM.
737 // FIXME: Re-enable coloring with register when it's capable of adding
739 addPass(&StackSlotColoringID);
741 // Run post-ra machine LICM to hoist reloads / remats.
743 // FIXME: can this move into MachineLateOptimization?
744 addPass(&PostRAMachineLICMID);
746 printAndVerify("After StackSlotColoring and postra Machine LICM");
749 //===---------------------------------------------------------------------===//
750 /// Post RegAlloc Pass Configuration
751 //===---------------------------------------------------------------------===//
753 /// Add passes that optimize machine instructions after register allocation.
754 void TargetPassConfig::addMachineLateOptimization() {
755 // Branch folding must be run after regalloc and prolog/epilog insertion.
756 if (addPass(&BranchFolderPassID))
757 printAndVerify("After BranchFolding");
760 // Note that duplicating tail just increases code size and degrades
761 // performance for targets that require Structured Control Flow.
762 // In addition it can also make CFG irreducible. Thus we disable it.
763 if (!TM->requiresStructuredCFG() && addPass(&TailDuplicateID))
764 printAndVerify("After TailDuplicate");
767 if (addPass(&MachineCopyPropagationID))
768 printAndVerify("After copy propagation pass");
771 /// Add standard GC passes.
772 bool TargetPassConfig::addGCPasses() {
773 addPass(&GCMachineCodeAnalysisID);
777 /// Add standard basic block placement passes.
778 void TargetPassConfig::addBlockPlacement() {
779 if (addPass(&MachineBlockPlacementID)) {
780 // Run a separate pass to collect block placement statistics.
781 if (EnableBlockPlacementStats)
782 addPass(&MachineBlockPlacementStatsID);
784 printAndVerify("After machine block placement.");