1 //===-- Passes.cpp - Target independent code generation passes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
13 //===---------------------------------------------------------------------===//
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Analysis/Passes.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/RegAllocRegistry.h"
19 #include "llvm/IR/IRPrintingPasses.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/IR/Verifier.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Transforms/Scalar.h"
28 #include "llvm/Transforms/Utils/SymbolRewriter.h"
32 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
33 cl::desc("Disable Post Regalloc"));
34 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
35 cl::desc("Disable branch folding"));
36 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
37 cl::desc("Disable tail duplication"));
38 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
39 cl::desc("Disable pre-register allocation tail duplication"));
40 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
41 cl::Hidden, cl::desc("Disable probability-driven block placement"));
42 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
43 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
44 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
45 cl::desc("Disable Stack Slot Coloring"));
46 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
47 cl::desc("Disable Machine Dead Code Elimination"));
48 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
49 cl::desc("Disable Early If-conversion"));
50 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
51 cl::desc("Disable Machine LICM"));
52 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
53 cl::desc("Disable Machine Common Subexpression Elimination"));
54 static cl::opt<cl::boolOrDefault>
55 OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
56 cl::desc("Enable optimized register allocation compilation path."));
57 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
59 cl::desc("Disable Machine LICM"));
60 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
61 cl::desc("Disable Machine Sinking"));
62 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
63 cl::desc("Disable Loop Strength Reduction Pass"));
64 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
65 cl::Hidden, cl::desc("Disable ConstantHoisting"));
66 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
67 cl::desc("Disable Codegen Prepare"));
68 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
69 cl::desc("Disable Copy Propagation pass"));
70 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
71 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
72 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
73 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
74 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
75 cl::desc("Print LLVM IR input to isel pass"));
76 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
77 cl::desc("Dump garbage collector data"));
78 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
79 cl::desc("Verify generated machine code"),
83 static cl::opt<std::string>
84 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
85 cl::desc("Print machine instrs"),
86 cl::value_desc("pass-name"), cl::init("option-unspecified"));
88 // Temporary option to allow experimenting with MachineScheduler as a post-RA
89 // scheduler. Targets can "properly" enable this with
90 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); Ideally it
91 // wouldn't be part of the standard pass pipeline, and the target would just add
92 // a PostRA scheduling pass wherever it wants.
93 static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
94 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
96 // Experimental option to run live interval analysis early.
97 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
98 cl::desc("Run live interval analysis earlier in the pipeline"));
100 static cl::opt<bool> UseCFLAA("use-cfl-aa-in-codegen",
101 cl::init(false), cl::Hidden,
102 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"));
104 /// Allow standard passes to be disabled by command line options. This supports
105 /// simple binary flags that either suppress the pass or do nothing.
106 /// i.e. -disable-mypass=false has no effect.
107 /// These should be converted to boolOrDefault in order to use applyOverride.
108 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
111 return IdentifyingPassPtr();
115 /// Allow standard passes to be disabled by the command line, regardless of who
116 /// is adding the pass.
118 /// StandardID is the pass identified in the standard pass pipeline and provided
119 /// to addPass(). It may be a target-specific ID in the case that the target
120 /// directly adds its own pass, but in that case we harmlessly fall through.
122 /// TargetID is the pass that the target has configured to override StandardID.
124 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
125 /// pass to run. This allows multiple options to control a single pass depending
126 /// on where in the pipeline that pass is added.
127 static IdentifyingPassPtr overridePass(AnalysisID StandardID,
128 IdentifyingPassPtr TargetID) {
129 if (StandardID == &PostRASchedulerID)
130 return applyDisable(TargetID, DisablePostRA);
132 if (StandardID == &BranchFolderPassID)
133 return applyDisable(TargetID, DisableBranchFold);
135 if (StandardID == &TailDuplicateID)
136 return applyDisable(TargetID, DisableTailDuplicate);
138 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
139 return applyDisable(TargetID, DisableEarlyTailDup);
141 if (StandardID == &MachineBlockPlacementID)
142 return applyDisable(TargetID, DisableBlockPlacement);
144 if (StandardID == &StackSlotColoringID)
145 return applyDisable(TargetID, DisableSSC);
147 if (StandardID == &DeadMachineInstructionElimID)
148 return applyDisable(TargetID, DisableMachineDCE);
150 if (StandardID == &EarlyIfConverterID)
151 return applyDisable(TargetID, DisableEarlyIfConversion);
153 if (StandardID == &MachineLICMID)
154 return applyDisable(TargetID, DisableMachineLICM);
156 if (StandardID == &MachineCSEID)
157 return applyDisable(TargetID, DisableMachineCSE);
159 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
160 return applyDisable(TargetID, DisablePostRAMachineLICM);
162 if (StandardID == &MachineSinkingID)
163 return applyDisable(TargetID, DisableMachineSink);
165 if (StandardID == &MachineCopyPropagationID)
166 return applyDisable(TargetID, DisableCopyProp);
171 //===---------------------------------------------------------------------===//
173 //===---------------------------------------------------------------------===//
175 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
176 "Target Pass Configuration", false, false)
177 char TargetPassConfig::ID = 0;
180 char TargetPassConfig::EarlyTailDuplicateID = 0;
181 char TargetPassConfig::PostRAMachineLICMID = 0;
184 class PassConfigImpl {
186 // List of passes explicitly substituted by this target. Normally this is
187 // empty, but it is a convenient way to suppress or replace specific passes
188 // that are part of a standard pass pipeline without overridding the entire
189 // pipeline. This mechanism allows target options to inherit a standard pass's
190 // user interface. For example, a target may disable a standard pass by
191 // default by substituting a pass ID of zero, and the user may still enable
192 // that standard pass with an explicit command line option.
193 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
195 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
196 /// is inserted after each instance of the first one.
197 SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses;
201 // Out of line virtual method.
202 TargetPassConfig::~TargetPassConfig() {
206 // Out of line constructor provides default values for pass options and
207 // registers all common codegen passes.
208 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
209 : ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr),
210 Started(true), Stopped(false), AddingMachinePasses(false), TM(tm),
211 Impl(nullptr), Initialized(false), DisableVerify(false),
212 EnableTailMerge(true) {
214 Impl = new PassConfigImpl();
216 // Register all target independent codegen passes to activate their PassIDs,
217 // including this pass itself.
218 initializeCodeGen(*PassRegistry::getPassRegistry());
220 // Substitute Pseudo Pass IDs for real ones.
221 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
222 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
225 /// Insert InsertedPassID pass after TargetPassID.
226 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
227 IdentifyingPassPtr InsertedPassID) {
228 assert(((!InsertedPassID.isInstance() &&
229 TargetPassID != InsertedPassID.getID()) ||
230 (InsertedPassID.isInstance() &&
231 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
232 "Insert a pass after itself!");
233 std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID);
234 Impl->InsertedPasses.push_back(P);
237 /// createPassConfig - Create a pass configuration object to be used by
238 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
240 /// Targets may override this to extend TargetPassConfig.
241 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
242 return new TargetPassConfig(this, PM);
245 TargetPassConfig::TargetPassConfig()
246 : ImmutablePass(ID), PM(nullptr) {
247 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
250 // Helper to verify the analysis is really immutable.
251 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
252 assert(!Initialized && "PassConfig is immutable");
256 void TargetPassConfig::substitutePass(AnalysisID StandardID,
257 IdentifyingPassPtr TargetID) {
258 Impl->TargetPasses[StandardID] = TargetID;
261 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
262 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
263 I = Impl->TargetPasses.find(ID);
264 if (I == Impl->TargetPasses.end())
269 /// Add a pass to the PassManager if that pass is supposed to be run. If the
270 /// Started/Stopped flags indicate either that the compilation should start at
271 /// a later pass or that it should stop after an earlier pass, then do not add
272 /// the pass. Finally, compare the current pass against the StartAfter
273 /// and StopAfter options and change the Started/Stopped flags accordingly.
274 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
275 assert(!Initialized && "PassConfig is immutable");
277 // Cache the Pass ID here in case the pass manager finds this pass is
278 // redundant with ones already scheduled / available, and deletes it.
279 // Fundamentally, once we add the pass to the manager, we no longer own it
280 // and shouldn't reference it.
281 AnalysisID PassID = P->getPassID();
283 if (Started && !Stopped) {
285 // Construct banner message before PM->add() as that may delete the pass.
286 if (AddingMachinePasses && (printAfter || verifyAfter))
287 Banner = std::string("After ") + std::string(P->getPassName());
289 if (AddingMachinePasses) {
291 addPrintPass(Banner);
293 addVerifyPass(Banner);
298 if (StopAfter == PassID)
300 if (StartAfter == PassID)
302 if (Stopped && !Started)
303 report_fatal_error("Cannot stop compilation after pass that is not run");
306 /// Add a CodeGen pass at this point in the pipeline after checking for target
307 /// and command line overrides.
309 /// addPass cannot return a pointer to the pass instance because is internal the
310 /// PassManager and the instance we create here may already be freed.
311 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
313 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
314 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
315 if (!FinalPtr.isValid())
319 if (FinalPtr.isInstance())
320 P = FinalPtr.getInstance();
322 P = Pass::createPass(FinalPtr.getID());
324 llvm_unreachable("Pass ID not registered");
326 AnalysisID FinalID = P->getPassID();
327 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
329 // Add the passes after the pass P if there is any.
330 for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
331 I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
333 if ((*I).first == PassID) {
334 assert((*I).second.isValid() && "Illegal Pass ID!");
336 if ((*I).second.isInstance())
337 NP = (*I).second.getInstance();
339 NP = Pass::createPass((*I).second.getID());
340 assert(NP && "Pass ID not registered");
342 addPass(NP, false, false);
348 void TargetPassConfig::printAndVerify(const std::string &Banner) {
349 addPrintPass(Banner);
350 addVerifyPass(Banner);
353 void TargetPassConfig::addPrintPass(const std::string &Banner) {
354 if (TM->shouldPrintMachineCode())
355 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
358 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
359 if (VerifyMachineCode)
360 PM->add(createMachineVerifierPass(Banner));
363 /// Add common target configurable passes that perform LLVM IR to IR transforms
364 /// following machine independent optimization.
365 void TargetPassConfig::addIRPasses() {
366 // Basic AliasAnalysis support.
367 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
368 // BasicAliasAnalysis wins if they disagree. This is intended to help
369 // support "obvious" type-punning idioms.
371 addPass(createCFLAliasAnalysisPass());
372 addPass(createTypeBasedAliasAnalysisPass());
373 addPass(createScopedNoAliasAAPass());
374 addPass(createBasicAliasAnalysisPass());
376 // Before running any passes, run the verifier to determine if the input
377 // coming from the front-end and/or optimizer is valid.
379 addPass(createVerifierPass());
381 // Run loop strength reduction before anything else.
382 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
383 addPass(createLoopStrengthReducePass());
385 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
388 // Run GC lowering passes for builtin collectors
389 // TODO: add a pass insertion point here
390 addPass(createGCLoweringPass());
391 addPass(createShadowStackGCLoweringPass());
393 // Make sure that no unreachable blocks are instruction selected.
394 addPass(createUnreachableBlockEliminationPass());
396 // Prepare expensive constants for SelectionDAG.
397 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
398 addPass(createConstantHoistingPass());
400 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
401 addPass(createPartiallyInlineLibCallsPass());
404 /// Turn exception handling constructs into something the code generators can
406 void TargetPassConfig::addPassesToHandleExceptions() {
407 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
408 case ExceptionHandling::SjLj:
409 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
410 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
411 // catch info can get misplaced when a selector ends up more than one block
412 // removed from the parent invoke(s). This could happen when a landing
413 // pad is shared by multiple invokes and is also a target of a normal
414 // edge from elsewhere.
415 addPass(createSjLjEHPreparePass(TM));
417 case ExceptionHandling::DwarfCFI:
418 case ExceptionHandling::ARM:
419 addPass(createDwarfEHPass(TM));
421 case ExceptionHandling::WinEH:
422 // We support using both GCC-style and MSVC-style exceptions on Windows, so
423 // add both preparation passes. Each pass will only actually run if it
424 // recognizes the personality function.
425 addPass(createWinEHPass(TM));
426 addPass(createDwarfEHPass(TM));
428 case ExceptionHandling::None:
429 addPass(createLowerInvokePass());
431 // The lower invoke pass may create unreachable code. Remove it.
432 addPass(createUnreachableBlockEliminationPass());
437 /// Add pass to prepare the LLVM IR for code generation. This should be done
438 /// before exception handling preparation passes.
439 void TargetPassConfig::addCodeGenPrepare() {
440 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
441 addPass(createCodeGenPreparePass(TM));
442 addPass(createRewriteSymbolsPass());
445 /// Add common passes that perform LLVM IR to IR transforms in preparation for
446 /// instruction selection.
447 void TargetPassConfig::addISelPrepare() {
450 addPass(createStackProtectorPass(TM));
453 addPass(createPrintFunctionPass(
454 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
456 // All passes which modify the LLVM IR are now complete; run the verifier
457 // to ensure that the IR is valid.
459 addPass(createVerifierPass());
462 /// Add the complete set of target-independent postISel code generator passes.
464 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
465 /// with nontrivial configuration or multiple passes are broken out below in
466 /// add%Stage routines.
468 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
469 /// addPre/Post methods with empty header implementations allow injecting
470 /// target-specific fixups just before or after major stages. Additionally,
471 /// targets have the flexibility to change pass order within a stage by
472 /// overriding default implementation of add%Stage routines below. Each
473 /// technique has maintainability tradeoffs because alternate pass orders are
474 /// not well supported. addPre/Post works better if the target pass is easily
475 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
476 /// the target should override the stage instead.
478 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
479 /// before/after any target-independent pass. But it's currently overkill.
480 void TargetPassConfig::addMachinePasses() {
481 AddingMachinePasses = true;
483 // Insert a machine instr printer pass after the specified pass.
484 // If -print-machineinstrs specified, print machineinstrs after all passes.
485 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
486 TM->Options.PrintMachineCode = true;
487 else if (!StringRef(PrintMachineInstrs.getValue())
488 .equals("option-unspecified")) {
489 const PassRegistry *PR = PassRegistry::getPassRegistry();
490 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
491 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
492 assert (TPI && IPI && "Pass ID not registered!");
493 const char *TID = (const char *)(TPI->getTypeInfo());
494 const char *IID = (const char *)(IPI->getTypeInfo());
495 insertPass(TID, IID);
498 // Print the instruction selected machine code...
499 printAndVerify("After Instruction Selection");
501 // Expand pseudo-instructions emitted by ISel.
502 addPass(&ExpandISelPseudosID);
504 // Add passes that optimize machine instructions in SSA form.
505 if (getOptLevel() != CodeGenOpt::None) {
506 addMachineSSAOptimization();
508 // If the target requests it, assign local variables to stack slots relative
509 // to one another and simplify frame index references where possible.
510 addPass(&LocalStackSlotAllocationID, false);
513 // Run pre-ra passes.
516 // Run register allocation and passes that are tightly coupled with it,
517 // including phi elimination and scheduling.
518 if (getOptimizeRegAlloc())
519 addOptimizedRegAlloc(createRegAllocPass(true));
521 addFastRegAlloc(createRegAllocPass(false));
523 // Run post-ra passes.
526 // Insert prolog/epilog code. Eliminate abstract frame index references...
527 addPass(&PrologEpilogCodeInserterID);
529 /// Add passes that optimize machine instructions after register allocation.
530 if (getOptLevel() != CodeGenOpt::None)
531 addMachineLateOptimization();
533 // Expand pseudo instructions before second scheduling pass.
534 addPass(&ExpandPostRAPseudosID);
536 // Run pre-sched2 passes.
539 // Second pass scheduler.
540 if (getOptLevel() != CodeGenOpt::None) {
542 addPass(&PostMachineSchedulerID);
544 addPass(&PostRASchedulerID);
550 addPass(createGCInfoPrinter(dbgs()), false, false);
553 // Basic block placement.
554 if (getOptLevel() != CodeGenOpt::None)
559 addPass(&StackMapLivenessID, false);
561 AddingMachinePasses = false;
564 /// Add passes that optimize machine instructions in SSA form.
565 void TargetPassConfig::addMachineSSAOptimization() {
566 // Pre-ra tail duplication.
567 addPass(&EarlyTailDuplicateID);
569 // Optimize PHIs before DCE: removing dead PHI cycles may make more
570 // instructions dead.
571 addPass(&OptimizePHIsID, false);
573 // This pass merges large allocas. StackSlotColoring is a different pass
574 // which merges spill slots.
575 addPass(&StackColoringID, false);
577 // If the target requests it, assign local variables to stack slots relative
578 // to one another and simplify frame index references where possible.
579 addPass(&LocalStackSlotAllocationID, false);
581 // With optimization, dead code should already be eliminated. However
582 // there is one known exception: lowered code for arguments that are only
583 // used by tail calls, where the tail calls reuse the incoming stack
584 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
585 addPass(&DeadMachineInstructionElimID);
587 // Allow targets to insert passes that improve instruction level parallelism,
588 // like if-conversion. Such passes will typically need dominator trees and
589 // loop info, just like LICM and CSE below.
592 addPass(&MachineLICMID, false);
593 addPass(&MachineCSEID, false);
594 addPass(&MachineSinkingID);
596 addPass(&PeepholeOptimizerID, false);
597 // Clean-up the dead code that may have been generated by peephole
599 addPass(&DeadMachineInstructionElimID);
602 //===---------------------------------------------------------------------===//
603 /// Register Allocation Pass Configuration
604 //===---------------------------------------------------------------------===//
606 bool TargetPassConfig::getOptimizeRegAlloc() const {
607 switch (OptimizeRegAlloc) {
608 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
609 case cl::BOU_TRUE: return true;
610 case cl::BOU_FALSE: return false;
612 llvm_unreachable("Invalid optimize-regalloc state");
615 /// RegisterRegAlloc's global Registry tracks allocator registration.
616 MachinePassRegistry RegisterRegAlloc::Registry;
618 /// A dummy default pass factory indicates whether the register allocator is
619 /// overridden on the command line.
620 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
621 static RegisterRegAlloc
622 defaultRegAlloc("default",
623 "pick register allocator based on -O option",
624 useDefaultRegisterAllocator);
626 /// -regalloc=... command line option.
627 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
628 RegisterPassParser<RegisterRegAlloc> >
630 cl::init(&useDefaultRegisterAllocator),
631 cl::desc("Register allocator to use"));
634 /// Instantiate the default register allocator pass for this target for either
635 /// the optimized or unoptimized allocation path. This will be added to the pass
636 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
637 /// in the optimized case.
639 /// A target that uses the standard regalloc pass order for fast or optimized
640 /// allocation may still override this for per-target regalloc
641 /// selection. But -regalloc=... always takes precedence.
642 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
644 return createGreedyRegisterAllocator();
646 return createFastRegisterAllocator();
649 /// Find and instantiate the register allocation pass requested by this target
650 /// at the current optimization level. Different register allocators are
651 /// defined as separate passes because they may require different analysis.
653 /// This helper ensures that the regalloc= option is always available,
654 /// even for targets that override the default allocator.
656 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
657 /// this can be folded into addPass.
658 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
659 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
661 // Initialize the global default.
664 RegisterRegAlloc::setDefault(RegAlloc);
666 if (Ctor != useDefaultRegisterAllocator)
669 // With no -regalloc= override, ask the target for a regalloc pass.
670 return createTargetRegisterAllocator(Optimized);
673 /// Return true if the default global register allocator is in use and
674 /// has not be overriden on the command line with '-regalloc=...'
675 bool TargetPassConfig::usingDefaultRegAlloc() const {
676 return RegAlloc.getNumOccurrences() == 0;
679 /// Add the minimum set of target-independent passes that are required for
680 /// register allocation. No coalescing or scheduling.
681 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
682 addPass(&PHIEliminationID, false);
683 addPass(&TwoAddressInstructionPassID, false);
685 addPass(RegAllocPass);
688 /// Add standard target-independent passes that are tightly coupled with
689 /// optimized register allocation, including coalescing, machine instruction
690 /// scheduling, and register allocation itself.
691 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
692 addPass(&ProcessImplicitDefsID, false);
694 // LiveVariables currently requires pure SSA form.
696 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
697 // LiveVariables can be removed completely, and LiveIntervals can be directly
698 // computed. (We still either need to regenerate kill flags after regalloc, or
699 // preferably fix the scavenger to not depend on them).
700 addPass(&LiveVariablesID, false);
702 // Edge splitting is smarter with machine loop info.
703 addPass(&MachineLoopInfoID, false);
704 addPass(&PHIEliminationID, false);
706 // Eventually, we want to run LiveIntervals before PHI elimination.
707 if (EarlyLiveIntervals)
708 addPass(&LiveIntervalsID, false);
710 addPass(&TwoAddressInstructionPassID, false);
711 addPass(&RegisterCoalescerID);
713 // PreRA instruction scheduling.
714 addPass(&MachineSchedulerID);
716 // Add the selected register allocation pass.
717 addPass(RegAllocPass);
719 // Allow targets to change the register assignments before rewriting.
722 // Finally rewrite virtual registers.
723 addPass(&VirtRegRewriterID);
725 // Perform stack slot coloring and post-ra machine LICM.
727 // FIXME: Re-enable coloring with register when it's capable of adding
729 addPass(&StackSlotColoringID);
731 // Run post-ra machine LICM to hoist reloads / remats.
733 // FIXME: can this move into MachineLateOptimization?
734 addPass(&PostRAMachineLICMID);
737 //===---------------------------------------------------------------------===//
738 /// Post RegAlloc Pass Configuration
739 //===---------------------------------------------------------------------===//
741 /// Add passes that optimize machine instructions after register allocation.
742 void TargetPassConfig::addMachineLateOptimization() {
743 // Branch folding must be run after regalloc and prolog/epilog insertion.
744 addPass(&BranchFolderPassID);
747 // Note that duplicating tail just increases code size and degrades
748 // performance for targets that require Structured Control Flow.
749 // In addition it can also make CFG irreducible. Thus we disable it.
750 if (!TM->requiresStructuredCFG())
751 addPass(&TailDuplicateID);
754 addPass(&MachineCopyPropagationID);
757 /// Add standard GC passes.
758 bool TargetPassConfig::addGCPasses() {
759 addPass(&GCMachineCodeAnalysisID, false);
763 /// Add standard basic block placement passes.
764 void TargetPassConfig::addBlockPlacement() {
765 if (addPass(&MachineBlockPlacementID, false)) {
766 // Run a separate pass to collect block placement statistics.
767 if (EnableBlockPlacementStats)
768 addPass(&MachineBlockPlacementStatsID);