1 //===-- Passes.cpp - Target independent code generation passes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
13 //===---------------------------------------------------------------------===//
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Analysis/Passes.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/RegAllocRegistry.h"
19 #include "llvm/IR/IRPrintingPasses.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/IR/Verifier.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Transforms/Scalar.h"
28 #include "llvm/Transforms/Utils/SymbolRewriter.h"
32 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
33 cl::desc("Disable Post Regalloc"));
34 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
35 cl::desc("Disable branch folding"));
36 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
37 cl::desc("Disable tail duplication"));
38 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
39 cl::desc("Disable pre-register allocation tail duplication"));
40 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
41 cl::Hidden, cl::desc("Disable probability-driven block placement"));
42 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
43 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
44 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
45 cl::desc("Disable Stack Slot Coloring"));
46 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
47 cl::desc("Disable Machine Dead Code Elimination"));
48 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
49 cl::desc("Disable Early If-conversion"));
50 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
51 cl::desc("Disable Machine LICM"));
52 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
53 cl::desc("Disable Machine Common Subexpression Elimination"));
54 static cl::opt<cl::boolOrDefault>
55 EnableShrinkWrapOpt("enable-shrink-wrap", cl::Hidden,
56 cl::desc("enable the shrink-wrapping pass"));
57 static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
58 "optimize-regalloc", cl::Hidden,
59 cl::desc("Enable optimized register allocation compilation path."));
60 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
62 cl::desc("Disable Machine LICM"));
63 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
64 cl::desc("Disable Machine Sinking"));
65 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
66 cl::desc("Disable Loop Strength Reduction Pass"));
67 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
68 cl::Hidden, cl::desc("Disable ConstantHoisting"));
69 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
70 cl::desc("Disable Codegen Prepare"));
71 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
72 cl::desc("Disable Copy Propagation pass"));
73 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
74 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
75 static cl::opt<bool> EnableImplicitNullChecks(
76 "enable-implicit-null-checks",
77 cl::desc("Fold null checks into faulting memory operations"),
79 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
80 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
81 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
82 cl::desc("Print LLVM IR input to isel pass"));
83 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
84 cl::desc("Dump garbage collector data"));
85 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
86 cl::desc("Verify generated machine code"),
90 static cl::opt<std::string>
91 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
92 cl::desc("Print machine instrs"),
93 cl::value_desc("pass-name"), cl::init("option-unspecified"));
95 // Temporary option to allow experimenting with MachineScheduler as a post-RA
96 // scheduler. Targets can "properly" enable this with
97 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); Ideally it
98 // wouldn't be part of the standard pass pipeline, and the target would just add
99 // a PostRA scheduling pass wherever it wants.
100 static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
101 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
103 // Experimental option to run live interval analysis early.
104 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
105 cl::desc("Run live interval analysis earlier in the pipeline"));
107 static cl::opt<bool> UseCFLAA("use-cfl-aa-in-codegen",
108 cl::init(false), cl::Hidden,
109 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"));
111 /// Allow standard passes to be disabled by command line options. This supports
112 /// simple binary flags that either suppress the pass or do nothing.
113 /// i.e. -disable-mypass=false has no effect.
114 /// These should be converted to boolOrDefault in order to use applyOverride.
115 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
118 return IdentifyingPassPtr();
122 /// Allow standard passes to be disabled by the command line, regardless of who
123 /// is adding the pass.
125 /// StandardID is the pass identified in the standard pass pipeline and provided
126 /// to addPass(). It may be a target-specific ID in the case that the target
127 /// directly adds its own pass, but in that case we harmlessly fall through.
129 /// TargetID is the pass that the target has configured to override StandardID.
131 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
132 /// pass to run. This allows multiple options to control a single pass depending
133 /// on where in the pipeline that pass is added.
134 static IdentifyingPassPtr overridePass(AnalysisID StandardID,
135 IdentifyingPassPtr TargetID) {
136 if (StandardID == &PostRASchedulerID)
137 return applyDisable(TargetID, DisablePostRA);
139 if (StandardID == &BranchFolderPassID)
140 return applyDisable(TargetID, DisableBranchFold);
142 if (StandardID == &TailDuplicateID)
143 return applyDisable(TargetID, DisableTailDuplicate);
145 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
146 return applyDisable(TargetID, DisableEarlyTailDup);
148 if (StandardID == &MachineBlockPlacementID)
149 return applyDisable(TargetID, DisableBlockPlacement);
151 if (StandardID == &StackSlotColoringID)
152 return applyDisable(TargetID, DisableSSC);
154 if (StandardID == &DeadMachineInstructionElimID)
155 return applyDisable(TargetID, DisableMachineDCE);
157 if (StandardID == &EarlyIfConverterID)
158 return applyDisable(TargetID, DisableEarlyIfConversion);
160 if (StandardID == &MachineLICMID)
161 return applyDisable(TargetID, DisableMachineLICM);
163 if (StandardID == &MachineCSEID)
164 return applyDisable(TargetID, DisableMachineCSE);
166 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
167 return applyDisable(TargetID, DisablePostRAMachineLICM);
169 if (StandardID == &MachineSinkingID)
170 return applyDisable(TargetID, DisableMachineSink);
172 if (StandardID == &MachineCopyPropagationID)
173 return applyDisable(TargetID, DisableCopyProp);
178 //===---------------------------------------------------------------------===//
180 //===---------------------------------------------------------------------===//
182 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
183 "Target Pass Configuration", false, false)
184 char TargetPassConfig::ID = 0;
187 char TargetPassConfig::EarlyTailDuplicateID = 0;
188 char TargetPassConfig::PostRAMachineLICMID = 0;
191 class PassConfigImpl {
193 // List of passes explicitly substituted by this target. Normally this is
194 // empty, but it is a convenient way to suppress or replace specific passes
195 // that are part of a standard pass pipeline without overridding the entire
196 // pipeline. This mechanism allows target options to inherit a standard pass's
197 // user interface. For example, a target may disable a standard pass by
198 // default by substituting a pass ID of zero, and the user may still enable
199 // that standard pass with an explicit command line option.
200 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
202 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
203 /// is inserted after each instance of the first one.
204 SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses;
208 // Out of line virtual method.
209 TargetPassConfig::~TargetPassConfig() {
213 // Out of line constructor provides default values for pass options and
214 // registers all common codegen passes.
215 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
216 : ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr),
217 Started(true), Stopped(false), AddingMachinePasses(false), TM(tm),
218 Impl(nullptr), Initialized(false), DisableVerify(false),
219 EnableTailMerge(true), EnableShrinkWrap(false) {
221 Impl = new PassConfigImpl();
223 // Register all target independent codegen passes to activate their PassIDs,
224 // including this pass itself.
225 initializeCodeGen(*PassRegistry::getPassRegistry());
227 // Substitute Pseudo Pass IDs for real ones.
228 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
229 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
232 /// Insert InsertedPassID pass after TargetPassID.
233 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
234 IdentifyingPassPtr InsertedPassID) {
235 assert(((!InsertedPassID.isInstance() &&
236 TargetPassID != InsertedPassID.getID()) ||
237 (InsertedPassID.isInstance() &&
238 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
239 "Insert a pass after itself!");
240 std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID);
241 Impl->InsertedPasses.push_back(P);
244 /// createPassConfig - Create a pass configuration object to be used by
245 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
247 /// Targets may override this to extend TargetPassConfig.
248 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
249 return new TargetPassConfig(this, PM);
252 TargetPassConfig::TargetPassConfig()
253 : ImmutablePass(ID), PM(nullptr) {
254 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
257 // Helper to verify the analysis is really immutable.
258 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
259 assert(!Initialized && "PassConfig is immutable");
263 void TargetPassConfig::substitutePass(AnalysisID StandardID,
264 IdentifyingPassPtr TargetID) {
265 Impl->TargetPasses[StandardID] = TargetID;
268 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
269 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
270 I = Impl->TargetPasses.find(ID);
271 if (I == Impl->TargetPasses.end())
276 /// Add a pass to the PassManager if that pass is supposed to be run. If the
277 /// Started/Stopped flags indicate either that the compilation should start at
278 /// a later pass or that it should stop after an earlier pass, then do not add
279 /// the pass. Finally, compare the current pass against the StartAfter
280 /// and StopAfter options and change the Started/Stopped flags accordingly.
281 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
282 assert(!Initialized && "PassConfig is immutable");
284 // Cache the Pass ID here in case the pass manager finds this pass is
285 // redundant with ones already scheduled / available, and deletes it.
286 // Fundamentally, once we add the pass to the manager, we no longer own it
287 // and shouldn't reference it.
288 AnalysisID PassID = P->getPassID();
290 if (Started && !Stopped) {
292 // Construct banner message before PM->add() as that may delete the pass.
293 if (AddingMachinePasses && (printAfter || verifyAfter))
294 Banner = std::string("After ") + std::string(P->getPassName());
296 if (AddingMachinePasses) {
298 addPrintPass(Banner);
300 addVerifyPass(Banner);
303 // Add the passes after the pass P if there is any.
304 for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
305 I = Impl->InsertedPasses.begin(),
306 E = Impl->InsertedPasses.end();
308 if ((*I).first == PassID) {
309 assert((*I).second.isValid() && "Illegal Pass ID!");
311 if ((*I).second.isInstance())
312 NP = (*I).second.getInstance();
314 NP = Pass::createPass((*I).second.getID());
315 assert(NP && "Pass ID not registered");
317 addPass(NP, false, false);
323 if (StopAfter == PassID)
325 if (StartAfter == PassID)
327 if (Stopped && !Started)
328 report_fatal_error("Cannot stop compilation after pass that is not run");
331 /// Add a CodeGen pass at this point in the pipeline after checking for target
332 /// and command line overrides.
334 /// addPass cannot return a pointer to the pass instance because is internal the
335 /// PassManager and the instance we create here may already be freed.
336 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
338 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
339 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
340 if (!FinalPtr.isValid())
344 if (FinalPtr.isInstance())
345 P = FinalPtr.getInstance();
347 P = Pass::createPass(FinalPtr.getID());
349 llvm_unreachable("Pass ID not registered");
351 AnalysisID FinalID = P->getPassID();
352 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
357 void TargetPassConfig::printAndVerify(const std::string &Banner) {
358 addPrintPass(Banner);
359 addVerifyPass(Banner);
362 void TargetPassConfig::addPrintPass(const std::string &Banner) {
363 if (TM->shouldPrintMachineCode())
364 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
367 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
368 if (VerifyMachineCode)
369 PM->add(createMachineVerifierPass(Banner));
372 /// Add common target configurable passes that perform LLVM IR to IR transforms
373 /// following machine independent optimization.
374 void TargetPassConfig::addIRPasses() {
375 // Basic AliasAnalysis support.
376 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
377 // BasicAliasAnalysis wins if they disagree. This is intended to help
378 // support "obvious" type-punning idioms.
380 addPass(createCFLAliasAnalysisPass());
381 addPass(createTypeBasedAliasAnalysisPass());
382 addPass(createScopedNoAliasAAPass());
383 addPass(createBasicAliasAnalysisPass());
385 // Before running any passes, run the verifier to determine if the input
386 // coming from the front-end and/or optimizer is valid.
388 addPass(createVerifierPass());
390 // Run loop strength reduction before anything else.
391 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
392 addPass(createLoopStrengthReducePass());
394 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
397 // Run GC lowering passes for builtin collectors
398 // TODO: add a pass insertion point here
399 addPass(createGCLoweringPass());
400 addPass(createShadowStackGCLoweringPass());
402 // Make sure that no unreachable blocks are instruction selected.
403 addPass(createUnreachableBlockEliminationPass());
405 // Prepare expensive constants for SelectionDAG.
406 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
407 addPass(createConstantHoistingPass());
409 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
410 addPass(createPartiallyInlineLibCallsPass());
413 /// Turn exception handling constructs into something the code generators can
415 void TargetPassConfig::addPassesToHandleExceptions() {
416 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
417 case ExceptionHandling::SjLj:
418 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
419 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
420 // catch info can get misplaced when a selector ends up more than one block
421 // removed from the parent invoke(s). This could happen when a landing
422 // pad is shared by multiple invokes and is also a target of a normal
423 // edge from elsewhere.
424 addPass(createSjLjEHPreparePass(TM));
426 case ExceptionHandling::DwarfCFI:
427 case ExceptionHandling::ARM:
428 addPass(createDwarfEHPass(TM));
430 case ExceptionHandling::WinEH:
431 // We support using both GCC-style and MSVC-style exceptions on Windows, so
432 // add both preparation passes. Each pass will only actually run if it
433 // recognizes the personality function.
434 addPass(createWinEHPass(TM));
435 addPass(createDwarfEHPass(TM));
437 case ExceptionHandling::None:
438 addPass(createLowerInvokePass());
440 // The lower invoke pass may create unreachable code. Remove it.
441 addPass(createUnreachableBlockEliminationPass());
446 /// Add pass to prepare the LLVM IR for code generation. This should be done
447 /// before exception handling preparation passes.
448 void TargetPassConfig::addCodeGenPrepare() {
449 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
450 addPass(createCodeGenPreparePass(TM));
451 addPass(createRewriteSymbolsPass());
454 /// Add common passes that perform LLVM IR to IR transforms in preparation for
455 /// instruction selection.
456 void TargetPassConfig::addISelPrepare() {
459 addPass(createStackProtectorPass(TM));
462 addPass(createPrintFunctionPass(
463 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
465 // All passes which modify the LLVM IR are now complete; run the verifier
466 // to ensure that the IR is valid.
468 addPass(createVerifierPass());
471 /// Add the complete set of target-independent postISel code generator passes.
473 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
474 /// with nontrivial configuration or multiple passes are broken out below in
475 /// add%Stage routines.
477 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
478 /// addPre/Post methods with empty header implementations allow injecting
479 /// target-specific fixups just before or after major stages. Additionally,
480 /// targets have the flexibility to change pass order within a stage by
481 /// overriding default implementation of add%Stage routines below. Each
482 /// technique has maintainability tradeoffs because alternate pass orders are
483 /// not well supported. addPre/Post works better if the target pass is easily
484 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
485 /// the target should override the stage instead.
487 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
488 /// before/after any target-independent pass. But it's currently overkill.
489 void TargetPassConfig::addMachinePasses() {
490 AddingMachinePasses = true;
492 // Insert a machine instr printer pass after the specified pass.
493 // If -print-machineinstrs specified, print machineinstrs after all passes.
494 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
495 TM->Options.PrintMachineCode = true;
496 else if (!StringRef(PrintMachineInstrs.getValue())
497 .equals("option-unspecified")) {
498 const PassRegistry *PR = PassRegistry::getPassRegistry();
499 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
500 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
501 assert (TPI && IPI && "Pass ID not registered!");
502 const char *TID = (const char *)(TPI->getTypeInfo());
503 const char *IID = (const char *)(IPI->getTypeInfo());
504 insertPass(TID, IID);
507 // Print the instruction selected machine code...
508 printAndVerify("After Instruction Selection");
510 // Expand pseudo-instructions emitted by ISel.
511 addPass(&ExpandISelPseudosID);
513 // Add passes that optimize machine instructions in SSA form.
514 if (getOptLevel() != CodeGenOpt::None) {
515 addMachineSSAOptimization();
517 // If the target requests it, assign local variables to stack slots relative
518 // to one another and simplify frame index references where possible.
519 addPass(&LocalStackSlotAllocationID, false);
522 // Run pre-ra passes.
525 // Run register allocation and passes that are tightly coupled with it,
526 // including phi elimination and scheduling.
527 if (getOptimizeRegAlloc())
528 addOptimizedRegAlloc(createRegAllocPass(true));
530 addFastRegAlloc(createRegAllocPass(false));
532 // Run post-ra passes.
535 // Insert prolog/epilog code. Eliminate abstract frame index references...
536 if (getEnableShrinkWrap())
537 addPass(&ShrinkWrapID);
538 addPass(&PrologEpilogCodeInserterID);
540 /// Add passes that optimize machine instructions after register allocation.
541 if (getOptLevel() != CodeGenOpt::None)
542 addMachineLateOptimization();
544 // Expand pseudo instructions before second scheduling pass.
545 addPass(&ExpandPostRAPseudosID);
547 // Run pre-sched2 passes.
550 if (EnableImplicitNullChecks)
551 addPass(&ImplicitNullChecksID);
553 // Second pass scheduler.
554 if (getOptLevel() != CodeGenOpt::None) {
556 addPass(&PostMachineSchedulerID);
558 addPass(&PostRASchedulerID);
564 addPass(createGCInfoPrinter(dbgs()), false, false);
567 // Basic block placement.
568 if (getOptLevel() != CodeGenOpt::None)
573 addPass(&StackMapLivenessID, false);
575 AddingMachinePasses = false;
578 /// Add passes that optimize machine instructions in SSA form.
579 void TargetPassConfig::addMachineSSAOptimization() {
580 // Pre-ra tail duplication.
581 addPass(&EarlyTailDuplicateID);
583 // Optimize PHIs before DCE: removing dead PHI cycles may make more
584 // instructions dead.
585 addPass(&OptimizePHIsID, false);
587 // This pass merges large allocas. StackSlotColoring is a different pass
588 // which merges spill slots.
589 addPass(&StackColoringID, false);
591 // If the target requests it, assign local variables to stack slots relative
592 // to one another and simplify frame index references where possible.
593 addPass(&LocalStackSlotAllocationID, false);
595 // With optimization, dead code should already be eliminated. However
596 // there is one known exception: lowered code for arguments that are only
597 // used by tail calls, where the tail calls reuse the incoming stack
598 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
599 addPass(&DeadMachineInstructionElimID);
601 // Allow targets to insert passes that improve instruction level parallelism,
602 // like if-conversion. Such passes will typically need dominator trees and
603 // loop info, just like LICM and CSE below.
606 addPass(&MachineLICMID, false);
607 addPass(&MachineCSEID, false);
608 addPass(&MachineSinkingID);
610 addPass(&PeepholeOptimizerID, false);
611 // Clean-up the dead code that may have been generated by peephole
613 addPass(&DeadMachineInstructionElimID);
616 bool TargetPassConfig::getEnableShrinkWrap() const {
617 switch (EnableShrinkWrapOpt) {
619 return EnableShrinkWrap && getOptLevel() != CodeGenOpt::None;
620 // If EnableShrinkWrap is set, it takes precedence on whatever the
621 // target sets. The rational is that we assume we want to test
622 // something related to shrink-wrapping.
628 llvm_unreachable("Invalid shrink-wrapping state");
631 //===---------------------------------------------------------------------===//
632 /// Register Allocation Pass Configuration
633 //===---------------------------------------------------------------------===//
635 bool TargetPassConfig::getOptimizeRegAlloc() const {
636 switch (OptimizeRegAlloc) {
637 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
638 case cl::BOU_TRUE: return true;
639 case cl::BOU_FALSE: return false;
641 llvm_unreachable("Invalid optimize-regalloc state");
644 /// RegisterRegAlloc's global Registry tracks allocator registration.
645 MachinePassRegistry RegisterRegAlloc::Registry;
647 /// A dummy default pass factory indicates whether the register allocator is
648 /// overridden on the command line.
649 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
650 static RegisterRegAlloc
651 defaultRegAlloc("default",
652 "pick register allocator based on -O option",
653 useDefaultRegisterAllocator);
655 /// -regalloc=... command line option.
656 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
657 RegisterPassParser<RegisterRegAlloc> >
659 cl::init(&useDefaultRegisterAllocator),
660 cl::desc("Register allocator to use"));
663 /// Instantiate the default register allocator pass for this target for either
664 /// the optimized or unoptimized allocation path. This will be added to the pass
665 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
666 /// in the optimized case.
668 /// A target that uses the standard regalloc pass order for fast or optimized
669 /// allocation may still override this for per-target regalloc
670 /// selection. But -regalloc=... always takes precedence.
671 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
673 return createGreedyRegisterAllocator();
675 return createFastRegisterAllocator();
678 /// Find and instantiate the register allocation pass requested by this target
679 /// at the current optimization level. Different register allocators are
680 /// defined as separate passes because they may require different analysis.
682 /// This helper ensures that the regalloc= option is always available,
683 /// even for targets that override the default allocator.
685 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
686 /// this can be folded into addPass.
687 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
688 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
690 // Initialize the global default.
693 RegisterRegAlloc::setDefault(RegAlloc);
695 if (Ctor != useDefaultRegisterAllocator)
698 // With no -regalloc= override, ask the target for a regalloc pass.
699 return createTargetRegisterAllocator(Optimized);
702 /// Return true if the default global register allocator is in use and
703 /// has not be overriden on the command line with '-regalloc=...'
704 bool TargetPassConfig::usingDefaultRegAlloc() const {
705 return RegAlloc.getNumOccurrences() == 0;
708 /// Add the minimum set of target-independent passes that are required for
709 /// register allocation. No coalescing or scheduling.
710 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
711 addPass(&PHIEliminationID, false);
712 addPass(&TwoAddressInstructionPassID, false);
714 addPass(RegAllocPass);
717 /// Add standard target-independent passes that are tightly coupled with
718 /// optimized register allocation, including coalescing, machine instruction
719 /// scheduling, and register allocation itself.
720 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
721 addPass(&ProcessImplicitDefsID, false);
723 // LiveVariables currently requires pure SSA form.
725 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
726 // LiveVariables can be removed completely, and LiveIntervals can be directly
727 // computed. (We still either need to regenerate kill flags after regalloc, or
728 // preferably fix the scavenger to not depend on them).
729 addPass(&LiveVariablesID, false);
731 // Edge splitting is smarter with machine loop info.
732 addPass(&MachineLoopInfoID, false);
733 addPass(&PHIEliminationID, false);
735 // Eventually, we want to run LiveIntervals before PHI elimination.
736 if (EarlyLiveIntervals)
737 addPass(&LiveIntervalsID, false);
739 addPass(&TwoAddressInstructionPassID, false);
740 addPass(&RegisterCoalescerID);
742 // PreRA instruction scheduling.
743 addPass(&MachineSchedulerID);
745 // Add the selected register allocation pass.
746 addPass(RegAllocPass);
748 // Allow targets to change the register assignments before rewriting.
751 // Finally rewrite virtual registers.
752 addPass(&VirtRegRewriterID);
754 // Perform stack slot coloring and post-ra machine LICM.
756 // FIXME: Re-enable coloring with register when it's capable of adding
758 addPass(&StackSlotColoringID);
760 // Run post-ra machine LICM to hoist reloads / remats.
762 // FIXME: can this move into MachineLateOptimization?
763 addPass(&PostRAMachineLICMID);
766 //===---------------------------------------------------------------------===//
767 /// Post RegAlloc Pass Configuration
768 //===---------------------------------------------------------------------===//
770 /// Add passes that optimize machine instructions after register allocation.
771 void TargetPassConfig::addMachineLateOptimization() {
772 // Branch folding must be run after regalloc and prolog/epilog insertion.
773 addPass(&BranchFolderPassID);
776 // Note that duplicating tail just increases code size and degrades
777 // performance for targets that require Structured Control Flow.
778 // In addition it can also make CFG irreducible. Thus we disable it.
779 if (!TM->requiresStructuredCFG())
780 addPass(&TailDuplicateID);
783 addPass(&MachineCopyPropagationID);
786 /// Add standard GC passes.
787 bool TargetPassConfig::addGCPasses() {
788 addPass(&GCMachineCodeAnalysisID, false);
792 /// Add standard basic block placement passes.
793 void TargetPassConfig::addBlockPlacement() {
794 if (addPass(&MachineBlockPlacementID, false)) {
795 // Run a separate pass to collect block placement statistics.
796 if (EnableBlockPlacementStats)
797 addPass(&MachineBlockPlacementStatsID);