1 //===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Perform peephole optimizations on the machine code:
12 // - Optimize Extensions
14 // Optimization of sign / zero extension instructions. It may be extended to
15 // handle other instructions with similar properties.
17 // On some targets, some instructions, e.g. X86 sign / zero extension, may
18 // leave the source value in the lower part of the result. This optimization
19 // will replace some uses of the pre-extension value with uses of the
20 // sub-register of the results.
22 // - Optimize Comparisons
24 // Optimization of comparison instructions. For instance, in this code:
30 // If the "sub" instruction all ready sets (or could be modified to set) the
31 // same flag that the "cmp" instruction sets and that "bz" uses, then we can
32 // eliminate the "cmp" instruction.
34 // Another instance, in this code:
36 // sub r1, r3 | sub r1, imm
37 // cmp r3, r1 or cmp r1, r3 | cmp r1, imm
40 // If the branch instruction can use flag from "sub", then we can replace
41 // "sub" with "subs" and eliminate the "cmp" instruction.
45 // Loads that can be folded into a later instruction. A load is foldable
46 // if it loads to virtual registers and the virtual register defined has
49 // - Optimize Copies and Bitcast (more generally, target specific copies):
51 // Rewrite copies and bitcasts to avoid cross register bank copies
53 // E.g., Consider the following example, where capital and lower
54 // letters denote different register file:
55 // b = copy A <-- cross-bank copy
56 // C = copy b <-- cross-bank copy
58 // b = copy A <-- cross-bank copy
59 // C = copy A <-- same-bank copy
62 // b = bitcast A <-- cross-bank copy
63 // C = bitcast b <-- cross-bank copy
65 // b = bitcast A <-- cross-bank copy
66 // C = copy A <-- same-bank copy
67 //===----------------------------------------------------------------------===//
69 #include "llvm/CodeGen/Passes.h"
70 #include "llvm/ADT/DenseMap.h"
71 #include "llvm/ADT/SmallPtrSet.h"
72 #include "llvm/ADT/SmallSet.h"
73 #include "llvm/ADT/Statistic.h"
74 #include "llvm/CodeGen/MachineDominators.h"
75 #include "llvm/CodeGen/MachineInstrBuilder.h"
76 #include "llvm/CodeGen/MachineRegisterInfo.h"
77 #include "llvm/Support/CommandLine.h"
78 #include "llvm/Support/Debug.h"
79 #include "llvm/Support/raw_ostream.h"
80 #include "llvm/Target/TargetInstrInfo.h"
81 #include "llvm/Target/TargetRegisterInfo.h"
82 #include "llvm/Target/TargetSubtargetInfo.h"
86 #define DEBUG_TYPE "peephole-opt"
88 // Optimize Extensions
90 Aggressive("aggressive-ext-opt", cl::Hidden,
91 cl::desc("Aggressive extension optimization"));
94 DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
95 cl::desc("Disable the peephole optimizer"));
98 DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false),
99 cl::desc("Disable advanced copy optimization"));
101 static cl::opt<bool> DisableNAPhysCopyOpt(
102 "disable-non-allocatable-phys-copy-opt", cl::Hidden, cl::init(false),
103 cl::desc("Disable non-allocatable physical register copy optimization"));
105 // Limit the number of PHI instructions to process
106 // in PeepholeOptimizer::getNextSource.
107 static cl::opt<unsigned> RewritePHILimit(
108 "rewrite-phi-limit", cl::Hidden, cl::init(10),
109 cl::desc("Limit the length of PHI chains to lookup"));
111 STATISTIC(NumReuse, "Number of extension results reused");
112 STATISTIC(NumCmps, "Number of compares eliminated");
113 STATISTIC(NumImmFold, "Number of move immediate folded");
114 STATISTIC(NumLoadFold, "Number of loads folded");
115 STATISTIC(NumSelects, "Number of selects optimized");
116 STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized");
117 STATISTIC(NumRewrittenCopies, "Number of copies rewritten");
118 STATISTIC(NumNAPhysCopies, "Number of non-allocatable physical copies removed");
121 class ValueTrackerResult;
123 class PeepholeOptimizer : public MachineFunctionPass {
124 const TargetInstrInfo *TII;
125 const TargetRegisterInfo *TRI;
126 MachineRegisterInfo *MRI;
127 MachineDominatorTree *DT; // Machine dominator tree
130 static char ID; // Pass identification
131 PeepholeOptimizer() : MachineFunctionPass(ID) {
132 initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
135 bool runOnMachineFunction(MachineFunction &MF) override;
137 void getAnalysisUsage(AnalysisUsage &AU) const override {
138 AU.setPreservesCFG();
139 MachineFunctionPass::getAnalysisUsage(AU);
141 AU.addRequired<MachineDominatorTree>();
142 AU.addPreserved<MachineDominatorTree>();
146 /// \brief Track Def -> Use info used for rewriting copies.
147 typedef SmallDenseMap<TargetInstrInfo::RegSubRegPair, ValueTrackerResult>
151 bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
152 bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
153 SmallPtrSetImpl<MachineInstr*> &LocalMIs);
154 bool optimizeSelect(MachineInstr *MI,
155 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
156 bool optimizeCondBranch(MachineInstr *MI);
157 bool optimizeCoalescableCopy(MachineInstr *MI);
158 bool optimizeUncoalescableCopy(MachineInstr *MI,
159 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
160 bool findNextSource(unsigned Reg, unsigned SubReg,
161 RewriteMapTy &RewriteMap);
162 bool isMoveImmediate(MachineInstr *MI,
163 SmallSet<unsigned, 4> &ImmDefRegs,
164 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
165 bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
166 SmallSet<unsigned, 4> &ImmDefRegs,
167 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
169 /// \brief If copy instruction \p MI is a virtual register copy, track it in
170 /// the set \p CopySrcRegs and \p CopyMIs. If this virtual register was
171 /// previously seen as a copy, replace the uses of this copy with the
172 /// previously seen copy's destination register.
173 bool foldRedundantCopy(MachineInstr *MI,
174 SmallSet<unsigned, 4> &CopySrcRegs,
175 DenseMap<unsigned, MachineInstr *> &CopyMIs);
177 /// \brief Is the register \p Reg a non-allocatable physical register?
178 bool isNAPhysCopy(unsigned Reg);
180 /// \brief If copy instruction \p MI is a non-allocatable virtual<->physical
181 /// register copy, track it in the \p NAPhysToVirtMIs map. If this
182 /// non-allocatable physical register was previously copied to a virtual
183 /// registered and hasn't been clobbered, the virt->phys copy can be
185 bool foldRedundantNAPhysCopy(
187 DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs);
189 bool isLoadFoldable(MachineInstr *MI,
190 SmallSet<unsigned, 16> &FoldAsLoadDefCandidates);
192 /// \brief Check whether \p MI is understood by the register coalescer
193 /// but may require some rewriting.
194 bool isCoalescableCopy(const MachineInstr &MI) {
195 // SubregToRegs are not interesting, because they are already register
196 // coalescer friendly.
197 return MI.isCopy() || (!DisableAdvCopyOpt &&
198 (MI.isRegSequence() || MI.isInsertSubreg() ||
199 MI.isExtractSubreg()));
202 /// \brief Check whether \p MI is a copy like instruction that is
203 /// not recognized by the register coalescer.
204 bool isUncoalescableCopy(const MachineInstr &MI) {
205 return MI.isBitcast() ||
206 (!DisableAdvCopyOpt &&
207 (MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
208 MI.isExtractSubregLike()));
212 /// \brief Helper class to hold a reply for ValueTracker queries. Contains the
213 /// returned sources for a given search and the instructions where the sources
214 /// were tracked from.
215 class ValueTrackerResult {
217 /// Track all sources found by one ValueTracker query.
218 SmallVector<TargetInstrInfo::RegSubRegPair, 2> RegSrcs;
220 /// Instruction using the sources in 'RegSrcs'.
221 const MachineInstr *Inst;
224 ValueTrackerResult() : Inst(nullptr) {}
225 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) {
226 addSource(Reg, SubReg);
229 bool isValid() const { return getNumSources() > 0; }
231 void setInst(const MachineInstr *I) { Inst = I; }
232 const MachineInstr *getInst() const { return Inst; }
239 void addSource(unsigned SrcReg, unsigned SrcSubReg) {
240 RegSrcs.push_back(TargetInstrInfo::RegSubRegPair(SrcReg, SrcSubReg));
243 void setSource(int Idx, unsigned SrcReg, unsigned SrcSubReg) {
244 assert(Idx < getNumSources() && "Reg pair source out of index");
245 RegSrcs[Idx] = TargetInstrInfo::RegSubRegPair(SrcReg, SrcSubReg);
248 int getNumSources() const { return RegSrcs.size(); }
250 unsigned getSrcReg(int Idx) const {
251 assert(Idx < getNumSources() && "Reg source out of index");
252 return RegSrcs[Idx].Reg;
255 unsigned getSrcSubReg(int Idx) const {
256 assert(Idx < getNumSources() && "SubReg source out of index");
257 return RegSrcs[Idx].SubReg;
260 bool operator==(const ValueTrackerResult &Other) {
261 if (Other.getInst() != getInst())
264 if (Other.getNumSources() != getNumSources())
267 for (int i = 0, e = Other.getNumSources(); i != e; ++i)
268 if (Other.getSrcReg(i) != getSrcReg(i) ||
269 Other.getSrcSubReg(i) != getSrcSubReg(i))
275 /// \brief Helper class to track the possible sources of a value defined by
276 /// a (chain of) copy related instructions.
277 /// Given a definition (instruction and definition index), this class
278 /// follows the use-def chain to find successive suitable sources.
279 /// The given source can be used to rewrite the definition into
282 /// For instance, let us consider the following snippet:
284 /// v2 = INSERT_SUBREG v1, v0, sub0
285 /// def = COPY v2.sub0
287 /// Using a ValueTracker for def = COPY v2.sub0 will give the following
288 /// suitable sources:
290 /// Then, def can be rewritten into def = COPY v0.
293 /// The current point into the use-def chain.
294 const MachineInstr *Def;
295 /// The index of the definition in Def.
297 /// The sub register index of the definition.
299 /// The register where the value can be found.
301 /// Specifiy whether or not the value tracking looks through
302 /// complex instructions. When this is false, the value tracker
303 /// bails on everything that is not a copy or a bitcast.
305 /// Note: This could have been implemented as a specialized version of
306 /// the ValueTracker class but that would have complicated the code of
307 /// the users of this class.
308 bool UseAdvancedTracking;
309 /// MachineRegisterInfo used to perform tracking.
310 const MachineRegisterInfo &MRI;
311 /// Optional TargetInstrInfo used to perform some complex
313 const TargetInstrInfo *TII;
315 /// \brief Dispatcher to the right underlying implementation of
317 ValueTrackerResult getNextSourceImpl();
318 /// \brief Specialized version of getNextSource for Copy instructions.
319 ValueTrackerResult getNextSourceFromCopy();
320 /// \brief Specialized version of getNextSource for Bitcast instructions.
321 ValueTrackerResult getNextSourceFromBitcast();
322 /// \brief Specialized version of getNextSource for RegSequence
324 ValueTrackerResult getNextSourceFromRegSequence();
325 /// \brief Specialized version of getNextSource for InsertSubreg
327 ValueTrackerResult getNextSourceFromInsertSubreg();
328 /// \brief Specialized version of getNextSource for ExtractSubreg
330 ValueTrackerResult getNextSourceFromExtractSubreg();
331 /// \brief Specialized version of getNextSource for SubregToReg
333 ValueTrackerResult getNextSourceFromSubregToReg();
334 /// \brief Specialized version of getNextSource for PHI instructions.
335 ValueTrackerResult getNextSourceFromPHI();
338 /// \brief Create a ValueTracker instance for the value defined by \p Reg.
339 /// \p DefSubReg represents the sub register index the value tracker will
340 /// track. It does not need to match the sub register index used in the
341 /// definition of \p Reg.
342 /// \p UseAdvancedTracking specifies whether or not the value tracker looks
343 /// through complex instructions. By default (false), it handles only copy
344 /// and bitcast instructions.
345 /// If \p Reg is a physical register, a value tracker constructed with
346 /// this constructor will not find any alternative source.
347 /// Indeed, when \p Reg is a physical register that constructor does not
348 /// know which definition of \p Reg it should track.
349 /// Use the next constructor to track a physical register.
350 ValueTracker(unsigned Reg, unsigned DefSubReg,
351 const MachineRegisterInfo &MRI,
352 bool UseAdvancedTracking = false,
353 const TargetInstrInfo *TII = nullptr)
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
355 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
356 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
357 Def = MRI.getVRegDef(Reg);
358 DefIdx = MRI.def_begin(Reg).getOperandNo();
362 /// \brief Create a ValueTracker instance for the value defined by
363 /// the pair \p MI, \p DefIdx.
364 /// Unlike the other constructor, the value tracker produced by this one
365 /// may be able to find a new source when the definition is a physical
367 /// This could be useful to rewrite target specific instructions into
368 /// generic copy instructions.
369 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
370 const MachineRegisterInfo &MRI,
371 bool UseAdvancedTracking = false,
372 const TargetInstrInfo *TII = nullptr)
373 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
374 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
375 assert(DefIdx < Def->getDesc().getNumDefs() &&
376 Def->getOperand(DefIdx).isReg() && "Invalid definition");
377 Reg = Def->getOperand(DefIdx).getReg();
380 /// \brief Following the use-def chain, get the next available source
381 /// for the tracked value.
382 /// \return A ValueTrackerResult containing a set of registers
383 /// and sub registers with tracked values. A ValueTrackerResult with
384 /// an empty set of registers means no source was found.
385 ValueTrackerResult getNextSource();
387 /// \brief Get the last register where the initial value can be found.
388 /// Initially this is the register of the definition.
389 /// Then, after each successful call to getNextSource, this is the
390 /// register of the last source.
391 unsigned getReg() const { return Reg; }
395 char PeepholeOptimizer::ID = 0;
396 char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
397 INITIALIZE_PASS_BEGIN(PeepholeOptimizer, "peephole-opts",
398 "Peephole Optimizations", false, false)
399 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
400 INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts",
401 "Peephole Optimizations", false, false)
403 /// If instruction is a copy-like instruction, i.e. it reads a single register
404 /// and writes a single register and it does not modify the source, and if the
405 /// source value is preserved as a sub-register of the result, then replace all
406 /// reachable uses of the source with the subreg of the result.
408 /// Do not generate an EXTRACT that is used only in a debug use, as this changes
409 /// the code. Since this code does not currently share EXTRACTs, just ignore all
411 bool PeepholeOptimizer::
412 optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
413 SmallPtrSetImpl<MachineInstr*> &LocalMIs) {
414 unsigned SrcReg, DstReg, SubIdx;
415 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
418 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
419 TargetRegisterInfo::isPhysicalRegister(SrcReg))
422 if (MRI->hasOneNonDBGUse(SrcReg))
426 // Ensure DstReg can get a register class that actually supports
427 // sub-registers. Don't change the class until we commit.
428 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
429 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
433 // The ext instr may be operating on a sub-register of SrcReg as well.
434 // PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a 64-bit
436 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
437 // SrcReg:SubIdx should be replaced.
439 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
441 // The source has other uses. See if we can replace the other uses with use of
442 // the result of the extension.
443 SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
444 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
445 ReachedBBs.insert(UI.getParent());
447 // Uses that are in the same BB of uses of the result of the instruction.
448 SmallVector<MachineOperand*, 8> Uses;
450 // Uses that the result of the instruction can reach.
451 SmallVector<MachineOperand*, 8> ExtendedUses;
453 bool ExtendLife = true;
454 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
455 MachineInstr *UseMI = UseMO.getParent();
459 if (UseMI->isPHI()) {
464 // Only accept uses of SrcReg:SubIdx.
465 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
468 // It's an error to translate this:
470 // %reg1025 = <sext> %reg1024
472 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
476 // %reg1025 = <sext> %reg1024
478 // %reg1027 = COPY %reg1025:4
479 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
481 // The problem here is that SUBREG_TO_REG is there to assert that an
482 // implicit zext occurs. It doesn't insert a zext instruction. If we allow
483 // the COPY here, it will give us the value after the <sext>, not the
484 // original value of %reg1024 before <sext>.
485 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
488 MachineBasicBlock *UseMBB = UseMI->getParent();
490 // Local uses that come after the extension.
491 if (!LocalMIs.count(UseMI))
492 Uses.push_back(&UseMO);
493 } else if (ReachedBBs.count(UseMBB)) {
494 // Non-local uses where the result of the extension is used. Always
495 // replace these unless it's a PHI.
496 Uses.push_back(&UseMO);
497 } else if (Aggressive && DT->dominates(MBB, UseMBB)) {
498 // We may want to extend the live range of the extension result in order
499 // to replace these uses.
500 ExtendedUses.push_back(&UseMO);
502 // Both will be live out of the def MBB anyway. Don't extend live range of
503 // the extension result.
509 if (ExtendLife && !ExtendedUses.empty())
510 // Extend the liveness of the extension result.
511 Uses.append(ExtendedUses.begin(), ExtendedUses.end());
513 // Now replace all uses.
514 bool Changed = false;
516 SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
518 // Look for PHI uses of the extended result, we don't want to extend the
519 // liveness of a PHI input. It breaks all kinds of assumptions down
520 // stream. A PHI use is expected to be the kill of its source values.
521 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
523 PHIBBs.insert(UI.getParent());
525 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
526 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
527 MachineOperand *UseMO = Uses[i];
528 MachineInstr *UseMI = UseMO->getParent();
529 MachineBasicBlock *UseMBB = UseMI->getParent();
530 if (PHIBBs.count(UseMBB))
533 // About to add uses of DstReg, clear DstReg's kill flags.
535 MRI->clearKillFlags(DstReg);
536 MRI->constrainRegClass(DstReg, DstRC);
539 unsigned NewVR = MRI->createVirtualRegister(RC);
540 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
541 TII->get(TargetOpcode::COPY), NewVR)
542 .addReg(DstReg, 0, SubIdx);
543 // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
545 Copy->getOperand(0).setSubReg(SubIdx);
546 Copy->getOperand(0).setIsUndef();
548 UseMO->setReg(NewVR);
557 /// If the instruction is a compare and the previous instruction it's comparing
558 /// against already sets (or could be modified to set) the same flag as the
559 /// compare, then we can remove the comparison and use the flag from the
560 /// previous instruction.
561 bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr *MI,
562 MachineBasicBlock *MBB) {
563 // If this instruction is a comparison against zero and isn't comparing a
564 // physical register, we can try to optimize it.
565 unsigned SrcReg, SrcReg2;
566 int CmpMask, CmpValue;
567 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
568 TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
569 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
572 // Attempt to optimize the comparison instruction.
573 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
581 /// Optimize a select instruction.
582 bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI,
583 SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
585 unsigned FalseOp = 0;
586 bool Optimizable = false;
587 SmallVector<MachineOperand, 4> Cond;
588 if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
592 if (!TII->optimizeSelect(MI, LocalMIs))
594 MI->eraseFromParent();
599 /// \brief Check if a simpler conditional branch can be
601 bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) {
602 return TII->optimizeCondBranch(MI);
605 /// \brief Try to find the next source that share the same register file
606 /// for the value defined by \p Reg and \p SubReg.
607 /// When true is returned, the \p RewriteMap can be used by the client to
608 /// retrieve all Def -> Use along the way up to the next source. Any found
609 /// Use that is not itself a key for another entry, is the next source to
610 /// use. During the search for the next source, multiple sources can be found
611 /// given multiple incoming sources of a PHI instruction. In this case, we
612 /// look in each PHI source for the next source; all found next sources must
613 /// share the same register file as \p Reg and \p SubReg. The client should
614 /// then be capable to rewrite all intermediate PHIs to get the next source.
615 /// \return False if no alternative sources are available. True otherwise.
616 bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg,
617 RewriteMapTy &RewriteMap) {
618 // Do not try to find a new source for a physical register.
619 // So far we do not have any motivating example for doing that.
620 // Thus, instead of maintaining untested code, we will revisit that if
621 // that changes at some point.
622 if (TargetRegisterInfo::isPhysicalRegister(Reg))
624 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
626 SmallVector<TargetInstrInfo::RegSubRegPair, 4> SrcToLook;
627 TargetInstrInfo::RegSubRegPair CurSrcPair(Reg, SubReg);
628 SrcToLook.push_back(CurSrcPair);
630 unsigned PHICount = 0;
631 while (!SrcToLook.empty() && PHICount < RewritePHILimit) {
632 TargetInstrInfo::RegSubRegPair Pair = SrcToLook.pop_back_val();
633 // As explained above, do not handle physical registers
634 if (TargetRegisterInfo::isPhysicalRegister(Pair.Reg))
638 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI,
639 !DisableAdvCopyOpt, TII);
640 ValueTrackerResult Res;
641 bool ShouldRewrite = false;
644 // Follow the chain of copies until we reach the top of the use-def chain
645 // or find a more suitable source.
646 Res = ValTracker.getNextSource();
650 // Insert the Def -> Use entry for the recently found source.
651 ValueTrackerResult CurSrcRes = RewriteMap.lookup(CurSrcPair);
652 if (CurSrcRes.isValid()) {
653 assert(CurSrcRes == Res && "ValueTrackerResult found must match");
654 // An existent entry with multiple sources is a PHI cycle we must avoid.
655 // Otherwise it's an entry with a valid next source we already found.
656 if (CurSrcRes.getNumSources() > 1) {
657 DEBUG(dbgs() << "findNextSource: found PHI cycle, aborting...\n");
662 RewriteMap.insert(std::make_pair(CurSrcPair, Res));
664 // ValueTrackerResult usually have one source unless it's the result from
665 // a PHI instruction. Add the found PHI edges to be looked up further.
666 unsigned NumSrcs = Res.getNumSources();
669 for (unsigned i = 0; i < NumSrcs; ++i)
670 SrcToLook.push_back(TargetInstrInfo::RegSubRegPair(
671 Res.getSrcReg(i), Res.getSrcSubReg(i)));
675 CurSrcPair.Reg = Res.getSrcReg(0);
676 CurSrcPair.SubReg = Res.getSrcSubReg(0);
677 // Do not extend the live-ranges of physical registers as they add
678 // constraints to the register allocator. Moreover, if we want to extend
679 // the live-range of a physical register, unlike SSA virtual register,
680 // we will have to check that they aren't redefine before the related use.
681 if (TargetRegisterInfo::isPhysicalRegister(CurSrcPair.Reg))
684 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
685 ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC,
687 } while (!ShouldRewrite);
689 // Continue looking for new sources...
693 // Do not continue searching for a new source if the there's at least
694 // one use-def which cannot be rewritten.
699 if (PHICount >= RewritePHILimit) {
700 DEBUG(dbgs() << "findNextSource: PHI limit reached\n");
704 // If we did not find a more suitable source, there is nothing to optimize.
705 return CurSrcPair.Reg != Reg;
708 /// \brief Insert a PHI instruction with incoming edges \p SrcRegs that are
709 /// guaranteed to have the same register class. This is necessary whenever we
710 /// successfully traverse a PHI instruction and find suitable sources coming
711 /// from its edges. By inserting a new PHI, we provide a rewritten PHI def
712 /// suitable to be used in a new COPY instruction.
713 static MachineInstr *
714 insertPHI(MachineRegisterInfo *MRI, const TargetInstrInfo *TII,
715 const SmallVectorImpl<TargetInstrInfo::RegSubRegPair> &SrcRegs,
716 MachineInstr *OrigPHI) {
717 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?");
719 const TargetRegisterClass *NewRC = MRI->getRegClass(SrcRegs[0].Reg);
720 unsigned NewVR = MRI->createVirtualRegister(NewRC);
721 MachineBasicBlock *MBB = OrigPHI->getParent();
722 MachineInstrBuilder MIB = BuildMI(*MBB, OrigPHI, OrigPHI->getDebugLoc(),
723 TII->get(TargetOpcode::PHI), NewVR);
725 unsigned MBBOpIdx = 2;
726 for (auto RegPair : SrcRegs) {
727 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg);
728 MIB.addMBB(OrigPHI->getOperand(MBBOpIdx).getMBB());
729 // Since we're extended the lifetime of RegPair.Reg, clear the
730 // kill flags to account for that and make RegPair.Reg reaches
732 MRI->clearKillFlags(RegPair.Reg);
740 /// \brief Helper class to rewrite the arguments of a copy-like instruction.
743 /// The copy-like instruction.
744 MachineInstr &CopyLike;
745 /// The index of the source being rewritten.
746 unsigned CurrentSrcIdx;
749 CopyRewriter(MachineInstr &MI) : CopyLike(MI), CurrentSrcIdx(0) {}
751 virtual ~CopyRewriter() {}
753 /// \brief Get the next rewritable source (SrcReg, SrcSubReg) and
754 /// the related value that it affects (TrackReg, TrackSubReg).
755 /// A source is considered rewritable if its register class and the
756 /// register class of the related TrackReg may not be register
757 /// coalescer friendly. In other words, given a copy-like instruction
758 /// not all the arguments may be returned at rewritable source, since
759 /// some arguments are none to be register coalescer friendly.
761 /// Each call of this method moves the current source to the next
762 /// rewritable source.
763 /// For instance, let CopyLike be the instruction to rewrite.
764 /// CopyLike has one definition and one source:
765 /// dst.dstSubIdx = CopyLike src.srcSubIdx.
767 /// The first call will give the first rewritable source, i.e.,
768 /// the only source this instruction has:
769 /// (SrcReg, SrcSubReg) = (src, srcSubIdx).
770 /// This source defines the whole definition, i.e.,
771 /// (TrackReg, TrackSubReg) = (dst, dstSubIdx).
773 /// The second and subsequent calls will return false, as there is only one
774 /// rewritable source.
776 /// \return True if a rewritable source has been found, false otherwise.
777 /// The output arguments are valid if and only if true is returned.
778 virtual bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
780 unsigned &TrackSubReg) {
781 // If CurrentSrcIdx == 1, this means this function has already been called
782 // once. CopyLike has one definition and one argument, thus, there is
783 // nothing else to rewrite.
784 if (!CopyLike.isCopy() || CurrentSrcIdx == 1)
786 // This is the first call to getNextRewritableSource.
787 // Move the CurrentSrcIdx to remember that we made that call.
789 // The rewritable source is the argument.
790 const MachineOperand &MOSrc = CopyLike.getOperand(1);
791 SrcReg = MOSrc.getReg();
792 SrcSubReg = MOSrc.getSubReg();
793 // What we track are the alternative sources of the definition.
794 const MachineOperand &MODef = CopyLike.getOperand(0);
795 TrackReg = MODef.getReg();
796 TrackSubReg = MODef.getSubReg();
800 /// \brief Rewrite the current source with \p NewReg and \p NewSubReg
802 /// \return True if the rewriting was possible, false otherwise.
803 virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) {
804 if (!CopyLike.isCopy() || CurrentSrcIdx != 1)
806 MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
807 MOSrc.setReg(NewReg);
808 MOSrc.setSubReg(NewSubReg);
812 /// \brief Given a \p Def.Reg and Def.SubReg pair, use \p RewriteMap to find
813 /// the new source to use for rewrite. If \p HandleMultipleSources is true and
814 /// multiple sources for a given \p Def are found along the way, we found a
815 /// PHI instructions that needs to be rewritten.
816 /// TODO: HandleMultipleSources should be removed once we test PHI handling
817 /// with coalescable copies.
818 TargetInstrInfo::RegSubRegPair
819 getNewSource(MachineRegisterInfo *MRI, const TargetInstrInfo *TII,
820 TargetInstrInfo::RegSubRegPair Def,
821 PeepholeOptimizer::RewriteMapTy &RewriteMap,
822 bool HandleMultipleSources = true) {
824 TargetInstrInfo::RegSubRegPair LookupSrc(Def.Reg, Def.SubReg);
826 ValueTrackerResult Res = RewriteMap.lookup(LookupSrc);
827 // If there are no entries on the map, LookupSrc is the new source.
831 // There's only one source for this definition, keep searching...
832 unsigned NumSrcs = Res.getNumSources();
834 LookupSrc.Reg = Res.getSrcReg(0);
835 LookupSrc.SubReg = Res.getSrcSubReg(0);
839 // TODO: Remove once multiple srcs w/ coalescable copies are supported.
840 if (!HandleMultipleSources)
843 // Multiple sources, recurse into each source to find a new source
844 // for it. Then, rewrite the PHI accordingly to its new edges.
845 SmallVector<TargetInstrInfo::RegSubRegPair, 4> NewPHISrcs;
846 for (unsigned i = 0; i < NumSrcs; ++i) {
847 TargetInstrInfo::RegSubRegPair PHISrc(Res.getSrcReg(i),
848 Res.getSrcSubReg(i));
849 NewPHISrcs.push_back(
850 getNewSource(MRI, TII, PHISrc, RewriteMap, HandleMultipleSources));
853 // Build the new PHI node and return its def register as the new source.
854 MachineInstr *OrigPHI = const_cast<MachineInstr *>(Res.getInst());
855 MachineInstr *NewPHI = insertPHI(MRI, TII, NewPHISrcs, OrigPHI);
856 DEBUG(dbgs() << "-- getNewSource\n");
857 DEBUG(dbgs() << " Replacing: " << *OrigPHI);
858 DEBUG(dbgs() << " With: " << *NewPHI);
859 const MachineOperand &MODef = NewPHI->getOperand(0);
860 return TargetInstrInfo::RegSubRegPair(MODef.getReg(), MODef.getSubReg());
864 return TargetInstrInfo::RegSubRegPair(0, 0);
867 /// \brief Rewrite the source found through \p Def, by using the \p RewriteMap
868 /// and create a new COPY instruction. More info about RewriteMap in
869 /// PeepholeOptimizer::findNextSource. Right now this is only used to handle
870 /// Uncoalescable copies, since they are copy like instructions that aren't
871 /// recognized by the register allocator.
872 virtual MachineInstr *
873 RewriteSource(TargetInstrInfo::RegSubRegPair Def,
874 PeepholeOptimizer::RewriteMapTy &RewriteMap) {
879 /// \brief Helper class to rewrite uncoalescable copy like instructions
880 /// into new COPY (coalescable friendly) instructions.
881 class UncoalescableRewriter : public CopyRewriter {
883 const TargetInstrInfo &TII;
884 MachineRegisterInfo &MRI;
885 /// The number of defs in the bitcast
889 UncoalescableRewriter(MachineInstr &MI, const TargetInstrInfo &TII,
890 MachineRegisterInfo &MRI)
891 : CopyRewriter(MI), TII(TII), MRI(MRI) {
892 NumDefs = MI.getDesc().getNumDefs();
895 /// \brief Get the next rewritable def source (TrackReg, TrackSubReg)
896 /// All such sources need to be considered rewritable in order to
897 /// rewrite a uncoalescable copy-like instruction. This method return
898 /// each definition that must be checked if rewritable.
900 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
902 unsigned &TrackSubReg) override {
903 // Find the next non-dead definition and continue from there.
904 if (CurrentSrcIdx == NumDefs)
907 while (CopyLike.getOperand(CurrentSrcIdx).isDead()) {
909 if (CurrentSrcIdx == NumDefs)
913 // What we track are the alternative sources of the definition.
914 const MachineOperand &MODef = CopyLike.getOperand(CurrentSrcIdx);
915 TrackReg = MODef.getReg();
916 TrackSubReg = MODef.getSubReg();
922 /// \brief Rewrite the source found through \p Def, by using the \p RewriteMap
923 /// and create a new COPY instruction. More info about RewriteMap in
924 /// PeepholeOptimizer::findNextSource. Right now this is only used to handle
925 /// Uncoalescable copies, since they are copy like instructions that aren't
926 /// recognized by the register allocator.
928 RewriteSource(TargetInstrInfo::RegSubRegPair Def,
929 PeepholeOptimizer::RewriteMapTy &RewriteMap) override {
930 assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) &&
931 "We do not rewrite physical registers");
933 // Find the new source to use in the COPY rewrite.
934 TargetInstrInfo::RegSubRegPair NewSrc =
935 getNewSource(&MRI, &TII, Def, RewriteMap);
938 const TargetRegisterClass *DefRC = MRI.getRegClass(Def.Reg);
939 unsigned NewVR = MRI.createVirtualRegister(DefRC);
941 MachineInstr *NewCopy =
942 BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
943 TII.get(TargetOpcode::COPY), NewVR)
944 .addReg(NewSrc.Reg, 0, NewSrc.SubReg);
946 NewCopy->getOperand(0).setSubReg(Def.SubReg);
948 NewCopy->getOperand(0).setIsUndef();
950 DEBUG(dbgs() << "-- RewriteSource\n");
951 DEBUG(dbgs() << " Replacing: " << CopyLike);
952 DEBUG(dbgs() << " With: " << *NewCopy);
953 MRI.replaceRegWith(Def.Reg, NewVR);
954 MRI.clearKillFlags(NewVR);
956 // We extended the lifetime of NewSrc.Reg, clear the kill flags to
958 MRI.clearKillFlags(NewSrc.Reg);
964 /// \brief Specialized rewriter for INSERT_SUBREG instruction.
965 class InsertSubregRewriter : public CopyRewriter {
967 InsertSubregRewriter(MachineInstr &MI) : CopyRewriter(MI) {
968 assert(MI.isInsertSubreg() && "Invalid instruction");
971 /// \brief See CopyRewriter::getNextRewritableSource.
972 /// Here CopyLike has the following form:
973 /// dst = INSERT_SUBREG Src1, Src2.src2SubIdx, subIdx.
974 /// Src1 has the same register class has dst, hence, there is
975 /// nothing to rewrite.
976 /// Src2.src2SubIdx, may not be register coalescer friendly.
977 /// Therefore, the first call to this method returns:
978 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
979 /// (TrackReg, TrackSubReg) = (dst, subIdx).
981 /// Subsequence calls will return false.
982 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
984 unsigned &TrackSubReg) override {
985 // If we already get the only source we can rewrite, return false.
986 if (CurrentSrcIdx == 2)
988 // We are looking at v2 = INSERT_SUBREG v0, v1, sub0.
990 const MachineOperand &MOInsertedReg = CopyLike.getOperand(2);
991 SrcReg = MOInsertedReg.getReg();
992 SrcSubReg = MOInsertedReg.getSubReg();
993 const MachineOperand &MODef = CopyLike.getOperand(0);
995 // We want to track something that is compatible with the
996 // partial definition.
997 TrackReg = MODef.getReg();
998 if (MODef.getSubReg())
999 // Bail if we have to compose sub-register indices.
1001 TrackSubReg = (unsigned)CopyLike.getOperand(3).getImm();
1004 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
1005 if (CurrentSrcIdx != 2)
1007 // We are rewriting the inserted reg.
1008 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
1010 MO.setSubReg(NewSubReg);
1015 /// \brief Specialized rewriter for EXTRACT_SUBREG instruction.
1016 class ExtractSubregRewriter : public CopyRewriter {
1017 const TargetInstrInfo &TII;
1020 ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII)
1021 : CopyRewriter(MI), TII(TII) {
1022 assert(MI.isExtractSubreg() && "Invalid instruction");
1025 /// \brief See CopyRewriter::getNextRewritableSource.
1026 /// Here CopyLike has the following form:
1027 /// dst.dstSubIdx = EXTRACT_SUBREG Src, subIdx.
1028 /// There is only one rewritable source: Src.subIdx,
1029 /// which defines dst.dstSubIdx.
1030 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
1032 unsigned &TrackSubReg) override {
1033 // If we already get the only source we can rewrite, return false.
1034 if (CurrentSrcIdx == 1)
1036 // We are looking at v1 = EXTRACT_SUBREG v0, sub0.
1038 const MachineOperand &MOExtractedReg = CopyLike.getOperand(1);
1039 SrcReg = MOExtractedReg.getReg();
1040 // If we have to compose sub-register indices, bail out.
1041 if (MOExtractedReg.getSubReg())
1044 SrcSubReg = CopyLike.getOperand(2).getImm();
1046 // We want to track something that is compatible with the definition.
1047 const MachineOperand &MODef = CopyLike.getOperand(0);
1048 TrackReg = MODef.getReg();
1049 TrackSubReg = MODef.getSubReg();
1053 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
1054 // The only source we can rewrite is the input register.
1055 if (CurrentSrcIdx != 1)
1058 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
1060 // If we find a source that does not require to extract something,
1061 // rewrite the operation with a copy.
1063 // Move the current index to an invalid position.
1064 // We do not want another call to this method to be able
1065 // to do any change.
1067 // Rewrite the operation as a COPY.
1068 // Get rid of the sub-register index.
1069 CopyLike.RemoveOperand(2);
1070 // Morph the operation into a COPY.
1071 CopyLike.setDesc(TII.get(TargetOpcode::COPY));
1074 CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);
1079 /// \brief Specialized rewriter for REG_SEQUENCE instruction.
1080 class RegSequenceRewriter : public CopyRewriter {
1082 RegSequenceRewriter(MachineInstr &MI) : CopyRewriter(MI) {
1083 assert(MI.isRegSequence() && "Invalid instruction");
1086 /// \brief See CopyRewriter::getNextRewritableSource.
1087 /// Here CopyLike has the following form:
1088 /// dst = REG_SEQUENCE Src1.src1SubIdx, subIdx1, Src2.src2SubIdx, subIdx2.
1089 /// Each call will return a different source, walking all the available
1092 /// The first call returns:
1093 /// (SrcReg, SrcSubReg) = (Src1, src1SubIdx).
1094 /// (TrackReg, TrackSubReg) = (dst, subIdx1).
1096 /// The second call returns:
1097 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
1098 /// (TrackReg, TrackSubReg) = (dst, subIdx2).
1100 /// And so on, until all the sources have been traversed, then
1101 /// it returns false.
1102 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
1104 unsigned &TrackSubReg) override {
1105 // We are looking at v0 = REG_SEQUENCE v1, sub1, v2, sub2, etc.
1107 // If this is the first call, move to the first argument.
1108 if (CurrentSrcIdx == 0) {
1111 // Otherwise, move to the next argument and check that it is valid.
1113 if (CurrentSrcIdx >= CopyLike.getNumOperands())
1116 const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
1117 SrcReg = MOInsertedReg.getReg();
1118 // If we have to compose sub-register indices, bail out.
1119 if ((SrcSubReg = MOInsertedReg.getSubReg()))
1122 // We want to track something that is compatible with the related
1123 // partial definition.
1124 TrackSubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
1126 const MachineOperand &MODef = CopyLike.getOperand(0);
1127 TrackReg = MODef.getReg();
1128 // If we have to compose sub-registers, bail.
1129 return MODef.getSubReg() == 0;
1132 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
1133 // We cannot rewrite out of bound operands.
1134 // Moreover, rewritable sources are at odd positions.
1135 if ((CurrentSrcIdx & 1) != 1 || CurrentSrcIdx > CopyLike.getNumOperands())
1138 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
1140 MO.setSubReg(NewSubReg);
1146 /// \brief Get the appropriated CopyRewriter for \p MI.
1147 /// \return A pointer to a dynamically allocated CopyRewriter or nullptr
1148 /// if no rewriter works for \p MI.
1149 static CopyRewriter *getCopyRewriter(MachineInstr &MI,
1150 const TargetInstrInfo &TII,
1151 MachineRegisterInfo &MRI) {
1152 // Handle uncoalescable copy-like instructions.
1153 if (MI.isBitcast() || (MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
1154 MI.isExtractSubregLike()))
1155 return new UncoalescableRewriter(MI, TII, MRI);
1157 switch (MI.getOpcode()) {
1160 case TargetOpcode::COPY:
1161 return new CopyRewriter(MI);
1162 case TargetOpcode::INSERT_SUBREG:
1163 return new InsertSubregRewriter(MI);
1164 case TargetOpcode::EXTRACT_SUBREG:
1165 return new ExtractSubregRewriter(MI, TII);
1166 case TargetOpcode::REG_SEQUENCE:
1167 return new RegSequenceRewriter(MI);
1169 llvm_unreachable(nullptr);
1172 /// \brief Optimize generic copy instructions to avoid cross
1173 /// register bank copy. The optimization looks through a chain of
1174 /// copies and tries to find a source that has a compatible register
1176 /// Two register classes are considered to be compatible if they share
1177 /// the same register bank.
1178 /// New copies issued by this optimization are register allocator
1179 /// friendly. This optimization does not remove any copy as it may
1180 /// overconstrain the register allocator, but replaces some operands
1182 /// \pre isCoalescableCopy(*MI) is true.
1183 /// \return True, when \p MI has been rewritten. False otherwise.
1184 bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr *MI) {
1185 assert(MI && isCoalescableCopy(*MI) && "Invalid argument");
1186 assert(MI->getDesc().getNumDefs() == 1 &&
1187 "Coalescer can understand multiple defs?!");
1188 const MachineOperand &MODef = MI->getOperand(0);
1189 // Do not rewrite physical definitions.
1190 if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
1193 bool Changed = false;
1194 // Get the right rewriter for the current copy.
1195 std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII, *MRI));
1196 // If none exists, bail out.
1199 // Rewrite each rewritable source.
1200 unsigned SrcReg, SrcSubReg, TrackReg, TrackSubReg;
1201 while (CpyRewriter->getNextRewritableSource(SrcReg, SrcSubReg, TrackReg,
1203 // Keep track of PHI nodes and its incoming edges when looking for sources.
1204 RewriteMapTy RewriteMap;
1205 // Try to find a more suitable source. If we failed to do so, or get the
1206 // actual source, move to the next source.
1207 if (!findNextSource(TrackReg, TrackSubReg, RewriteMap))
1210 // Get the new source to rewrite. TODO: Only enable handling of multiple
1211 // sources (PHIs) once we have a motivating example and testcases for it.
1212 TargetInstrInfo::RegSubRegPair TrackPair(TrackReg, TrackSubReg);
1213 TargetInstrInfo::RegSubRegPair NewSrc = CpyRewriter->getNewSource(
1214 MRI, TII, TrackPair, RewriteMap, false /* multiple sources */);
1215 if (SrcReg == NewSrc.Reg || NewSrc.Reg == 0)
1219 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) {
1220 // We may have extended the live-range of NewSrc, account for that.
1221 MRI->clearKillFlags(NewSrc.Reg);
1225 // TODO: We could have a clean-up method to tidy the instruction.
1226 // E.g., v0 = INSERT_SUBREG v1, v1.sub0, sub0
1228 // Currently we haven't seen motivating example for that and we
1229 // want to avoid untested code.
1230 NumRewrittenCopies += Changed;
1234 /// \brief Optimize copy-like instructions to create
1235 /// register coalescer friendly instruction.
1236 /// The optimization tries to kill-off the \p MI by looking
1237 /// through a chain of copies to find a source that has a compatible
1239 /// If such a source is found, it replace \p MI by a generic COPY
1241 /// \pre isUncoalescableCopy(*MI) is true.
1242 /// \return True, when \p MI has been optimized. In that case, \p MI has
1243 /// been removed from its parent.
1244 /// All COPY instructions created, are inserted in \p LocalMIs.
1245 bool PeepholeOptimizer::optimizeUncoalescableCopy(
1246 MachineInstr *MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
1247 assert(MI && isUncoalescableCopy(*MI) && "Invalid argument");
1249 // Check if we can rewrite all the values defined by this instruction.
1250 SmallVector<TargetInstrInfo::RegSubRegPair, 4> RewritePairs;
1251 // Get the right rewriter for the current copy.
1252 std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII, *MRI));
1253 // If none exists, bail out.
1257 // Rewrite each rewritable source by generating new COPYs. This works
1258 // differently from optimizeCoalescableCopy since it first makes sure that all
1259 // definitions can be rewritten.
1260 RewriteMapTy RewriteMap;
1261 unsigned Reg, SubReg, CopyDefReg, CopyDefSubReg;
1262 while (CpyRewriter->getNextRewritableSource(Reg, SubReg, CopyDefReg,
1264 // If a physical register is here, this is probably for a good reason.
1265 // Do not rewrite that.
1266 if (TargetRegisterInfo::isPhysicalRegister(CopyDefReg))
1269 // If we do not know how to rewrite this definition, there is no point
1270 // in trying to kill this instruction.
1271 TargetInstrInfo::RegSubRegPair Def(CopyDefReg, CopyDefSubReg);
1272 if (!findNextSource(Def.Reg, Def.SubReg, RewriteMap))
1275 RewritePairs.push_back(Def);
1278 // The change is possible for all defs, do it.
1279 for (const auto &Def : RewritePairs) {
1280 // Rewrite the "copy" in a way the register coalescer understands.
1281 MachineInstr *NewCopy = CpyRewriter->RewriteSource(Def, RewriteMap);
1282 assert(NewCopy && "Should be able to always generate a new copy");
1283 LocalMIs.insert(NewCopy);
1287 MI->eraseFromParent();
1288 ++NumUncoalescableCopies;
1292 /// Check whether MI is a candidate for folding into a later instruction.
1293 /// We only fold loads to virtual registers and the virtual register defined
1294 /// has a single use.
1295 bool PeepholeOptimizer::isLoadFoldable(
1296 MachineInstr *MI, SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) {
1297 if (!MI->canFoldAsLoad() || !MI->mayLoad())
1299 const MCInstrDesc &MCID = MI->getDesc();
1300 if (MCID.getNumDefs() != 1)
1303 unsigned Reg = MI->getOperand(0).getReg();
1304 // To reduce compilation time, we check MRI->hasOneNonDBGUse when inserting
1305 // loads. It should be checked when processing uses of the load, since
1306 // uses can be removed during peephole.
1307 if (!MI->getOperand(0).getSubReg() &&
1308 TargetRegisterInfo::isVirtualRegister(Reg) &&
1309 MRI->hasOneNonDBGUse(Reg)) {
1310 FoldAsLoadDefCandidates.insert(Reg);
1316 bool PeepholeOptimizer::isMoveImmediate(
1317 MachineInstr *MI, SmallSet<unsigned, 4> &ImmDefRegs,
1318 DenseMap<unsigned, MachineInstr *> &ImmDefMIs) {
1319 const MCInstrDesc &MCID = MI->getDesc();
1320 if (!MI->isMoveImmediate())
1322 if (MCID.getNumDefs() != 1)
1324 unsigned Reg = MI->getOperand(0).getReg();
1325 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1326 ImmDefMIs.insert(std::make_pair(Reg, MI));
1327 ImmDefRegs.insert(Reg);
1334 /// Try folding register operands that are defined by move immediate
1335 /// instructions, i.e. a trivial constant folding optimization, if
1336 /// and only if the def and use are in the same BB.
1337 bool PeepholeOptimizer::foldImmediate(
1338 MachineInstr *MI, MachineBasicBlock *MBB, SmallSet<unsigned, 4> &ImmDefRegs,
1339 DenseMap<unsigned, MachineInstr *> &ImmDefMIs) {
1340 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
1341 MachineOperand &MO = MI->getOperand(i);
1342 if (!MO.isReg() || MO.isDef())
1344 // Ignore dead implicit defs.
1345 if (MO.isImplicit() && MO.isDead())
1347 unsigned Reg = MO.getReg();
1348 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1350 if (ImmDefRegs.count(Reg) == 0)
1352 DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
1353 assert(II != ImmDefMIs.end() && "couldn't find immediate definition");
1354 if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
1362 // FIXME: This is very simple and misses some cases which should be handled when
1363 // motivating examples are found.
1365 // The copy rewriting logic should look at uses as well as defs and be able to
1366 // eliminate copies across blocks.
1368 // Later copies that are subregister extracts will also not be eliminated since
1369 // only the first copy is considered.
1372 // %vreg1 = COPY %vreg0
1373 // %vreg2 = COPY %vreg0:sub1
1375 // Should replace %vreg2 uses with %vreg1:sub1
1376 bool PeepholeOptimizer::foldRedundantCopy(
1377 MachineInstr *MI, SmallSet<unsigned, 4> &CopySrcRegs,
1378 DenseMap<unsigned, MachineInstr *> &CopyMIs) {
1379 assert(MI->isCopy() && "expected a COPY machine instruction");
1381 unsigned SrcReg = MI->getOperand(1).getReg();
1382 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1385 unsigned DstReg = MI->getOperand(0).getReg();
1386 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
1389 if (CopySrcRegs.insert(SrcReg).second) {
1390 // First copy of this reg seen.
1391 CopyMIs.insert(std::make_pair(SrcReg, MI));
1395 MachineInstr *PrevCopy = CopyMIs.find(SrcReg)->second;
1397 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1398 unsigned PrevSrcSubReg = PrevCopy->getOperand(1).getSubReg();
1400 // Can't replace different subregister extracts.
1401 if (SrcSubReg != PrevSrcSubReg)
1404 unsigned PrevDstReg = PrevCopy->getOperand(0).getReg();
1406 // Only replace if the copy register class is the same.
1408 // TODO: If we have multiple copies to different register classes, we may want
1409 // to track multiple copies of the same source register.
1410 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg))
1413 MRI->replaceRegWith(DstReg, PrevDstReg);
1415 // Lifetime of the previous copy has been extended.
1416 MRI->clearKillFlags(PrevDstReg);
1420 bool PeepholeOptimizer::isNAPhysCopy(unsigned Reg) {
1421 return TargetRegisterInfo::isPhysicalRegister(Reg) &&
1422 !MRI->isAllocatable(Reg);
1425 bool PeepholeOptimizer::foldRedundantNAPhysCopy(
1426 MachineInstr *MI, DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs) {
1427 assert(MI->isCopy() && "expected a COPY machine instruction");
1429 if (DisableNAPhysCopyOpt)
1432 unsigned DstReg = MI->getOperand(0).getReg();
1433 unsigned SrcReg = MI->getOperand(1).getReg();
1434 if (isNAPhysCopy(SrcReg) && TargetRegisterInfo::isVirtualRegister(DstReg)) {
1435 // %vreg = COPY %PHYSREG
1436 // Avoid using a datastructure which can track multiple live non-allocatable
1437 // phys->virt copies since LLVM doesn't seem to do this.
1438 NAPhysToVirtMIs.insert({SrcReg, MI});
1442 if (!(TargetRegisterInfo::isVirtualRegister(SrcReg) && isNAPhysCopy(DstReg)))
1445 // %PHYSREG = COPY %vreg
1446 auto PrevCopy = NAPhysToVirtMIs.find(DstReg);
1447 if (PrevCopy == NAPhysToVirtMIs.end()) {
1448 // We can't remove the copy: there was an intervening clobber of the
1449 // non-allocatable physical register after the copy to virtual.
1450 DEBUG(dbgs() << "NAPhysCopy: intervening clobber forbids erasing " << *MI
1455 unsigned PrevDstReg = PrevCopy->second->getOperand(0).getReg();
1456 if (PrevDstReg == SrcReg) {
1457 // Remove the virt->phys copy: we saw the virtual register definition, and
1458 // the non-allocatable physical register's state hasn't changed since then.
1459 DEBUG(dbgs() << "NAPhysCopy: erasing " << *MI << '\n');
1464 // Potential missed optimization opportunity: we saw a different virtual
1465 // register get a copy of the non-allocatable physical register, and we only
1466 // track one such copy. Avoid getting confused by this new non-allocatable
1467 // physical register definition, and remove it from the tracked copies.
1468 DEBUG(dbgs() << "NAPhysCopy: missed opportunity " << *MI << '\n');
1469 NAPhysToVirtMIs.erase(PrevCopy);
1473 bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
1474 if (skipOptnoneFunction(*MF.getFunction()))
1477 DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
1478 DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
1480 if (DisablePeephole)
1483 TII = MF.getSubtarget().getInstrInfo();
1484 TRI = MF.getSubtarget().getRegisterInfo();
1485 MRI = &MF.getRegInfo();
1486 DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : nullptr;
1488 bool Changed = false;
1490 for (MachineBasicBlock &MBB : MF) {
1491 bool SeenMoveImm = false;
1493 // During this forward scan, at some point it needs to answer the question
1494 // "given a pointer to an MI in the current BB, is it located before or
1495 // after the current instruction".
1496 // To perform this, the following set keeps track of the MIs already seen
1497 // during the scan, if a MI is not in the set, it is assumed to be located
1498 // after. Newly created MIs have to be inserted in the set as well.
1499 SmallPtrSet<MachineInstr*, 16> LocalMIs;
1500 SmallSet<unsigned, 4> ImmDefRegs;
1501 DenseMap<unsigned, MachineInstr*> ImmDefMIs;
1502 SmallSet<unsigned, 16> FoldAsLoadDefCandidates;
1504 // Track when a non-allocatable physical register is copied to a virtual
1505 // register so that useless moves can be removed.
1507 // %PHYSREG is the map index; MI is the last valid `%vreg = COPY %PHYSREG`
1508 // without any intervening re-definition of %PHYSREG.
1509 DenseMap<unsigned, MachineInstr *> NAPhysToVirtMIs;
1511 // Set of virtual registers that are copied from.
1512 SmallSet<unsigned, 4> CopySrcRegs;
1513 DenseMap<unsigned, MachineInstr *> CopySrcMIs;
1515 for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end();
1517 MachineInstr *MI = &*MII;
1518 // We may be erasing MI below, increment MII now.
1520 LocalMIs.insert(MI);
1522 // Skip debug values. They should not affect this peephole optimization.
1523 if (MI->isDebugValue())
1526 // If we run into an instruction we can't fold across, discard
1527 // the load candidates.
1528 if (MI->isLoadFoldBarrier())
1529 FoldAsLoadDefCandidates.clear();
1531 if (MI->isPosition() || MI->isPHI())
1534 if (!MI->isCopy()) {
1535 for (const auto &Op : MI->operands()) {
1536 // Visit all operands: definitions can be implicit or explicit.
1538 unsigned Reg = Op.getReg();
1539 if (Op.isDef() && isNAPhysCopy(Reg)) {
1540 const auto &Def = NAPhysToVirtMIs.find(Reg);
1541 if (Def != NAPhysToVirtMIs.end()) {
1542 // A new definition of the non-allocatable physical register
1543 // invalidates previous copies.
1544 DEBUG(dbgs() << "NAPhysCopy: invalidating because of " << *MI
1546 NAPhysToVirtMIs.erase(Def);
1549 } else if (Op.isRegMask()) {
1550 const uint32_t *RegMask = Op.getRegMask();
1551 for (auto &RegMI : NAPhysToVirtMIs) {
1552 unsigned Def = RegMI.first;
1553 if (MachineOperand::clobbersPhysReg(RegMask, Def)) {
1554 DEBUG(dbgs() << "NAPhysCopy: invalidating because of " << *MI
1556 NAPhysToVirtMIs.erase(Def);
1563 if (MI->isImplicitDef() || MI->isKill())
1566 if (MI->isInlineAsm() || MI->hasUnmodeledSideEffects()) {
1567 // Blow away all non-allocatable physical registers knowledge since we
1568 // don't know what's correct anymore.
1570 // FIXME: handle explicit asm clobbers.
1571 DEBUG(dbgs() << "NAPhysCopy: blowing away all info due to " << *MI
1573 NAPhysToVirtMIs.clear();
1577 if ((isUncoalescableCopy(*MI) &&
1578 optimizeUncoalescableCopy(MI, LocalMIs)) ||
1579 (MI->isCompare() && optimizeCmpInstr(MI, &MBB)) ||
1580 (MI->isSelect() && optimizeSelect(MI, LocalMIs))) {
1587 if (MI->isConditionalBranch() && optimizeCondBranch(MI)) {
1592 if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(MI)) {
1593 // MI is just rewritten.
1599 (foldRedundantCopy(MI, CopySrcRegs, CopySrcMIs) ||
1600 foldRedundantNAPhysCopy(MI, NAPhysToVirtMIs))) {
1602 MI->eraseFromParent();
1607 if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
1610 Changed |= optimizeExtInstr(MI, &MBB, LocalMIs);
1611 // optimizeExtInstr might have created new instructions after MI
1612 // and before the already incremented MII. Adjust MII so that the
1613 // next iteration sees the new instructions.
1617 Changed |= foldImmediate(MI, &MBB, ImmDefRegs, ImmDefMIs);
1620 // Check whether MI is a load candidate for folding into a later
1621 // instruction. If MI is not a candidate, check whether we can fold an
1622 // earlier load into MI.
1623 if (!isLoadFoldable(MI, FoldAsLoadDefCandidates) &&
1624 !FoldAsLoadDefCandidates.empty()) {
1625 const MCInstrDesc &MIDesc = MI->getDesc();
1626 for (unsigned i = MIDesc.getNumDefs(); i != MIDesc.getNumOperands();
1628 const MachineOperand &MOp = MI->getOperand(i);
1631 unsigned FoldAsLoadDefReg = MOp.getReg();
1632 if (FoldAsLoadDefCandidates.count(FoldAsLoadDefReg)) {
1633 // We need to fold load after optimizeCmpInstr, since
1634 // optimizeCmpInstr can enable folding by converting SUB to CMP.
1635 // Save FoldAsLoadDefReg because optimizeLoadInstr() resets it and
1636 // we need it for markUsesInDebugValueAsUndef().
1637 unsigned FoldedReg = FoldAsLoadDefReg;
1638 MachineInstr *DefMI = nullptr;
1639 MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI,
1643 // Update LocalMIs since we replaced MI with FoldMI and deleted
1645 DEBUG(dbgs() << "Replacing: " << *MI);
1646 DEBUG(dbgs() << " With: " << *FoldMI);
1648 LocalMIs.erase(DefMI);
1649 LocalMIs.insert(FoldMI);
1650 MI->eraseFromParent();
1651 DefMI->eraseFromParent();
1652 MRI->markUsesInDebugValueAsUndef(FoldedReg);
1653 FoldAsLoadDefCandidates.erase(FoldedReg);
1655 // MI is replaced with FoldMI.
1668 ValueTrackerResult ValueTracker::getNextSourceFromCopy() {
1669 assert(Def->isCopy() && "Invalid definition");
1670 // Copy instruction are supposed to be: Def = Src.
1671 // If someone breaks this assumption, bad things will happen everywhere.
1672 assert(Def->getNumOperands() == 2 && "Invalid number of operands");
1674 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1675 // If we look for a different subreg, it means we want a subreg of src.
1676 // Bails as we do not support composing subregs yet.
1677 return ValueTrackerResult();
1678 // Otherwise, we want the whole source.
1679 const MachineOperand &Src = Def->getOperand(1);
1680 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1683 ValueTrackerResult ValueTracker::getNextSourceFromBitcast() {
1684 assert(Def->isBitcast() && "Invalid definition");
1686 // Bail if there are effects that a plain copy will not expose.
1687 if (Def->hasUnmodeledSideEffects())
1688 return ValueTrackerResult();
1690 // Bitcasts with more than one def are not supported.
1691 if (Def->getDesc().getNumDefs() != 1)
1692 return ValueTrackerResult();
1693 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1694 // If we look for a different subreg, it means we want a subreg of the src.
1695 // Bails as we do not support composing subregs yet.
1696 return ValueTrackerResult();
1698 unsigned SrcIdx = Def->getNumOperands();
1699 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
1701 const MachineOperand &MO = Def->getOperand(OpIdx);
1702 if (!MO.isReg() || !MO.getReg())
1704 // Ignore dead implicit defs.
1705 if (MO.isImplicit() && MO.isDead())
1707 assert(!MO.isDef() && "We should have skipped all the definitions by now");
1708 if (SrcIdx != EndOpIdx)
1709 // Multiple sources?
1710 return ValueTrackerResult();
1713 const MachineOperand &Src = Def->getOperand(SrcIdx);
1714 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1717 ValueTrackerResult ValueTracker::getNextSourceFromRegSequence() {
1718 assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
1719 "Invalid definition");
1721 if (Def->getOperand(DefIdx).getSubReg())
1722 // If we are composing subregs, bail out.
1723 // The case we are checking is Def.<subreg> = REG_SEQUENCE.
1724 // This should almost never happen as the SSA property is tracked at
1725 // the register level (as opposed to the subreg level).
1729 // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
1730 // Def. Thus, it must not be generated.
1731 // However, some code could theoretically generates a single
1732 // Def.sub0 (i.e, not defining the other subregs) and we would
1734 // If we can ascertain (or force) that this never happens, we could
1735 // turn that into an assertion.
1736 return ValueTrackerResult();
1739 // We could handle the REG_SEQUENCE here, but we do not want to
1740 // duplicate the code from the generic TII.
1741 return ValueTrackerResult();
1743 SmallVector<TargetInstrInfo::RegSubRegPairAndIdx, 8> RegSeqInputRegs;
1744 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1745 return ValueTrackerResult();
1747 // We are looking at:
1748 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1749 // Check if one of the operand defines the subreg we are interested in.
1750 for (auto &RegSeqInput : RegSeqInputRegs) {
1751 if (RegSeqInput.SubIdx == DefSubReg) {
1752 if (RegSeqInput.SubReg)
1753 // Bail if we have to compose sub registers.
1754 return ValueTrackerResult();
1756 return ValueTrackerResult(RegSeqInput.Reg, RegSeqInput.SubReg);
1760 // If the subreg we are tracking is super-defined by another subreg,
1761 // we could follow this value. However, this would require to compose
1762 // the subreg and we do not do that for now.
1763 return ValueTrackerResult();
1766 ValueTrackerResult ValueTracker::getNextSourceFromInsertSubreg() {
1767 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
1768 "Invalid definition");
1770 if (Def->getOperand(DefIdx).getSubReg())
1771 // If we are composing subreg, bail out.
1772 // Same remark as getNextSourceFromRegSequence.
1773 // I.e., this may be turned into an assert.
1774 return ValueTrackerResult();
1777 // We could handle the REG_SEQUENCE here, but we do not want to
1778 // duplicate the code from the generic TII.
1779 return ValueTrackerResult();
1781 TargetInstrInfo::RegSubRegPair BaseReg;
1782 TargetInstrInfo::RegSubRegPairAndIdx InsertedReg;
1783 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
1784 return ValueTrackerResult();
1786 // We are looking at:
1787 // Def = INSERT_SUBREG v0, v1, sub1
1788 // There are two cases:
1789 // 1. DefSubReg == sub1, get v1.
1790 // 2. DefSubReg != sub1, the value may be available through v0.
1792 // #1 Check if the inserted register matches the required sub index.
1793 if (InsertedReg.SubIdx == DefSubReg) {
1794 return ValueTrackerResult(InsertedReg.Reg, InsertedReg.SubReg);
1796 // #2 Otherwise, if the sub register we are looking for is not partial
1797 // defined by the inserted element, we can look through the main
1799 const MachineOperand &MODef = Def->getOperand(DefIdx);
1800 // If the result register (Def) and the base register (v0) do not
1801 // have the same register class or if we have to compose
1802 // subregisters, bail out.
1803 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
1805 return ValueTrackerResult();
1807 // Get the TRI and check if the inserted sub-register overlaps with the
1808 // sub-register we are tracking.
1809 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
1811 (TRI->getSubRegIndexLaneMask(DefSubReg) &
1812 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) != 0)
1813 return ValueTrackerResult();
1814 // At this point, the value is available in v0 via the same subreg
1816 return ValueTrackerResult(BaseReg.Reg, DefSubReg);
1819 ValueTrackerResult ValueTracker::getNextSourceFromExtractSubreg() {
1820 assert((Def->isExtractSubreg() ||
1821 Def->isExtractSubregLike()) && "Invalid definition");
1822 // We are looking at:
1823 // Def = EXTRACT_SUBREG v0, sub0
1825 // Bail if we have to compose sub registers.
1826 // Indeed, if DefSubReg != 0, we would have to compose it with sub0.
1828 return ValueTrackerResult();
1831 // We could handle the EXTRACT_SUBREG here, but we do not want to
1832 // duplicate the code from the generic TII.
1833 return ValueTrackerResult();
1835 TargetInstrInfo::RegSubRegPairAndIdx ExtractSubregInputReg;
1836 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
1837 return ValueTrackerResult();
1839 // Bail if we have to compose sub registers.
1840 // Likewise, if v0.subreg != 0, we would have to compose v0.subreg with sub0.
1841 if (ExtractSubregInputReg.SubReg)
1842 return ValueTrackerResult();
1843 // Otherwise, the value is available in the v0.sub0.
1844 return ValueTrackerResult(ExtractSubregInputReg.Reg,
1845 ExtractSubregInputReg.SubIdx);
1848 ValueTrackerResult ValueTracker::getNextSourceFromSubregToReg() {
1849 assert(Def->isSubregToReg() && "Invalid definition");
1850 // We are looking at:
1851 // Def = SUBREG_TO_REG Imm, v0, sub0
1853 // Bail if we have to compose sub registers.
1854 // If DefSubReg != sub0, we would have to check that all the bits
1855 // we track are included in sub0 and if yes, we would have to
1856 // determine the right subreg in v0.
1857 if (DefSubReg != Def->getOperand(3).getImm())
1858 return ValueTrackerResult();
1859 // Bail if we have to compose sub registers.
1860 // Likewise, if v0.subreg != 0, we would have to compose it with sub0.
1861 if (Def->getOperand(2).getSubReg())
1862 return ValueTrackerResult();
1864 return ValueTrackerResult(Def->getOperand(2).getReg(),
1865 Def->getOperand(3).getImm());
1868 /// \brief Explore each PHI incoming operand and return its sources
1869 ValueTrackerResult ValueTracker::getNextSourceFromPHI() {
1870 assert(Def->isPHI() && "Invalid definition");
1871 ValueTrackerResult Res;
1873 // If we look for a different subreg, bail as we do not support composing
1875 if (Def->getOperand(0).getSubReg() != DefSubReg)
1876 return ValueTrackerResult();
1878 // Return all register sources for PHI instructions.
1879 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
1880 auto &MO = Def->getOperand(i);
1881 assert(MO.isReg() && "Invalid PHI instruction");
1882 Res.addSource(MO.getReg(), MO.getSubReg());
1888 ValueTrackerResult ValueTracker::getNextSourceImpl() {
1889 assert(Def && "This method needs a valid definition");
1892 (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic()) &&
1893 Def->getOperand(DefIdx).isDef() && "Invalid DefIdx");
1895 return getNextSourceFromCopy();
1896 if (Def->isBitcast())
1897 return getNextSourceFromBitcast();
1898 // All the remaining cases involve "complex" instructions.
1899 // Bail if we did not ask for the advanced tracking.
1900 if (!UseAdvancedTracking)
1901 return ValueTrackerResult();
1902 if (Def->isRegSequence() || Def->isRegSequenceLike())
1903 return getNextSourceFromRegSequence();
1904 if (Def->isInsertSubreg() || Def->isInsertSubregLike())
1905 return getNextSourceFromInsertSubreg();
1906 if (Def->isExtractSubreg() || Def->isExtractSubregLike())
1907 return getNextSourceFromExtractSubreg();
1908 if (Def->isSubregToReg())
1909 return getNextSourceFromSubregToReg();
1911 return getNextSourceFromPHI();
1912 return ValueTrackerResult();
1915 ValueTrackerResult ValueTracker::getNextSource() {
1916 // If we reach a point where we cannot move up in the use-def chain,
1917 // there is nothing we can get.
1919 return ValueTrackerResult();
1921 ValueTrackerResult Res = getNextSourceImpl();
1922 if (Res.isValid()) {
1923 // Update definition, definition index, and subregister for the
1924 // next call of getNextSource.
1925 // Update the current register.
1926 bool OneRegSrc = Res.getNumSources() == 1;
1928 Reg = Res.getSrcReg(0);
1929 // Update the result before moving up in the use-def chain
1930 // with the instruction containing the last found sources.
1933 // If we can still move up in the use-def chain, move to the next
1935 if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) {
1936 Def = MRI.getVRegDef(Reg);
1937 DefIdx = MRI.def_begin(Reg).getOperandNo();
1938 DefSubReg = Res.getSrcSubReg(0);
1942 // If we end up here, this means we will not be able to find another source
1943 // for the next iteration. Make sure any new call to getNextSource bails out
1944 // early by cutting the use-def chain.