1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "post-RA-sched"
22 #include "llvm/CodeGen/Passes.h"
23 #include "AggressiveAntiDepBreaker.h"
24 #include "AntiDepBreaker.h"
25 #include "CriticalAntiDepBreaker.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Analysis/AliasAnalysis.h"
29 #include "llvm/CodeGen/LatencyPriorityQueue.h"
30 #include "llvm/CodeGen/MachineDominators.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/RegisterClassInfo.h"
37 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
48 #include "llvm/Target/TargetSubtargetInfo.h"
51 STATISTIC(NumNoops, "Number of noops inserted");
52 STATISTIC(NumStalls, "Number of pipeline stalls");
53 STATISTIC(NumFixedAnti, "Number of fixed anti-dependencies");
55 // Post-RA scheduling is enabled with
56 // TargetSubtargetInfo.enablePostRAScheduler(). This flag can be used to
57 // override the target.
59 EnablePostRAScheduler("post-RA-scheduler",
60 cl::desc("Enable scheduling after register allocation"),
61 cl::init(false), cl::Hidden);
62 static cl::opt<std::string>
63 EnableAntiDepBreaking("break-anti-dependencies",
64 cl::desc("Break post-RA scheduling anti-dependencies: "
65 "\"critical\", \"all\", or \"none\""),
66 cl::init("none"), cl::Hidden);
68 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
70 DebugDiv("postra-sched-debugdiv",
71 cl::desc("Debug control MBBs that are scheduled"),
72 cl::init(0), cl::Hidden);
74 DebugMod("postra-sched-debugmod",
75 cl::desc("Debug control MBBs that are scheduled"),
76 cl::init(0), cl::Hidden);
78 AntiDepBreaker::~AntiDepBreaker() { }
81 class PostRAScheduler : public MachineFunctionPass {
82 const TargetInstrInfo *TII;
83 RegisterClassInfo RegClassInfo;
87 PostRAScheduler() : MachineFunctionPass(ID) {}
89 void getAnalysisUsage(AnalysisUsage &AU) const {
91 AU.addRequired<AliasAnalysis>();
92 AU.addRequired<TargetPassConfig>();
93 AU.addRequired<MachineDominatorTree>();
94 AU.addPreserved<MachineDominatorTree>();
95 AU.addRequired<MachineLoopInfo>();
96 AU.addPreserved<MachineLoopInfo>();
97 MachineFunctionPass::getAnalysisUsage(AU);
100 bool runOnMachineFunction(MachineFunction &Fn);
102 char PostRAScheduler::ID = 0;
104 class SchedulePostRATDList : public ScheduleDAGInstrs {
105 /// AvailableQueue - The priority queue to use for the available SUnits.
107 LatencyPriorityQueue AvailableQueue;
109 /// PendingQueue - This contains all of the instructions whose operands have
110 /// been issued, but their results are not ready yet (due to the latency of
111 /// the operation). Once the operands becomes available, the instruction is
112 /// added to the AvailableQueue.
113 std::vector<SUnit*> PendingQueue;
115 /// HazardRec - The hazard recognizer to use.
116 ScheduleHazardRecognizer *HazardRec;
118 /// AntiDepBreak - Anti-dependence breaking object, or NULL if none
119 AntiDepBreaker *AntiDepBreak;
121 /// AA - AliasAnalysis for making memory reference queries.
124 /// LiveRegs - true if the register is live.
127 /// The schedule. Null SUnit*'s represent noop instructions.
128 std::vector<SUnit*> Sequence;
130 /// The index in BB of RegionEnd.
132 /// This is the instruction number from the top of the current block, not
133 /// the SlotIndex. It is only used by the AntiDepBreaker.
137 SchedulePostRATDList(
138 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
139 AliasAnalysis *AA, const RegisterClassInfo&,
140 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
141 SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs);
143 ~SchedulePostRATDList();
145 /// startBlock - Initialize register live-range state for scheduling in
148 void startBlock(MachineBasicBlock *BB);
150 // Set the index of RegionEnd within the current BB.
151 void setEndIndex(unsigned EndIdx) { EndIndex = EndIdx; }
153 /// Initialize the scheduler state for the next scheduling region.
154 virtual void enterRegion(MachineBasicBlock *bb,
155 MachineBasicBlock::iterator begin,
156 MachineBasicBlock::iterator end,
157 unsigned regioninstrs);
159 /// Notify that the scheduler has finished scheduling the current region.
160 virtual void exitRegion();
162 /// Schedule - Schedule the instruction range using list scheduling.
168 /// Observe - Update liveness information to account for the current
169 /// instruction, which will not be scheduled.
171 void Observe(MachineInstr *MI, unsigned Count);
173 /// finishBlock - Clean up register live-range state.
177 /// FixupKills - Fix register kill flags that have been made
178 /// invalid due to scheduling
180 void FixupKills(MachineBasicBlock *MBB);
183 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
184 void ReleaseSuccessors(SUnit *SU);
185 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
186 void ListScheduleTopDown();
187 void StartBlockForKills(MachineBasicBlock *BB);
189 // ToggleKillFlag - Toggle a register operand kill flag. Other
190 // adjustments may be made to the instruction if necessary. Return
191 // true if the operand has been deleted, false if not.
192 bool ToggleKillFlag(MachineInstr *MI, MachineOperand &MO);
194 void dumpSchedule() const;
198 char &llvm::PostRASchedulerID = PostRAScheduler::ID;
200 INITIALIZE_PASS(PostRAScheduler, "post-RA-sched",
201 "Post RA top-down list latency scheduler", false, false)
203 SchedulePostRATDList::SchedulePostRATDList(
204 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
205 AliasAnalysis *AA, const RegisterClassInfo &RCI,
206 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
207 SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs)
208 : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), AA(AA),
209 LiveRegs(TRI->getNumRegs()), EndIndex(0)
211 const TargetMachine &TM = MF.getTarget();
212 const InstrItineraryData *InstrItins = TM.getInstrItineraryData();
214 TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins, this);
216 assert((AntiDepMode == TargetSubtargetInfo::ANTIDEP_NONE ||
217 MRI.tracksLiveness()) &&
218 "Live-ins must be accurate for anti-dependency breaking");
220 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_ALL) ?
221 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
222 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_CRITICAL) ?
223 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL));
226 SchedulePostRATDList::~SchedulePostRATDList() {
231 /// Initialize state associated with the next scheduling region.
232 void SchedulePostRATDList::enterRegion(MachineBasicBlock *bb,
233 MachineBasicBlock::iterator begin,
234 MachineBasicBlock::iterator end,
235 unsigned regioninstrs) {
236 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
240 /// Print the schedule before exiting the region.
241 void SchedulePostRATDList::exitRegion() {
243 dbgs() << "*** Final schedule ***\n";
247 ScheduleDAGInstrs::exitRegion();
250 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
251 /// dumpSchedule - dump the scheduled Sequence.
252 void SchedulePostRATDList::dumpSchedule() const {
253 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
254 if (SUnit *SU = Sequence[i])
257 dbgs() << "**** NOOP ****\n";
262 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
263 TII = Fn.getTarget().getInstrInfo();
264 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
265 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
266 AliasAnalysis *AA = &getAnalysis<AliasAnalysis>();
267 TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
269 RegClassInfo.runOnMachineFunction(Fn);
271 // Check for explicit enable/disable of post-ra scheduling.
272 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode =
273 TargetSubtargetInfo::ANTIDEP_NONE;
274 SmallVector<const TargetRegisterClass*, 4> CriticalPathRCs;
275 if (EnablePostRAScheduler.getPosition() > 0) {
276 if (!EnablePostRAScheduler)
279 // Check that post-RA scheduling is enabled for this target.
280 // This may upgrade the AntiDepMode.
281 const TargetSubtargetInfo &ST = Fn.getTarget().getSubtarget<TargetSubtargetInfo>();
282 if (!ST.enablePostRAScheduler(PassConfig->getOptLevel(), AntiDepMode,
287 // Check for antidep breaking override...
288 if (EnableAntiDepBreaking.getPosition() > 0) {
289 AntiDepMode = (EnableAntiDepBreaking == "all")
290 ? TargetSubtargetInfo::ANTIDEP_ALL
291 : ((EnableAntiDepBreaking == "critical")
292 ? TargetSubtargetInfo::ANTIDEP_CRITICAL
293 : TargetSubtargetInfo::ANTIDEP_NONE);
296 DEBUG(dbgs() << "PostRAScheduler\n");
298 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
301 // Loop over all of the basic blocks
302 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
303 MBB != MBBe; ++MBB) {
305 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
307 static int bbcnt = 0;
308 if (bbcnt++ % DebugDiv != DebugMod)
310 dbgs() << "*** DEBUG scheduling " << Fn.getName()
311 << ":BB#" << MBB->getNumber() << " ***\n";
315 // Initialize register live-range state for scheduling in this block.
316 Scheduler.startBlock(MBB);
318 // Schedule each sequence of instructions not interrupted by a label
319 // or anything else that effectively needs to shut down scheduling.
320 MachineBasicBlock::iterator Current = MBB->end();
321 unsigned Count = MBB->size(), CurrentCount = Count;
322 for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
323 MachineInstr *MI = llvm::prior(I);
325 // Calls are not scheduling boundaries before register allocation, but
326 // post-ra we don't gain anything by scheduling across calls since we
327 // don't need to worry about register pressure.
328 if (MI->isCall() || TII->isSchedulingBoundary(MI, MBB, Fn)) {
329 Scheduler.enterRegion(MBB, I, Current, CurrentCount - Count);
330 Scheduler.setEndIndex(CurrentCount);
331 Scheduler.schedule();
332 Scheduler.exitRegion();
333 Scheduler.EmitSchedule();
335 CurrentCount = Count;
336 Scheduler.Observe(MI, CurrentCount);
340 Count -= MI->getBundleSize();
342 assert(Count == 0 && "Instruction count mismatch!");
343 assert((MBB->begin() == Current || CurrentCount != 0) &&
344 "Instruction count mismatch!");
345 Scheduler.enterRegion(MBB, MBB->begin(), Current, CurrentCount);
346 Scheduler.setEndIndex(CurrentCount);
347 Scheduler.schedule();
348 Scheduler.exitRegion();
349 Scheduler.EmitSchedule();
351 // Clean up register live-range state.
352 Scheduler.finishBlock();
354 // Update register kills
355 Scheduler.FixupKills(MBB);
361 /// StartBlock - Initialize register live-range state for scheduling in
364 void SchedulePostRATDList::startBlock(MachineBasicBlock *BB) {
365 // Call the superclass.
366 ScheduleDAGInstrs::startBlock(BB);
368 // Reset the hazard recognizer and anti-dep breaker.
370 if (AntiDepBreak != NULL)
371 AntiDepBreak->StartBlock(BB);
374 /// Schedule - Schedule the instruction range using list scheduling.
376 void SchedulePostRATDList::schedule() {
377 // Build the scheduling graph.
380 if (AntiDepBreak != NULL) {
382 AntiDepBreak->BreakAntiDependencies(SUnits, RegionBegin, RegionEnd,
383 EndIndex, DbgValues);
386 // We made changes. Update the dependency graph.
387 // Theoretically we could update the graph in place:
388 // When a live range is changed to use a different register, remove
389 // the def's anti-dependence *and* output-dependence edges due to
390 // that register, and add new anti-dependence and output-dependence
391 // edges based on the next live range of the register.
392 ScheduleDAG::clearDAG();
395 NumFixedAnti += Broken;
399 DEBUG(dbgs() << "********** List Scheduling **********\n");
400 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
401 SUnits[su].dumpAll(this));
403 AvailableQueue.initNodes(SUnits);
404 ListScheduleTopDown();
405 AvailableQueue.releaseState();
408 /// Observe - Update liveness information to account for the current
409 /// instruction, which will not be scheduled.
411 void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
412 if (AntiDepBreak != NULL)
413 AntiDepBreak->Observe(MI, Count, EndIndex);
416 /// FinishBlock - Clean up register live-range state.
418 void SchedulePostRATDList::finishBlock() {
419 if (AntiDepBreak != NULL)
420 AntiDepBreak->FinishBlock();
422 // Call the superclass.
423 ScheduleDAGInstrs::finishBlock();
426 /// StartBlockForKills - Initialize register live-range state for updating kills
428 void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
429 // Start with no live registers.
432 // Examine the live-in regs of all successors.
433 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
434 SE = BB->succ_end(); SI != SE; ++SI) {
435 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
436 E = (*SI)->livein_end(); I != E; ++I) {
438 // Repeat, for reg and all subregs.
439 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
440 SubRegs.isValid(); ++SubRegs)
441 LiveRegs.set(*SubRegs);
446 bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
447 MachineOperand &MO) {
448 // Setting kill flag...
454 // If MO itself is live, clear the kill flag...
455 if (LiveRegs.test(MO.getReg())) {
460 // If any subreg of MO is live, then create an imp-def for that
461 // subreg and keep MO marked as killed.
464 const unsigned SuperReg = MO.getReg();
465 MachineInstrBuilder MIB(MF, MI);
466 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
467 if (LiveRegs.test(*SubRegs)) {
468 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
478 /// FixupKills - Fix the register kill flags, they may have been made
479 /// incorrect by instruction reordering.
481 void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
482 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
484 BitVector killedRegs(TRI->getNumRegs());
486 StartBlockForKills(MBB);
488 // Examine block from end to start...
489 unsigned Count = MBB->size();
490 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
492 MachineInstr *MI = --I;
493 if (MI->isDebugValue())
496 // Update liveness. Registers that are defed but not used in this
497 // instruction are now dead. Mark register and all subregs as they
498 // are completely defined.
499 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
500 MachineOperand &MO = MI->getOperand(i);
502 LiveRegs.clearBitsNotInMask(MO.getRegMask());
503 if (!MO.isReg()) continue;
504 unsigned Reg = MO.getReg();
505 if (Reg == 0) continue;
506 if (!MO.isDef()) continue;
507 // Ignore two-addr defs.
508 if (MI->isRegTiedToUseOperand(i)) continue;
510 // Repeat for reg and all subregs.
511 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
512 SubRegs.isValid(); ++SubRegs)
513 LiveRegs.reset(*SubRegs);
516 // Examine all used registers and set/clear kill flag. When a
517 // register is used multiple times we only set the kill flag on
518 // the first use. Don't set kill flags on undef operands.
520 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
521 MachineOperand &MO = MI->getOperand(i);
522 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
523 unsigned Reg = MO.getReg();
524 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
527 if (!killedRegs.test(Reg)) {
529 // A register is not killed if any subregs are live...
530 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
531 if (LiveRegs.test(*SubRegs)) {
537 // If subreg is not live, then register is killed if it became
538 // live in this instruction
540 kill = !LiveRegs.test(Reg);
543 if (MO.isKill() != kill) {
544 DEBUG(dbgs() << "Fixing " << MO << " in ");
545 // Warning: ToggleKillFlag may invalidate MO.
546 ToggleKillFlag(MI, MO);
553 // Mark any used register (that is not using undef) and subregs as
555 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
556 MachineOperand &MO = MI->getOperand(i);
557 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
558 unsigned Reg = MO.getReg();
559 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
561 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
562 SubRegs.isValid(); ++SubRegs)
563 LiveRegs.set(*SubRegs);
568 //===----------------------------------------------------------------------===//
569 // Top-Down Scheduling
570 //===----------------------------------------------------------------------===//
572 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
573 /// the PendingQueue if the count reaches zero.
574 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
575 SUnit *SuccSU = SuccEdge->getSUnit();
577 if (SuccEdge->isWeak()) {
578 --SuccSU->WeakPredsLeft;
582 if (SuccSU->NumPredsLeft == 0) {
583 dbgs() << "*** Scheduling failed! ***\n";
585 dbgs() << " has been released too many times!\n";
589 --SuccSU->NumPredsLeft;
591 // Standard scheduler algorithms will recompute the depth of the successor
593 // SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
595 // However, we lazily compute node depth instead. Note that
596 // ScheduleNodeTopDown has already updated the depth of this node which causes
597 // all descendents to be marked dirty. Setting the successor depth explicitly
598 // here would cause depth to be recomputed for all its ancestors. If the
599 // successor is not yet ready (because of a transitively redundant edge) then
600 // this causes depth computation to be quadratic in the size of the DAG.
602 // If all the node's predecessors are scheduled, this node is ready
603 // to be scheduled. Ignore the special ExitSU node.
604 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
605 PendingQueue.push_back(SuccSU);
608 /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
609 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
610 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
612 ReleaseSucc(SU, &*I);
616 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
617 /// count of its successors. If a successor pending count is zero, add it to
618 /// the Available queue.
619 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
620 DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
621 DEBUG(SU->dump(this));
623 Sequence.push_back(SU);
624 assert(CurCycle >= SU->getDepth() &&
625 "Node scheduled above its depth!");
626 SU->setDepthToAtLeast(CurCycle);
628 ReleaseSuccessors(SU);
629 SU->isScheduled = true;
630 AvailableQueue.scheduledNode(SU);
633 /// ListScheduleTopDown - The main loop of list scheduling for top-down
635 void SchedulePostRATDList::ListScheduleTopDown() {
636 unsigned CurCycle = 0;
638 // We're scheduling top-down but we're visiting the regions in
639 // bottom-up order, so we don't know the hazards at the start of a
640 // region. So assume no hazards (this should usually be ok as most
641 // blocks are a single region).
644 // Release any successors of the special Entry node.
645 ReleaseSuccessors(&EntrySU);
647 // Add all leaves to Available queue.
648 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
649 // It is available if it has no predecessors.
650 if (!SUnits[i].NumPredsLeft && !SUnits[i].isAvailable) {
651 AvailableQueue.push(&SUnits[i]);
652 SUnits[i].isAvailable = true;
656 // In any cycle where we can't schedule any instructions, we must
657 // stall or emit a noop, depending on the target.
658 bool CycleHasInsts = false;
660 // While Available queue is not empty, grab the node with the highest
661 // priority. If it is not ready put it back. Schedule the node.
662 std::vector<SUnit*> NotReady;
663 Sequence.reserve(SUnits.size());
664 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
665 // Check to see if any of the pending instructions are ready to issue. If
666 // so, add them to the available queue.
667 unsigned MinDepth = ~0u;
668 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
669 if (PendingQueue[i]->getDepth() <= CurCycle) {
670 AvailableQueue.push(PendingQueue[i]);
671 PendingQueue[i]->isAvailable = true;
672 PendingQueue[i] = PendingQueue.back();
673 PendingQueue.pop_back();
675 } else if (PendingQueue[i]->getDepth() < MinDepth)
676 MinDepth = PendingQueue[i]->getDepth();
679 DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this));
681 SUnit *FoundSUnit = 0;
682 bool HasNoopHazards = false;
683 while (!AvailableQueue.empty()) {
684 SUnit *CurSUnit = AvailableQueue.pop();
686 ScheduleHazardRecognizer::HazardType HT =
687 HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
688 if (HT == ScheduleHazardRecognizer::NoHazard) {
689 FoundSUnit = CurSUnit;
693 // Remember if this is a noop hazard.
694 HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
696 NotReady.push_back(CurSUnit);
699 // Add the nodes that aren't ready back onto the available list.
700 if (!NotReady.empty()) {
701 AvailableQueue.push_all(NotReady);
705 // If we found a node to schedule...
707 // ... schedule the node...
708 ScheduleNodeTopDown(FoundSUnit, CurCycle);
709 HazardRec->EmitInstruction(FoundSUnit);
710 CycleHasInsts = true;
711 if (HazardRec->atIssueLimit()) {
712 DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n');
713 HazardRec->AdvanceCycle();
715 CycleHasInsts = false;
719 DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
720 HazardRec->AdvanceCycle();
721 } else if (!HasNoopHazards) {
722 // Otherwise, we have a pipeline stall, but no other problem,
723 // just advance the current cycle and try again.
724 DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n');
725 HazardRec->AdvanceCycle();
728 // Otherwise, we have no instructions to issue and we have instructions
729 // that will fault if we don't do this right. This is the case for
730 // processors without pipeline interlocks and other cases.
731 DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n');
732 HazardRec->EmitNoop();
733 Sequence.push_back(0); // NULL here means noop
738 CycleHasInsts = false;
743 unsigned ScheduledNodes = VerifyScheduledDAG(/*isBottomUp=*/false);
745 for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
748 assert(Sequence.size() - Noops == ScheduledNodes &&
749 "The number of nodes scheduled doesn't match the expected number!");
753 // EmitSchedule - Emit the machine code in scheduled order.
754 void SchedulePostRATDList::EmitSchedule() {
755 RegionBegin = RegionEnd;
757 // If first instruction was a DBG_VALUE then put it back.
759 BB->splice(RegionEnd, BB, FirstDbgValue);
761 // Then re-insert them according to the given schedule.
762 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
763 if (SUnit *SU = Sequence[i])
764 BB->splice(RegionEnd, BB, SU->getInstr());
766 // Null SUnit* is a noop.
767 TII->insertNoop(*BB, RegionEnd);
769 // Update the Begin iterator, as the first instruction in the block
770 // may have been scheduled later.
772 RegionBegin = prior(RegionEnd);
775 // Reinsert any remaining debug_values.
776 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
777 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
778 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
779 MachineInstr *DbgValue = P.first;
780 MachineBasicBlock::iterator OrigPrivMI = P.second;
781 BB->splice(++OrigPrivMI, BB, DbgValue);
784 FirstDbgValue = NULL;