1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "post-RA-sched"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
24 #include "llvm/CodeGen/LatencyPriorityQueue.h"
25 #include "llvm/CodeGen/SchedulerRegistry.h"
26 #include "llvm/CodeGen/MachineDominators.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/ADT/Statistic.h"
40 STATISTIC(NumNoops, "Number of noops inserted");
41 STATISTIC(NumStalls, "Number of pipeline stalls");
44 EnableAntiDepBreaking("break-anti-dependencies",
45 cl::desc("Break post-RA scheduling anti-dependencies"),
46 cl::init(true), cl::Hidden);
49 EnablePostRAHazardAvoidance("avoid-hazards",
50 cl::desc("Enable simple hazard-avoidance"),
51 cl::init(true), cl::Hidden);
54 class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
57 PostRAScheduler() : MachineFunctionPass(&ID) {}
59 void getAnalysisUsage(AnalysisUsage &AU) const {
60 AU.addRequired<MachineDominatorTree>();
61 AU.addPreserved<MachineDominatorTree>();
62 AU.addRequired<MachineLoopInfo>();
63 AU.addPreserved<MachineLoopInfo>();
64 MachineFunctionPass::getAnalysisUsage(AU);
67 const char *getPassName() const {
68 return "Post RA top-down list latency scheduler";
71 bool runOnMachineFunction(MachineFunction &Fn);
73 char PostRAScheduler::ID = 0;
75 class VISIBILITY_HIDDEN SchedulePostRATDList : public ScheduleDAGInstrs {
76 /// AvailableQueue - The priority queue to use for the available SUnits.
78 LatencyPriorityQueue AvailableQueue;
80 /// PendingQueue - This contains all of the instructions whose operands have
81 /// been issued, but their results are not ready yet (due to the latency of
82 /// the operation). Once the operands becomes available, the instruction is
83 /// added to the AvailableQueue.
84 std::vector<SUnit*> PendingQueue;
86 /// Topo - A topological ordering for SUnits.
87 ScheduleDAGTopologicalSort Topo;
89 /// AllocatableSet - The set of allocatable registers.
90 /// We'll be ignoring anti-dependencies on non-allocatable registers,
91 /// because they may not be safe to break.
92 const BitVector AllocatableSet;
94 /// HazardRec - The hazard recognizer to use.
95 ScheduleHazardRecognizer *HazardRec;
98 SchedulePostRATDList(MachineFunction &MF,
99 const MachineLoopInfo &MLI,
100 const MachineDominatorTree &MDT,
101 ScheduleHazardRecognizer *HR)
102 : ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
103 AllocatableSet(TRI->getAllocatableSet(MF)),
106 ~SchedulePostRATDList() {
113 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
114 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
115 void ListScheduleTopDown();
116 bool BreakAntiDependencies();
119 /// SimpleHazardRecognizer - A *very* simple hazard recognizer. It uses
120 /// a coarse classification and attempts to avoid that instructions of
121 /// a given class aren't grouped too densely together.
122 class SimpleHazardRecognizer : public ScheduleHazardRecognizer {
123 /// Class - A simple classification for SUnits.
128 /// Window - The Class values of the most recently issued
132 /// getClass - Classify the given SUnit.
133 Class getClass(const SUnit *SU) {
134 const MachineInstr *MI = SU->getInstr();
135 const TargetInstrDesc &TID = MI->getDesc();
143 /// Step - Rotate the existing entries in Window and insert the
144 /// given class value in position as the most recent.
146 std::copy(Window+1, array_endof(Window), Window);
147 Window[array_lengthof(Window)-1] = C;
151 SimpleHazardRecognizer() : Window() {}
153 virtual HazardType getHazardType(SUnit *SU) {
154 Class C = getClass(SU);
158 for (int i = 0; i != array_lengthof(Window); ++i)
161 if (Score > array_lengthof(Window) * 2)
166 virtual void EmitInstruction(SUnit *SU) {
170 virtual void AdvanceCycle() {
176 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
177 DOUT << "PostRAScheduler\n";
179 const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
180 const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
181 ScheduleHazardRecognizer *HR = EnablePostRAHazardAvoidance ?
182 new SimpleHazardRecognizer :
183 new ScheduleHazardRecognizer();
185 SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR);
187 // Loop over all of the basic blocks
188 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
189 MBB != MBBe; ++MBB) {
191 Scheduler.Run(0, MBB);
193 Scheduler.EmitSchedule();
199 /// Schedule - Schedule the DAG using list scheduling.
200 void SchedulePostRATDList::Schedule() {
201 DOUT << "********** List Scheduling **********\n";
203 // Build the scheduling graph.
206 if (EnableAntiDepBreaking) {
207 if (BreakAntiDependencies()) {
208 // We made changes. Update the dependency graph.
209 // Theoretically we could update the graph in place:
210 // When a live range is changed to use a different register, remove
211 // the def's anti-dependence *and* output-dependence edges due to
212 // that register, and add new anti-dependence and output-dependence
213 // edges based on the next live range of the register.
219 AvailableQueue.initNodes(SUnits);
221 ListScheduleTopDown();
223 AvailableQueue.releaseState();
226 /// getInstrOperandRegClass - Return register class of the operand of an
227 /// instruction of the specified TargetInstrDesc.
228 static const TargetRegisterClass*
229 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
230 const TargetInstrInfo *TII, const TargetInstrDesc &II,
232 if (Op >= II.getNumOperands())
234 if (II.OpInfo[Op].isLookupPtrRegClass())
235 return TII->getPointerRegClass();
236 return TRI->getRegClass(II.OpInfo[Op].RegClass);
239 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
241 static SDep *CriticalPathStep(SUnit *SU) {
243 unsigned NextDepth = 0;
244 // Find the predecessor edge with the greatest depth.
245 for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
247 SUnit *PredSU = P->getSUnit();
248 unsigned PredLatency = P->getLatency();
249 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
250 // In the case of a latency tie, prefer an anti-dependency edge over
251 // other types of edges.
252 if (NextDepth < PredTotalLatency ||
253 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
254 NextDepth = PredTotalLatency;
261 /// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
262 /// of the ScheduleDAG and break them by renaming registers.
264 bool SchedulePostRATDList::BreakAntiDependencies() {
265 // The code below assumes that there is at least one instruction,
266 // so just duck out immediately if the block is empty.
267 if (BB->empty()) return false;
269 // Find the node at the bottom of the critical path.
271 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
272 SUnit *SU = &SUnits[i];
273 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
277 DOUT << "Critical path has total latency "
278 << (Max ? Max->getDepth() + Max->Latency : 0) << "\n";
280 // Track progress along the critical path through the SUnit graph as we walk
282 SUnit *CriticalPathSU = Max;
283 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
285 // For live regs that are only used in one register class in a live range,
286 // the register class. If the register is not live, the corresponding value
287 // is null. If the register is live but used in multiple register classes,
288 // the corresponding value is -1 casted to a pointer.
289 const TargetRegisterClass *
290 Classes[TargetRegisterInfo::FirstVirtualRegister] = {};
292 // Map registers to all their references within a live range.
293 std::multimap<unsigned, MachineOperand *> RegRefs;
295 // The index of the most recent kill (proceding bottom-up), or ~0u if
296 // the register is not live.
297 unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
298 std::fill(KillIndices, array_endof(KillIndices), ~0u);
299 // The index of the most recent complete def (proceding bottom up), or ~0u if
300 // the register is live.
301 unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
302 std::fill(DefIndices, array_endof(DefIndices), BB->size());
304 // Determine the live-out physregs for this block.
305 if (BB->back().getDesc().isReturn())
306 // In a return block, examine the function live-out regs.
307 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
308 E = MRI.liveout_end(); I != E; ++I) {
310 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
311 KillIndices[Reg] = BB->size();
312 DefIndices[Reg] = ~0u;
313 // Repeat, for all aliases.
314 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
315 unsigned AliasReg = *Alias;
316 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
317 KillIndices[AliasReg] = BB->size();
318 DefIndices[AliasReg] = ~0u;
322 // In a non-return block, examine the live-in regs of all successors.
323 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
324 SE = BB->succ_end(); SI != SE; ++SI)
325 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
326 E = (*SI)->livein_end(); I != E; ++I) {
328 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
329 KillIndices[Reg] = BB->size();
330 DefIndices[Reg] = ~0u;
331 // Repeat, for all aliases.
332 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
333 unsigned AliasReg = *Alias;
334 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
335 KillIndices[AliasReg] = BB->size();
336 DefIndices[AliasReg] = ~0u;
340 // Consider callee-saved registers as live-out, since we're running after
341 // prologue/epilogue insertion so there's no way to add additional
344 // TODO: If the callee saves and restores these, then we can potentially
345 // use them between the save and the restore. To do that, we could scan
346 // the exit blocks to see which of these registers are defined.
347 // Alternatively, callee-saved registers that aren't saved and restored
348 // could be marked live-in in every block.
349 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
351 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
352 KillIndices[Reg] = BB->size();
353 DefIndices[Reg] = ~0u;
354 // Repeat, for all aliases.
355 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
356 unsigned AliasReg = *Alias;
357 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
358 KillIndices[AliasReg] = BB->size();
359 DefIndices[AliasReg] = ~0u;
363 // Consider this pattern:
372 // There are three anti-dependencies here, and without special care,
373 // we'd break all of them using the same register:
382 // because at each anti-dependence, B is the first register that
383 // isn't A which is free. This re-introduces anti-dependencies
384 // at all but one of the original anti-dependencies that we were
385 // trying to break. To avoid this, keep track of the most recent
386 // register that each register was replaced with, avoid avoid
387 // using it to repair an anti-dependence on the same register.
388 // This lets us produce this:
397 // This still has an anti-dependence on B, but at least it isn't on the
398 // original critical path.
400 // TODO: If we tracked more than one register here, we could potentially
401 // fix that remaining critical edge too. This is a little more involved,
402 // because unlike the most recent register, less recent registers should
403 // still be considered, though only if no other registers are available.
404 unsigned LastNewReg[TargetRegisterInfo::FirstVirtualRegister] = {};
406 // Attempt to break anti-dependence edges on the critical path. Walk the
407 // instructions from the bottom up, tracking information about liveness
408 // as we go to help determine which registers are available.
409 bool Changed = false;
410 unsigned Count = BB->size() - 1;
411 for (MachineBasicBlock::reverse_iterator I = BB->rbegin(), E = BB->rend();
412 I != E; ++I, --Count) {
413 MachineInstr *MI = &*I;
415 // After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
416 // dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
417 // is left behind appearing to clobber the super-register, while the
418 // subregister needs to remain live. So we just ignore them.
419 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
422 // Check if this instruction has a dependence on the critical path that
423 // is an anti-dependence that we may be able to break. If it is, set
424 // AntiDepReg to the non-zero register associated with the anti-dependence.
426 // We limit our attention to the critical path as a heuristic to avoid
427 // breaking anti-dependence edges that aren't going to significantly
428 // impact the overall schedule. There are a limited number of registers
429 // and we want to save them for the important edges.
431 // TODO: Instructions with multiple defs could have multiple
432 // anti-dependencies. The current code here only knows how to break one
433 // edge per instruction. Note that we'd have to be able to break all of
434 // the anti-dependencies in an instruction in order to be effective.
435 unsigned AntiDepReg = 0;
436 if (MI == CriticalPathMI) {
437 if (SDep *Edge = CriticalPathStep(CriticalPathSU)) {
438 SUnit *NextSU = Edge->getSUnit();
440 // Only consider anti-dependence edges.
441 if (Edge->getKind() == SDep::Anti) {
442 AntiDepReg = Edge->getReg();
443 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
444 // Don't break anti-dependencies on non-allocatable registers.
445 if (AllocatableSet.test(AntiDepReg)) {
446 // If the SUnit has other dependencies on the SUnit that it
447 // anti-depends on, don't bother breaking the anti-dependency
448 // since those edges would prevent such units from being
449 // scheduled past each other regardless.
451 // Also, if there are dependencies on other SUnits with the
452 // same register as the anti-dependency, don't attempt to
454 for (SUnit::pred_iterator P = CriticalPathSU->Preds.begin(),
455 PE = CriticalPathSU->Preds.end(); P != PE; ++P)
456 if (P->getSUnit() == NextSU ?
457 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
458 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
464 CriticalPathSU = NextSU;
465 CriticalPathMI = CriticalPathSU->getInstr();
467 // We've reached the end of the critical path.
473 // Scan the register operands for this instruction and update
474 // Classes and RegRefs.
475 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
476 MachineOperand &MO = MI->getOperand(i);
477 if (!MO.isReg()) continue;
478 unsigned Reg = MO.getReg();
479 if (Reg == 0) continue;
480 const TargetRegisterClass *NewRC =
481 getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
483 // If this instruction has a use of AntiDepReg, breaking it
485 if (MO.isUse() && AntiDepReg == Reg)
488 // For now, only allow the register to be changed if its register
489 // class is consistent across all uses.
490 if (!Classes[Reg] && NewRC)
491 Classes[Reg] = NewRC;
492 else if (!NewRC || Classes[Reg] != NewRC)
493 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
495 // Now check for aliases.
496 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
497 // If an alias of the reg is used during the live range, give up.
498 // Note that this allows us to skip checking if AntiDepReg
499 // overlaps with any of the aliases, among other things.
500 unsigned AliasReg = *Alias;
501 if (Classes[AliasReg]) {
502 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
503 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
507 // If we're still willing to consider this register, note the reference.
508 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
509 RegRefs.insert(std::make_pair(Reg, &MO));
512 // Determine AntiDepReg's register class, if it is live and is
513 // consistently used within a single class.
514 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
515 assert((AntiDepReg == 0 || RC != NULL) &&
516 "Register should be live if it's causing an anti-dependence!");
517 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
520 // Look for a suitable register to use to break the anti-depenence.
522 // TODO: Instead of picking the first free register, consider which might
524 if (AntiDepReg != 0) {
525 for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF),
526 RE = RC->allocation_order_end(MF); R != RE; ++R) {
527 unsigned NewReg = *R;
528 // Don't replace a register with itself.
529 if (NewReg == AntiDepReg) continue;
530 // Don't replace a register with one that was recently used to repair
531 // an anti-dependence with this AntiDepReg, because that would
532 // re-introduce that anti-dependence.
533 if (NewReg == LastNewReg[AntiDepReg]) continue;
534 // If NewReg is dead and NewReg's most recent def is not before
535 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
536 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) &&
537 "Kill and Def maps aren't consistent for AntiDepReg!");
538 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) &&
539 "Kill and Def maps aren't consistent for NewReg!");
540 if (KillIndices[NewReg] == ~0u &&
541 Classes[NewReg] != reinterpret_cast<TargetRegisterClass *>(-1) &&
542 KillIndices[AntiDepReg] <= DefIndices[NewReg]) {
543 DOUT << "Breaking anti-dependence edge on "
544 << TRI->getName(AntiDepReg)
545 << " with " << RegRefs.count(AntiDepReg) << " references"
546 << " using " << TRI->getName(NewReg) << "!\n";
548 // Update the references to the old register to refer to the new
550 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
551 std::multimap<unsigned, MachineOperand *>::iterator>
552 Range = RegRefs.equal_range(AntiDepReg);
553 for (std::multimap<unsigned, MachineOperand *>::iterator
554 Q = Range.first, QE = Range.second; Q != QE; ++Q)
555 Q->second->setReg(NewReg);
557 // We just went back in time and modified history; the
558 // liveness information for the anti-depenence reg is now
559 // inconsistent. Set the state as if it were dead.
560 Classes[NewReg] = Classes[AntiDepReg];
561 DefIndices[NewReg] = DefIndices[AntiDepReg];
562 KillIndices[NewReg] = KillIndices[AntiDepReg];
564 Classes[AntiDepReg] = 0;
565 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
566 KillIndices[AntiDepReg] = ~0u;
568 RegRefs.erase(AntiDepReg);
570 LastNewReg[AntiDepReg] = NewReg;
577 // Proceding upwards, registers that are defed but not used in this
578 // instruction are now dead.
579 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
580 MachineOperand &MO = MI->getOperand(i);
581 if (!MO.isReg()) continue;
582 unsigned Reg = MO.getReg();
583 if (Reg == 0) continue;
584 if (!MO.isDef()) continue;
585 // Ignore two-addr defs.
586 if (MI->isRegReDefinedByTwoAddr(i)) continue;
588 DefIndices[Reg] = Count;
589 KillIndices[Reg] = ~0u;
592 // Repeat, for all subregs.
593 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
595 unsigned SubregReg = *Subreg;
596 DefIndices[SubregReg] = Count;
597 KillIndices[SubregReg] = ~0u;
598 Classes[SubregReg] = 0;
599 RegRefs.erase(SubregReg);
601 // Conservatively mark super-registers as unusable.
602 for (const unsigned *Super = TRI->getSuperRegisters(Reg);
604 unsigned SuperReg = *Super;
605 Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
608 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
609 MachineOperand &MO = MI->getOperand(i);
610 if (!MO.isReg()) continue;
611 unsigned Reg = MO.getReg();
612 if (Reg == 0) continue;
613 if (!MO.isUse()) continue;
615 const TargetRegisterClass *NewRC =
616 getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
618 // For now, only allow the register to be changed if its register
619 // class is consistent across all uses.
620 if (!Classes[Reg] && NewRC)
621 Classes[Reg] = NewRC;
622 else if (!NewRC || Classes[Reg] != NewRC)
623 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
625 RegRefs.insert(std::make_pair(Reg, &MO));
627 // It wasn't previously live but now it is, this is a kill.
628 if (KillIndices[Reg] == ~0u) {
629 KillIndices[Reg] = Count;
630 DefIndices[Reg] = ~0u;
632 // Repeat, for all aliases.
633 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
634 unsigned AliasReg = *Alias;
635 if (KillIndices[AliasReg] == ~0u) {
636 KillIndices[AliasReg] = Count;
637 DefIndices[AliasReg] = ~0u;
642 assert(Count == ~0u && "Count mismatch!");
647 //===----------------------------------------------------------------------===//
648 // Top-Down Scheduling
649 //===----------------------------------------------------------------------===//
651 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
652 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
653 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
654 SUnit *SuccSU = SuccEdge->getSUnit();
655 --SuccSU->NumPredsLeft;
658 if (SuccSU->NumPredsLeft < 0) {
659 cerr << "*** Scheduling failed! ***\n";
661 cerr << " has been released too many times!\n";
666 // Compute how many cycles it will be before this actually becomes
667 // available. This is the max of the start time of all predecessors plus
669 SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
671 if (SuccSU->NumPredsLeft == 0) {
672 PendingQueue.push_back(SuccSU);
676 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
677 /// count of its successors. If a successor pending count is zero, add it to
678 /// the Available queue.
679 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
680 DOUT << "*** Scheduling [" << CurCycle << "]: ";
681 DEBUG(SU->dump(this));
683 Sequence.push_back(SU);
684 assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
685 SU->setDepthToAtLeast(CurCycle);
687 // Top down: release successors.
688 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
690 ReleaseSucc(SU, &*I);
692 SU->isScheduled = true;
693 AvailableQueue.ScheduledNode(SU);
696 /// ListScheduleTopDown - The main loop of list scheduling for top-down
698 void SchedulePostRATDList::ListScheduleTopDown() {
699 unsigned CurCycle = 0;
701 // All leaves to Available queue.
702 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
703 // It is available if it has no predecessors.
704 if (SUnits[i].Preds.empty()) {
705 AvailableQueue.push(&SUnits[i]);
706 SUnits[i].isAvailable = true;
710 // While Available queue is not empty, grab the node with the highest
711 // priority. If it is not ready put it back. Schedule the node.
712 std::vector<SUnit*> NotReady;
713 Sequence.reserve(SUnits.size());
714 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
715 // Check to see if any of the pending instructions are ready to issue. If
716 // so, add them to the available queue.
717 unsigned MinDepth = ~0u;
718 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
719 if (PendingQueue[i]->getDepth() <= CurCycle) {
720 AvailableQueue.push(PendingQueue[i]);
721 PendingQueue[i]->isAvailable = true;
722 PendingQueue[i] = PendingQueue.back();
723 PendingQueue.pop_back();
725 } else if (PendingQueue[i]->getDepth() < MinDepth)
726 MinDepth = PendingQueue[i]->getDepth();
729 // If there are no instructions available, don't try to issue anything, and
730 // don't advance the hazard recognizer.
731 if (AvailableQueue.empty()) {
732 CurCycle = MinDepth != ~0u ? MinDepth : CurCycle + 1;
736 SUnit *FoundSUnit = 0;
738 bool HasNoopHazards = false;
739 while (!AvailableQueue.empty()) {
740 SUnit *CurSUnit = AvailableQueue.pop();
742 ScheduleHazardRecognizer::HazardType HT =
743 HazardRec->getHazardType(CurSUnit);
744 if (HT == ScheduleHazardRecognizer::NoHazard) {
745 FoundSUnit = CurSUnit;
749 // Remember if this is a noop hazard.
750 HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
752 NotReady.push_back(CurSUnit);
755 // Add the nodes that aren't ready back onto the available list.
756 if (!NotReady.empty()) {
757 AvailableQueue.push_all(NotReady);
761 // If we found a node to schedule, do it now.
763 ScheduleNodeTopDown(FoundSUnit, CurCycle);
764 HazardRec->EmitInstruction(FoundSUnit);
766 // If this is a pseudo-op node, we don't want to increment the current
768 if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
770 } else if (!HasNoopHazards) {
771 // Otherwise, we have a pipeline stall, but no other problem, just advance
772 // the current cycle and try again.
773 DOUT << "*** Advancing cycle, no work to do\n";
774 HazardRec->AdvanceCycle();
778 // Otherwise, we have no instructions to issue and we have instructions
779 // that will fault if we don't do this right. This is the case for
780 // processors without pipeline interlocks and other cases.
781 DOUT << "*** Emitting noop\n";
782 HazardRec->EmitNoop();
783 Sequence.push_back(0); // NULL here means noop
790 VerifySchedule(/*isBottomUp=*/false);
794 //===----------------------------------------------------------------------===//
795 // Public Constructor Functions
796 //===----------------------------------------------------------------------===//
798 FunctionPass *llvm::createPostRAScheduler() {
799 return new PostRAScheduler();