1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "post-RA-sched"
22 #include "AntiDepBreaker.h"
23 #include "AggressiveAntiDepBreaker.h"
24 #include "CriticalAntiDepBreaker.h"
25 #include "RegisterClassInfo.h"
26 #include "ScheduleDAGInstrs.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/CodeGen/LatencyPriorityQueue.h"
29 #include "llvm/CodeGen/SchedulerRegistry.h"
30 #include "llvm/CodeGen/MachineDominators.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetSubtargetInfo.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include "llvm/ADT/BitVector.h"
47 #include "llvm/ADT/Statistic.h"
50 STATISTIC(NumNoops, "Number of noops inserted");
51 STATISTIC(NumStalls, "Number of pipeline stalls");
52 STATISTIC(NumFixedAnti, "Number of fixed anti-dependencies");
54 // Post-RA scheduling is enabled with
55 // TargetSubtargetInfo.enablePostRAScheduler(). This flag can be used to
56 // override the target.
58 EnablePostRAScheduler("post-RA-scheduler",
59 cl::desc("Enable scheduling after register allocation"),
60 cl::init(false), cl::Hidden);
61 static cl::opt<std::string>
62 EnableAntiDepBreaking("break-anti-dependencies",
63 cl::desc("Break post-RA scheduling anti-dependencies: "
64 "\"critical\", \"all\", or \"none\""),
65 cl::init("none"), cl::Hidden);
67 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
69 DebugDiv("postra-sched-debugdiv",
70 cl::desc("Debug control MBBs that are scheduled"),
71 cl::init(0), cl::Hidden);
73 DebugMod("postra-sched-debugmod",
74 cl::desc("Debug control MBBs that are scheduled"),
75 cl::init(0), cl::Hidden);
77 AntiDepBreaker::~AntiDepBreaker() { }
80 class PostRAScheduler : public MachineFunctionPass {
82 const TargetInstrInfo *TII;
83 RegisterClassInfo RegClassInfo;
87 PostRAScheduler() : MachineFunctionPass(ID) {}
89 void getAnalysisUsage(AnalysisUsage &AU) const {
91 AU.addRequired<AliasAnalysis>();
92 AU.addRequired<TargetPassConfig>();
93 AU.addRequired<MachineDominatorTree>();
94 AU.addPreserved<MachineDominatorTree>();
95 AU.addRequired<MachineLoopInfo>();
96 AU.addPreserved<MachineLoopInfo>();
97 MachineFunctionPass::getAnalysisUsage(AU);
100 bool runOnMachineFunction(MachineFunction &Fn);
102 char PostRAScheduler::ID = 0;
104 class SchedulePostRATDList : public ScheduleDAGInstrs {
105 /// AvailableQueue - The priority queue to use for the available SUnits.
107 LatencyPriorityQueue AvailableQueue;
109 /// PendingQueue - This contains all of the instructions whose operands have
110 /// been issued, but their results are not ready yet (due to the latency of
111 /// the operation). Once the operands becomes available, the instruction is
112 /// added to the AvailableQueue.
113 std::vector<SUnit*> PendingQueue;
115 /// Topo - A topological ordering for SUnits.
116 ScheduleDAGTopologicalSort Topo;
118 /// HazardRec - The hazard recognizer to use.
119 ScheduleHazardRecognizer *HazardRec;
121 /// AntiDepBreak - Anti-dependence breaking object, or NULL if none
122 AntiDepBreaker *AntiDepBreak;
124 /// AA - AliasAnalysis for making memory reference queries.
127 /// LiveRegs - true if the register is live.
131 SchedulePostRATDList(
132 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
133 AliasAnalysis *AA, const RegisterClassInfo&,
134 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
135 SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs);
137 ~SchedulePostRATDList();
139 /// StartBlock - Initialize register live-range state for scheduling in
142 void StartBlock(MachineBasicBlock *BB);
144 /// Schedule - Schedule the instruction range using list scheduling.
150 /// Observe - Update liveness information to account for the current
151 /// instruction, which will not be scheduled.
153 void Observe(MachineInstr *MI, unsigned Count);
155 /// FinishBlock - Clean up register live-range state.
159 /// FixupKills - Fix register kill flags that have been made
160 /// invalid due to scheduling
162 void FixupKills(MachineBasicBlock *MBB);
165 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
166 void ReleaseSuccessors(SUnit *SU);
167 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
168 void ListScheduleTopDown();
169 void StartBlockForKills(MachineBasicBlock *BB);
171 // ToggleKillFlag - Toggle a register operand kill flag. Other
172 // adjustments may be made to the instruction if necessary. Return
173 // true if the operand has been deleted, false if not.
174 bool ToggleKillFlag(MachineInstr *MI, MachineOperand &MO);
176 void dumpSchedule() const;
180 char &llvm::PostRASchedulerID = PostRAScheduler::ID;
182 INITIALIZE_PASS(PostRAScheduler, "post-RA-sched",
183 "Post RA top-down list latency scheduler", false, false)
185 SchedulePostRATDList::SchedulePostRATDList(
186 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
187 AliasAnalysis *AA, const RegisterClassInfo &RCI,
188 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
189 SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs)
190 : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), Topo(SUnits), AA(AA),
191 LiveRegs(TRI->getNumRegs())
193 const TargetMachine &TM = MF.getTarget();
194 const InstrItineraryData *InstrItins = TM.getInstrItineraryData();
196 TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins, this);
198 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_ALL) ?
199 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
200 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_CRITICAL) ?
201 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL));
204 SchedulePostRATDList::~SchedulePostRATDList() {
209 /// dumpSchedule - dump the scheduled Sequence.
210 void SchedulePostRATDList::dumpSchedule() const {
211 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
212 if (SUnit *SU = Sequence[i])
215 dbgs() << "**** NOOP ****\n";
219 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
220 TII = Fn.getTarget().getInstrInfo();
221 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
222 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
223 AliasAnalysis *AA = &getAnalysis<AliasAnalysis>();
224 TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
226 RegClassInfo.runOnMachineFunction(Fn);
228 // Check for explicit enable/disable of post-ra scheduling.
229 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode =
230 TargetSubtargetInfo::ANTIDEP_NONE;
231 SmallVector<const TargetRegisterClass*, 4> CriticalPathRCs;
232 if (EnablePostRAScheduler.getPosition() > 0) {
233 if (!EnablePostRAScheduler)
236 // Check that post-RA scheduling is enabled for this target.
237 // This may upgrade the AntiDepMode.
238 const TargetSubtargetInfo &ST = Fn.getTarget().getSubtarget<TargetSubtargetInfo>();
239 if (!ST.enablePostRAScheduler(PassConfig->getOptLevel(), AntiDepMode,
244 // Check for antidep breaking override...
245 if (EnableAntiDepBreaking.getPosition() > 0) {
246 AntiDepMode = (EnableAntiDepBreaking == "all")
247 ? TargetSubtargetInfo::ANTIDEP_ALL
248 : ((EnableAntiDepBreaking == "critical")
249 ? TargetSubtargetInfo::ANTIDEP_CRITICAL
250 : TargetSubtargetInfo::ANTIDEP_NONE);
253 DEBUG(dbgs() << "PostRAScheduler\n");
255 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
258 // Loop over all of the basic blocks
259 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
260 MBB != MBBe; ++MBB) {
262 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
264 static int bbcnt = 0;
265 if (bbcnt++ % DebugDiv != DebugMod)
267 dbgs() << "*** DEBUG scheduling " << Fn.getFunction()->getName()
268 << ":BB#" << MBB->getNumber() << " ***\n";
272 // Initialize register live-range state for scheduling in this block.
273 Scheduler.StartBlock(MBB);
275 // Schedule each sequence of instructions not interrupted by a label
276 // or anything else that effectively needs to shut down scheduling.
277 MachineBasicBlock::iterator Current = MBB->end();
278 unsigned Count = MBB->size(), CurrentCount = Count;
279 for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
280 MachineInstr *MI = llvm::prior(I);
281 // Calls are not scheduling boundaries before register allocation, but
282 // post-ra we don't gain anything by scheduling across calls since we
283 // don't need to worry about register pressure.
284 if (MI->isCall() || TII->isSchedulingBoundary(MI, MBB, Fn)) {
285 Scheduler.Run(MBB, I, Current, CurrentCount);
286 Scheduler.EmitSchedule();
288 CurrentCount = Count - 1;
289 Scheduler.Observe(MI, CurrentCount);
294 Count -= MI->getBundleSize();
296 assert(Count == 0 && "Instruction count mismatch!");
297 assert((MBB->begin() == Current || CurrentCount != 0) &&
298 "Instruction count mismatch!");
299 Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
300 Scheduler.EmitSchedule();
302 // Clean up register live-range state.
303 Scheduler.FinishBlock();
305 // Update register kills
306 Scheduler.FixupKills(MBB);
312 /// StartBlock - Initialize register live-range state for scheduling in
315 void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
316 // Call the superclass.
317 ScheduleDAGInstrs::StartBlock(BB);
319 // Reset the hazard recognizer and anti-dep breaker.
321 if (AntiDepBreak != NULL)
322 AntiDepBreak->StartBlock(BB);
325 /// Schedule - Schedule the instruction range using list scheduling.
327 void SchedulePostRATDList::Schedule() {
328 // Build the scheduling graph.
331 if (AntiDepBreak != NULL) {
333 AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos,
334 InsertPosIndex, DbgValues);
337 // We made changes. Update the dependency graph.
338 // Theoretically we could update the graph in place:
339 // When a live range is changed to use a different register, remove
340 // the def's anti-dependence *and* output-dependence edges due to
341 // that register, and add new anti-dependence and output-dependence
342 // edges based on the next live range of the register.
349 NumFixedAnti += Broken;
353 DEBUG(dbgs() << "********** List Scheduling **********\n");
354 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
355 SUnits[su].dumpAll(this));
357 AvailableQueue.initNodes(SUnits);
358 ListScheduleTopDown();
359 AvailableQueue.releaseState();
362 dbgs() << "*** Final schedule ***\n";
368 /// Observe - Update liveness information to account for the current
369 /// instruction, which will not be scheduled.
371 void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
372 if (AntiDepBreak != NULL)
373 AntiDepBreak->Observe(MI, Count, InsertPosIndex);
376 /// FinishBlock - Clean up register live-range state.
378 void SchedulePostRATDList::FinishBlock() {
379 if (AntiDepBreak != NULL)
380 AntiDepBreak->FinishBlock();
382 // Call the superclass.
383 ScheduleDAGInstrs::FinishBlock();
386 /// StartBlockForKills - Initialize register live-range state for updating kills
388 void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
389 // Start with no live registers.
392 // Determine the live-out physregs for this block.
393 if (!BB->empty() && BB->back().isReturn()) {
394 // In a return block, examine the function live-out regs.
395 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
396 E = MRI.liveout_end(); I != E; ++I) {
399 // Repeat, for all subregs.
400 for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
402 LiveRegs.set(*Subreg);
406 // In a non-return block, examine the live-in regs of all successors.
407 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
408 SE = BB->succ_end(); SI != SE; ++SI) {
409 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
410 E = (*SI)->livein_end(); I != E; ++I) {
413 // Repeat, for all subregs.
414 for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
416 LiveRegs.set(*Subreg);
422 bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
423 MachineOperand &MO) {
424 // Setting kill flag...
430 // If MO itself is live, clear the kill flag...
431 if (LiveRegs.test(MO.getReg())) {
436 // If any subreg of MO is live, then create an imp-def for that
437 // subreg and keep MO marked as killed.
440 const unsigned SuperReg = MO.getReg();
441 for (const uint16_t *Subreg = TRI->getSubRegisters(SuperReg);
443 if (LiveRegs.test(*Subreg)) {
444 MI->addOperand(MachineOperand::CreateReg(*Subreg,
458 /// FixupKills - Fix the register kill flags, they may have been made
459 /// incorrect by instruction reordering.
461 void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
462 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
464 BitVector killedRegs(TRI->getNumRegs());
465 BitVector ReservedRegs = TRI->getReservedRegs(MF);
467 StartBlockForKills(MBB);
469 // Examine block from end to start...
470 unsigned Count = MBB->size();
471 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
473 MachineInstr *MI = --I;
474 if (MI->isDebugValue())
477 // Update liveness. Registers that are defed but not used in this
478 // instruction are now dead. Mark register and all subregs as they
479 // are completely defined.
480 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
481 MachineOperand &MO = MI->getOperand(i);
483 LiveRegs.clearBitsNotInMask(MO.getRegMask());
484 if (!MO.isReg()) continue;
485 unsigned Reg = MO.getReg();
486 if (Reg == 0) continue;
487 if (!MO.isDef()) continue;
488 // Ignore two-addr defs.
489 if (MI->isRegTiedToUseOperand(i)) continue;
493 // Repeat for all subregs.
494 for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
496 LiveRegs.reset(*Subreg);
499 // Examine all used registers and set/clear kill flag. When a
500 // register is used multiple times we only set the kill flag on
503 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
504 MachineOperand &MO = MI->getOperand(i);
505 if (!MO.isReg() || !MO.isUse()) continue;
506 unsigned Reg = MO.getReg();
507 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
510 if (!killedRegs.test(Reg)) {
512 // A register is not killed if any subregs are live...
513 for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
515 if (LiveRegs.test(*Subreg)) {
521 // If subreg is not live, then register is killed if it became
522 // live in this instruction
524 kill = !LiveRegs.test(Reg);
527 if (MO.isKill() != kill) {
528 DEBUG(dbgs() << "Fixing " << MO << " in ");
529 // Warning: ToggleKillFlag may invalidate MO.
530 ToggleKillFlag(MI, MO);
537 // Mark any used register (that is not using undef) and subregs as
539 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
540 MachineOperand &MO = MI->getOperand(i);
541 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
542 unsigned Reg = MO.getReg();
543 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
547 for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
549 LiveRegs.set(*Subreg);
554 //===----------------------------------------------------------------------===//
555 // Top-Down Scheduling
556 //===----------------------------------------------------------------------===//
558 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
559 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
560 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
561 SUnit *SuccSU = SuccEdge->getSUnit();
564 if (SuccSU->NumPredsLeft == 0) {
565 dbgs() << "*** Scheduling failed! ***\n";
567 dbgs() << " has been released too many times!\n";
571 --SuccSU->NumPredsLeft;
573 // Standard scheduler algorithms will recompute the depth of the successor
575 // SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
577 // However, we lazily compute node depth instead. Note that
578 // ScheduleNodeTopDown has already updated the depth of this node which causes
579 // all descendents to be marked dirty. Setting the successor depth explicitly
580 // here would cause depth to be recomputed for all its ancestors. If the
581 // successor is not yet ready (because of a transitively redundant edge) then
582 // this causes depth computation to be quadratic in the size of the DAG.
584 // If all the node's predecessors are scheduled, this node is ready
585 // to be scheduled. Ignore the special ExitSU node.
586 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
587 PendingQueue.push_back(SuccSU);
590 /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
591 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
592 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
594 ReleaseSucc(SU, &*I);
598 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
599 /// count of its successors. If a successor pending count is zero, add it to
600 /// the Available queue.
601 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
602 DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
603 DEBUG(SU->dump(this));
605 Sequence.push_back(SU);
606 assert(CurCycle >= SU->getDepth() &&
607 "Node scheduled above its depth!");
608 SU->setDepthToAtLeast(CurCycle);
610 ReleaseSuccessors(SU);
611 SU->isScheduled = true;
612 AvailableQueue.ScheduledNode(SU);
615 /// ListScheduleTopDown - The main loop of list scheduling for top-down
617 void SchedulePostRATDList::ListScheduleTopDown() {
618 unsigned CurCycle = 0;
620 // We're scheduling top-down but we're visiting the regions in
621 // bottom-up order, so we don't know the hazards at the start of a
622 // region. So assume no hazards (this should usually be ok as most
623 // blocks are a single region).
626 // Release any successors of the special Entry node.
627 ReleaseSuccessors(&EntrySU);
629 // Add all leaves to Available queue.
630 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
631 // It is available if it has no predecessors.
632 bool available = SUnits[i].Preds.empty();
634 AvailableQueue.push(&SUnits[i]);
635 SUnits[i].isAvailable = true;
639 // In any cycle where we can't schedule any instructions, we must
640 // stall or emit a noop, depending on the target.
641 bool CycleHasInsts = false;
643 // While Available queue is not empty, grab the node with the highest
644 // priority. If it is not ready put it back. Schedule the node.
645 std::vector<SUnit*> NotReady;
646 Sequence.reserve(SUnits.size());
647 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
648 // Check to see if any of the pending instructions are ready to issue. If
649 // so, add them to the available queue.
650 unsigned MinDepth = ~0u;
651 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
652 if (PendingQueue[i]->getDepth() <= CurCycle) {
653 AvailableQueue.push(PendingQueue[i]);
654 PendingQueue[i]->isAvailable = true;
655 PendingQueue[i] = PendingQueue.back();
656 PendingQueue.pop_back();
658 } else if (PendingQueue[i]->getDepth() < MinDepth)
659 MinDepth = PendingQueue[i]->getDepth();
662 DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this));
664 SUnit *FoundSUnit = 0;
665 bool HasNoopHazards = false;
666 while (!AvailableQueue.empty()) {
667 SUnit *CurSUnit = AvailableQueue.pop();
669 ScheduleHazardRecognizer::HazardType HT =
670 HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
671 if (HT == ScheduleHazardRecognizer::NoHazard) {
672 FoundSUnit = CurSUnit;
676 // Remember if this is a noop hazard.
677 HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
679 NotReady.push_back(CurSUnit);
682 // Add the nodes that aren't ready back onto the available list.
683 if (!NotReady.empty()) {
684 AvailableQueue.push_all(NotReady);
688 // If we found a node to schedule...
690 // ... schedule the node...
691 ScheduleNodeTopDown(FoundSUnit, CurCycle);
692 HazardRec->EmitInstruction(FoundSUnit);
693 CycleHasInsts = true;
694 if (HazardRec->atIssueLimit()) {
695 DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n');
696 HazardRec->AdvanceCycle();
698 CycleHasInsts = false;
702 DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
703 HazardRec->AdvanceCycle();
704 } else if (!HasNoopHazards) {
705 // Otherwise, we have a pipeline stall, but no other problem,
706 // just advance the current cycle and try again.
707 DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n');
708 HazardRec->AdvanceCycle();
711 // Otherwise, we have no instructions to issue and we have instructions
712 // that will fault if we don't do this right. This is the case for
713 // processors without pipeline interlocks and other cases.
714 DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n');
715 HazardRec->EmitNoop();
716 Sequence.push_back(0); // NULL here means noop
721 CycleHasInsts = false;
726 unsigned ScheduledNodes = VerifyScheduledDAG(/*isBottomUp=*/false);
728 for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
731 assert(Sequence.size() - Noops == ScheduledNodes &&
732 "The number of nodes scheduled doesn't match the expected number!");
736 // EmitSchedule - Emit the machine code in scheduled order.
737 void SchedulePostRATDList::EmitSchedule() {
740 // If first instruction was a DBG_VALUE then put it back.
742 BB->splice(InsertPos, BB, FirstDbgValue);
744 // Then re-insert them according to the given schedule.
745 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
746 if (SUnit *SU = Sequence[i])
747 BB->splice(InsertPos, BB, SU->getInstr());
749 // Null SUnit* is a noop.
750 TII->insertNoop(*BB, InsertPos);
752 // Update the Begin iterator, as the first instruction in the block
753 // may have been scheduled later.
755 Begin = prior(InsertPos);
758 // Reinsert any remaining debug_values.
759 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
760 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
761 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
762 MachineInstr *DbgValue = P.first;
763 MachineBasicBlock::iterator OrigPrivMI = P.second;
764 BB->splice(++OrigPrivMI, BB, DbgValue);
767 FirstDbgValue = NULL;