1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "post-RA-sched"
22 #include "AntiDepBreaker.h"
23 #include "AggressiveAntiDepBreaker.h"
24 #include "CriticalAntiDepBreaker.h"
25 #include "RegisterClassInfo.h"
26 #include "ScheduleDAGInstrs.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/CodeGen/LatencyPriorityQueue.h"
29 #include "llvm/CodeGen/SchedulerRegistry.h"
30 #include "llvm/CodeGen/MachineDominators.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetSubtarget.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include "llvm/ADT/BitVector.h"
47 #include "llvm/ADT/Statistic.h"
51 STATISTIC(NumNoops, "Number of noops inserted");
52 STATISTIC(NumStalls, "Number of pipeline stalls");
53 STATISTIC(NumFixedAnti, "Number of fixed anti-dependencies");
55 // Post-RA scheduling is enabled with
56 // TargetSubtarget.enablePostRAScheduler(). This flag can be used to
57 // override the target.
59 EnablePostRAScheduler("post-RA-scheduler",
60 cl::desc("Enable scheduling after register allocation"),
61 cl::init(false), cl::Hidden);
62 static cl::opt<std::string>
63 EnableAntiDepBreaking("break-anti-dependencies",
64 cl::desc("Break post-RA scheduling anti-dependencies: "
65 "\"critical\", \"all\", or \"none\""),
66 cl::init("none"), cl::Hidden);
68 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
70 DebugDiv("postra-sched-debugdiv",
71 cl::desc("Debug control MBBs that are scheduled"),
72 cl::init(0), cl::Hidden);
74 DebugMod("postra-sched-debugmod",
75 cl::desc("Debug control MBBs that are scheduled"),
76 cl::init(0), cl::Hidden);
78 AntiDepBreaker::~AntiDepBreaker() { }
81 class PostRAScheduler : public MachineFunctionPass {
83 const TargetInstrInfo *TII;
84 RegisterClassInfo RegClassInfo;
85 CodeGenOpt::Level OptLevel;
89 PostRAScheduler(CodeGenOpt::Level ol) :
90 MachineFunctionPass(ID), OptLevel(ol) {}
92 void getAnalysisUsage(AnalysisUsage &AU) const {
94 AU.addRequired<AliasAnalysis>();
95 AU.addRequired<MachineDominatorTree>();
96 AU.addPreserved<MachineDominatorTree>();
97 AU.addRequired<MachineLoopInfo>();
98 AU.addPreserved<MachineLoopInfo>();
99 MachineFunctionPass::getAnalysisUsage(AU);
102 const char *getPassName() const {
103 return "Post RA top-down list latency scheduler";
106 bool runOnMachineFunction(MachineFunction &Fn);
108 char PostRAScheduler::ID = 0;
110 class SchedulePostRATDList : public ScheduleDAGInstrs {
111 /// AvailableQueue - The priority queue to use for the available SUnits.
113 LatencyPriorityQueue AvailableQueue;
115 /// PendingQueue - This contains all of the instructions whose operands have
116 /// been issued, but their results are not ready yet (due to the latency of
117 /// the operation). Once the operands becomes available, the instruction is
118 /// added to the AvailableQueue.
119 std::vector<SUnit*> PendingQueue;
121 /// Topo - A topological ordering for SUnits.
122 ScheduleDAGTopologicalSort Topo;
124 /// HazardRec - The hazard recognizer to use.
125 ScheduleHazardRecognizer *HazardRec;
127 /// AntiDepBreak - Anti-dependence breaking object, or NULL if none
128 AntiDepBreaker *AntiDepBreak;
130 /// AA - AliasAnalysis for making memory reference queries.
133 /// KillIndices - The index of the most recent kill (proceding bottom-up),
134 /// or ~0u if the register is not live.
135 std::vector<unsigned> KillIndices;
138 SchedulePostRATDList(
139 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
140 AliasAnalysis *AA, const RegisterClassInfo&,
141 TargetSubtarget::AntiDepBreakMode AntiDepMode,
142 SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs);
144 ~SchedulePostRATDList();
146 /// StartBlock - Initialize register live-range state for scheduling in
149 void StartBlock(MachineBasicBlock *BB);
151 /// Schedule - Schedule the instruction range using list scheduling.
155 /// Observe - Update liveness information to account for the current
156 /// instruction, which will not be scheduled.
158 void Observe(MachineInstr *MI, unsigned Count);
160 /// FinishBlock - Clean up register live-range state.
164 /// FixupKills - Fix register kill flags that have been made
165 /// invalid due to scheduling
167 void FixupKills(MachineBasicBlock *MBB);
170 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
171 void ReleaseSuccessors(SUnit *SU);
172 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
173 void ListScheduleTopDown();
174 void StartBlockForKills(MachineBasicBlock *BB);
176 // ToggleKillFlag - Toggle a register operand kill flag. Other
177 // adjustments may be made to the instruction if necessary. Return
178 // true if the operand has been deleted, false if not.
179 bool ToggleKillFlag(MachineInstr *MI, MachineOperand &MO);
183 SchedulePostRATDList::SchedulePostRATDList(
184 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
185 AliasAnalysis *AA, const RegisterClassInfo &RCI,
186 TargetSubtarget::AntiDepBreakMode AntiDepMode,
187 SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs)
188 : ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits), AA(AA),
189 KillIndices(TRI->getNumRegs())
191 const TargetMachine &TM = MF.getTarget();
192 const InstrItineraryData *InstrItins = TM.getInstrItineraryData();
194 TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins, this);
196 ((AntiDepMode == TargetSubtarget::ANTIDEP_ALL) ?
197 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
198 ((AntiDepMode == TargetSubtarget::ANTIDEP_CRITICAL) ?
199 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL));
202 SchedulePostRATDList::~SchedulePostRATDList() {
207 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
208 TII = Fn.getTarget().getInstrInfo();
209 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
210 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
211 AliasAnalysis *AA = &getAnalysis<AliasAnalysis>();
212 RegClassInfo.runOnMachineFunction(Fn);
214 // Check for explicit enable/disable of post-ra scheduling.
215 TargetSubtarget::AntiDepBreakMode AntiDepMode = TargetSubtarget::ANTIDEP_NONE;
216 SmallVector<TargetRegisterClass*, 4> CriticalPathRCs;
217 if (EnablePostRAScheduler.getPosition() > 0) {
218 if (!EnablePostRAScheduler)
221 // Check that post-RA scheduling is enabled for this target.
222 // This may upgrade the AntiDepMode.
223 const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
224 if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode, CriticalPathRCs))
228 // Check for antidep breaking override...
229 if (EnableAntiDepBreaking.getPosition() > 0) {
230 AntiDepMode = (EnableAntiDepBreaking == "all") ?
231 TargetSubtarget::ANTIDEP_ALL :
232 (EnableAntiDepBreaking == "critical")
233 ? TargetSubtarget::ANTIDEP_CRITICAL : TargetSubtarget::ANTIDEP_NONE;
236 DEBUG(dbgs() << "PostRAScheduler\n");
238 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
241 // Loop over all of the basic blocks
242 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
243 MBB != MBBe; ++MBB) {
245 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
247 static int bbcnt = 0;
248 if (bbcnt++ % DebugDiv != DebugMod)
250 dbgs() << "*** DEBUG scheduling " << Fn.getFunction()->getNameStr() <<
251 ":BB#" << MBB->getNumber() << " ***\n";
255 // Initialize register live-range state for scheduling in this block.
256 Scheduler.StartBlock(MBB);
258 // Schedule each sequence of instructions not interrupted by a label
259 // or anything else that effectively needs to shut down scheduling.
260 MachineBasicBlock::iterator Current = MBB->end();
261 unsigned Count = MBB->size(), CurrentCount = Count;
262 for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
263 MachineInstr *MI = llvm::prior(I);
264 if (TII->isSchedulingBoundary(MI, MBB, Fn)) {
265 Scheduler.Run(MBB, I, Current, CurrentCount);
266 Scheduler.EmitSchedule();
268 CurrentCount = Count - 1;
269 Scheduler.Observe(MI, CurrentCount);
274 assert(Count == 0 && "Instruction count mismatch!");
275 assert((MBB->begin() == Current || CurrentCount != 0) &&
276 "Instruction count mismatch!");
277 Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
278 Scheduler.EmitSchedule();
280 // Clean up register live-range state.
281 Scheduler.FinishBlock();
283 // Update register kills
284 Scheduler.FixupKills(MBB);
290 /// StartBlock - Initialize register live-range state for scheduling in
293 void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
294 // Call the superclass.
295 ScheduleDAGInstrs::StartBlock(BB);
297 // Reset the hazard recognizer and anti-dep breaker.
299 if (AntiDepBreak != NULL)
300 AntiDepBreak->StartBlock(BB);
303 /// Schedule - Schedule the instruction range using list scheduling.
305 void SchedulePostRATDList::Schedule() {
306 // Build the scheduling graph.
309 if (AntiDepBreak != NULL) {
311 AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos,
312 InsertPosIndex, DbgValues);
315 // We made changes. Update the dependency graph.
316 // Theoretically we could update the graph in place:
317 // When a live range is changed to use a different register, remove
318 // the def's anti-dependence *and* output-dependence edges due to
319 // that register, and add new anti-dependence and output-dependence
320 // edges based on the next live range of the register.
327 NumFixedAnti += Broken;
331 DEBUG(dbgs() << "********** List Scheduling **********\n");
332 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
333 SUnits[su].dumpAll(this));
335 AvailableQueue.initNodes(SUnits);
336 ListScheduleTopDown();
337 AvailableQueue.releaseState();
340 /// Observe - Update liveness information to account for the current
341 /// instruction, which will not be scheduled.
343 void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
344 if (AntiDepBreak != NULL)
345 AntiDepBreak->Observe(MI, Count, InsertPosIndex);
348 /// FinishBlock - Clean up register live-range state.
350 void SchedulePostRATDList::FinishBlock() {
351 if (AntiDepBreak != NULL)
352 AntiDepBreak->FinishBlock();
354 // Call the superclass.
355 ScheduleDAGInstrs::FinishBlock();
358 /// StartBlockForKills - Initialize register live-range state for updating kills
360 void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
361 // Initialize the indices to indicate that no registers are live.
362 for (unsigned i = 0; i < TRI->getNumRegs(); ++i)
363 KillIndices[i] = ~0u;
365 // Determine the live-out physregs for this block.
366 if (!BB->empty() && BB->back().getDesc().isReturn()) {
367 // In a return block, examine the function live-out regs.
368 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
369 E = MRI.liveout_end(); I != E; ++I) {
371 KillIndices[Reg] = BB->size();
372 // Repeat, for all subregs.
373 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
375 KillIndices[*Subreg] = BB->size();
380 // In a non-return block, examine the live-in regs of all successors.
381 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
382 SE = BB->succ_end(); SI != SE; ++SI) {
383 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
384 E = (*SI)->livein_end(); I != E; ++I) {
386 KillIndices[Reg] = BB->size();
387 // Repeat, for all subregs.
388 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
390 KillIndices[*Subreg] = BB->size();
397 bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
398 MachineOperand &MO) {
399 // Setting kill flag...
405 // If MO itself is live, clear the kill flag...
406 if (KillIndices[MO.getReg()] != ~0u) {
411 // If any subreg of MO is live, then create an imp-def for that
412 // subreg and keep MO marked as killed.
415 const unsigned SuperReg = MO.getReg();
416 for (const unsigned *Subreg = TRI->getSubRegisters(SuperReg);
418 if (KillIndices[*Subreg] != ~0u) {
419 MI->addOperand(MachineOperand::CreateReg(*Subreg,
433 /// FixupKills - Fix the register kill flags, they may have been made
434 /// incorrect by instruction reordering.
436 void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
437 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
439 std::set<unsigned> killedRegs;
440 BitVector ReservedRegs = TRI->getReservedRegs(MF);
442 StartBlockForKills(MBB);
444 // Examine block from end to start...
445 unsigned Count = MBB->size();
446 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
448 MachineInstr *MI = --I;
449 if (MI->isDebugValue())
452 // Update liveness. Registers that are defed but not used in this
453 // instruction are now dead. Mark register and all subregs as they
454 // are completely defined.
455 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
456 MachineOperand &MO = MI->getOperand(i);
457 if (!MO.isReg()) continue;
458 unsigned Reg = MO.getReg();
459 if (Reg == 0) continue;
460 if (!MO.isDef()) continue;
461 // Ignore two-addr defs.
462 if (MI->isRegTiedToUseOperand(i)) continue;
464 KillIndices[Reg] = ~0u;
466 // Repeat for all subregs.
467 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
469 KillIndices[*Subreg] = ~0u;
473 // Examine all used registers and set/clear kill flag. When a
474 // register is used multiple times we only set the kill flag on
477 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
478 MachineOperand &MO = MI->getOperand(i);
479 if (!MO.isReg() || !MO.isUse()) continue;
480 unsigned Reg = MO.getReg();
481 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
484 if (killedRegs.find(Reg) == killedRegs.end()) {
486 // A register is not killed if any subregs are live...
487 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
489 if (KillIndices[*Subreg] != ~0u) {
495 // If subreg is not live, then register is killed if it became
496 // live in this instruction
498 kill = (KillIndices[Reg] == ~0u);
501 if (MO.isKill() != kill) {
502 DEBUG(dbgs() << "Fixing " << MO << " in ");
503 // Warning: ToggleKillFlag may invalidate MO.
504 ToggleKillFlag(MI, MO);
508 killedRegs.insert(Reg);
511 // Mark any used register (that is not using undef) and subregs as
513 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
514 MachineOperand &MO = MI->getOperand(i);
515 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
516 unsigned Reg = MO.getReg();
517 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
519 KillIndices[Reg] = Count;
521 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
523 KillIndices[*Subreg] = Count;
529 //===----------------------------------------------------------------------===//
530 // Top-Down Scheduling
531 //===----------------------------------------------------------------------===//
533 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
534 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
535 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
536 SUnit *SuccSU = SuccEdge->getSUnit();
539 if (SuccSU->NumPredsLeft == 0) {
540 dbgs() << "*** Scheduling failed! ***\n";
542 dbgs() << " has been released too many times!\n";
546 --SuccSU->NumPredsLeft;
548 // Standard scheduler algorithms will recompute the depth of the successor
550 // SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
552 // However, we lazily compute node depth instead. Note that
553 // ScheduleNodeTopDown has already updated the depth of this node which causes
554 // all descendents to be marked dirty. Setting the successor depth explicitly
555 // here would cause depth to be recomputed for all its ancestors. If the
556 // successor is not yet ready (because of a transitively redundant edge) then
557 // this causes depth computation to be quadratic in the size of the DAG.
559 // If all the node's predecessors are scheduled, this node is ready
560 // to be scheduled. Ignore the special ExitSU node.
561 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
562 PendingQueue.push_back(SuccSU);
565 /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
566 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
567 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
569 ReleaseSucc(SU, &*I);
573 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
574 /// count of its successors. If a successor pending count is zero, add it to
575 /// the Available queue.
576 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
577 DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
578 DEBUG(SU->dump(this));
580 Sequence.push_back(SU);
581 assert(CurCycle >= SU->getDepth() &&
582 "Node scheduled above its depth!");
583 SU->setDepthToAtLeast(CurCycle);
585 ReleaseSuccessors(SU);
586 SU->isScheduled = true;
587 AvailableQueue.ScheduledNode(SU);
590 /// ListScheduleTopDown - The main loop of list scheduling for top-down
592 void SchedulePostRATDList::ListScheduleTopDown() {
593 unsigned CurCycle = 0;
595 // We're scheduling top-down but we're visiting the regions in
596 // bottom-up order, so we don't know the hazards at the start of a
597 // region. So assume no hazards (this should usually be ok as most
598 // blocks are a single region).
601 // Release any successors of the special Entry node.
602 ReleaseSuccessors(&EntrySU);
604 // Add all leaves to Available queue.
605 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
606 // It is available if it has no predecessors.
607 bool available = SUnits[i].Preds.empty();
609 AvailableQueue.push(&SUnits[i]);
610 SUnits[i].isAvailable = true;
614 // In any cycle where we can't schedule any instructions, we must
615 // stall or emit a noop, depending on the target.
616 bool CycleHasInsts = false;
618 // While Available queue is not empty, grab the node with the highest
619 // priority. If it is not ready put it back. Schedule the node.
620 std::vector<SUnit*> NotReady;
621 Sequence.reserve(SUnits.size());
622 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
623 // Check to see if any of the pending instructions are ready to issue. If
624 // so, add them to the available queue.
625 unsigned MinDepth = ~0u;
626 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
627 if (PendingQueue[i]->getDepth() <= CurCycle) {
628 AvailableQueue.push(PendingQueue[i]);
629 PendingQueue[i]->isAvailable = true;
630 PendingQueue[i] = PendingQueue.back();
631 PendingQueue.pop_back();
633 } else if (PendingQueue[i]->getDepth() < MinDepth)
634 MinDepth = PendingQueue[i]->getDepth();
637 DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this));
639 SUnit *FoundSUnit = 0;
640 bool HasNoopHazards = false;
641 while (!AvailableQueue.empty()) {
642 SUnit *CurSUnit = AvailableQueue.pop();
644 ScheduleHazardRecognizer::HazardType HT =
645 HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
646 if (HT == ScheduleHazardRecognizer::NoHazard) {
647 FoundSUnit = CurSUnit;
651 // Remember if this is a noop hazard.
652 HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
654 NotReady.push_back(CurSUnit);
657 // Add the nodes that aren't ready back onto the available list.
658 if (!NotReady.empty()) {
659 AvailableQueue.push_all(NotReady);
663 // If we found a node to schedule...
665 // ... schedule the node...
666 ScheduleNodeTopDown(FoundSUnit, CurCycle);
667 HazardRec->EmitInstruction(FoundSUnit);
668 CycleHasInsts = true;
669 if (HazardRec->atIssueLimit()) {
670 DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n');
671 HazardRec->AdvanceCycle();
673 CycleHasInsts = false;
677 DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
678 HazardRec->AdvanceCycle();
679 } else if (!HasNoopHazards) {
680 // Otherwise, we have a pipeline stall, but no other problem,
681 // just advance the current cycle and try again.
682 DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n');
683 HazardRec->AdvanceCycle();
686 // Otherwise, we have no instructions to issue and we have instructions
687 // that will fault if we don't do this right. This is the case for
688 // processors without pipeline interlocks and other cases.
689 DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n');
690 HazardRec->EmitNoop();
691 Sequence.push_back(0); // NULL here means noop
696 CycleHasInsts = false;
701 VerifySchedule(/*isBottomUp=*/false);
705 //===----------------------------------------------------------------------===//
706 // Public Constructor Functions
707 //===----------------------------------------------------------------------===//
709 FunctionPass *llvm::createPostRAScheduler(CodeGenOpt::Level OptLevel) {
710 return new PostRAScheduler(OptLevel);