1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "post-RA-sched"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
24 #include "llvm/CodeGen/LatencyPriorityQueue.h"
25 #include "llvm/CodeGen/SchedulerRegistry.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/ADT/DenseSet.h"
34 #include "llvm/ADT/SmallVector.h"
39 STATISTIC(NumStalls, "Number of pipeline stalls");
42 EnableAntiDepBreaking("break-anti-dependencies",
43 cl::desc("Break scheduling anti-dependencies"),
47 class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
50 PostRAScheduler() : MachineFunctionPass(&ID) {}
52 const char *getPassName() const {
53 return "Post RA top-down list latency scheduler";
56 bool runOnMachineFunction(MachineFunction &Fn);
58 char PostRAScheduler::ID = 0;
60 class VISIBILITY_HIDDEN SchedulePostRATDList : public ScheduleDAGInstrs {
61 /// AvailableQueue - The priority queue to use for the available SUnits.
63 LatencyPriorityQueue AvailableQueue;
65 /// PendingQueue - This contains all of the instructions whose operands have
66 /// been issued, but their results are not ready yet (due to the latency of
67 /// the operation). Once the operands becomes available, the instruction is
68 /// added to the AvailableQueue.
69 std::vector<SUnit*> PendingQueue;
71 /// Topo - A topological ordering for SUnits.
72 ScheduleDAGTopologicalSort Topo;
75 SchedulePostRATDList(MachineBasicBlock *mbb, const TargetMachine &tm)
76 : ScheduleDAGInstrs(mbb, tm), Topo(SUnits) {}
81 void ReleaseSucc(SUnit *SU, SUnit *SuccSU, bool isChain);
82 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
83 void ListScheduleTopDown();
84 bool BreakAntiDependencies();
88 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
89 DOUT << "PostRAScheduler\n";
91 // Loop over all of the basic blocks
92 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
95 SchedulePostRATDList Scheduler(MBB, Fn.getTarget());
99 Scheduler.EmitSchedule();
105 /// Schedule - Schedule the DAG using list scheduling.
106 void SchedulePostRATDList::Schedule() {
107 DOUT << "********** List Scheduling **********\n";
109 // Build scheduling units.
112 if (EnableAntiDepBreaking) {
113 if (BreakAntiDependencies()) {
114 // We made changes. Update the dependency graph.
115 // Theoretically we could update the graph in place:
116 // When a live range is changed to use a different register, remove
117 // the def's anti-dependence *and* output-dependence edges due to
118 // that register, and add new anti-dependence and output-dependence
119 // edges based on the next live range of the register.
125 AvailableQueue.initNodes(SUnits);
127 ListScheduleTopDown();
129 AvailableQueue.releaseState();
132 /// getInstrOperandRegClass - Return register class of the operand of an
133 /// instruction of the specified TargetInstrDesc.
134 static const TargetRegisterClass*
135 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
136 const TargetInstrInfo *TII, const TargetInstrDesc &II,
138 if (Op >= II.getNumOperands())
140 if (II.OpInfo[Op].isLookupPtrRegClass())
141 return TII->getPointerRegClass();
142 return TRI->getRegClass(II.OpInfo[Op].RegClass);
145 /// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
146 /// of the ScheduleDAG and break them by renaming registers.
148 bool SchedulePostRATDList::BreakAntiDependencies() {
149 // The code below assumes that there is at least one instruction,
150 // so just duck out immediately if the block is empty.
151 if (BB->empty()) return false;
153 Topo.InitDAGTopologicalSorting();
155 // Compute a critical path for the DAG.
157 std::vector<SDep *> CriticalPath(SUnits.size());
158 for (ScheduleDAGTopologicalSort::const_iterator I = Topo.begin(),
159 E = Topo.end(); I != E; ++I) {
160 SUnit *SU = &SUnits[*I];
161 for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
163 SUnit *PredSU = P->Dep;
164 // This assumes that there's no delay for reusing registers.
165 unsigned PredLatency = (P->isCtrl && P->Reg != 0) ? 1 : PredSU->Latency;
166 unsigned PredTotalLatency = PredSU->CycleBound + PredLatency;
167 if (SU->CycleBound < PredTotalLatency ||
168 (SU->CycleBound == PredTotalLatency && !P->isAntiDep)) {
169 SU->CycleBound = PredTotalLatency;
170 CriticalPath[*I] = &*P;
173 // Keep track of the node at the end of the critical path.
174 if (!Max || SU->CycleBound + SU->Latency > Max->CycleBound + Max->Latency)
178 DOUT << "Critical path has total latency "
179 << (Max ? Max->CycleBound + Max->Latency : 0) << "\n";
181 // Walk the critical path from the bottom up. Collect all anti-dependence
182 // edges on the critical path. Skip anti-dependencies between SUnits that
183 // are connected with other edges, since such units won't be able to be
184 // scheduled past each other anyway.
186 // The heuristic is that edges on the critical path are more important to
187 // break than other edges. And since there are a limited number of
188 // registers, we don't want to waste them breaking edges that aren't
191 // TODO: Instructions with multiple defs could have multiple
192 // anti-dependencies. The current code here only knows how to break one
193 // edge per instruction. Note that we'd have to be able to break all of
194 // the anti-dependencies in an instruction in order to be effective.
195 BitVector AllocatableSet = TRI->getAllocatableSet(*MF);
196 DenseMap<MachineInstr *, unsigned> CriticalAntiDeps;
197 for (SUnit *SU = Max; CriticalPath[SU->NodeNum];
198 SU = CriticalPath[SU->NodeNum]->Dep) {
199 SDep *Edge = CriticalPath[SU->NodeNum];
200 SUnit *NextSU = Edge->Dep;
201 unsigned AntiDepReg = Edge->Reg;
202 // Only consider anti-dependence edges.
203 if (!Edge->isAntiDep)
205 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
206 // Don't break anti-dependencies on non-allocatable registers.
207 if (!AllocatableSet.test(AntiDepReg))
209 // If the SUnit has other dependencies on the SUnit that it
210 // anti-depends on, don't bother breaking the anti-dependency.
211 // Also, if there are dependencies on other SUnits with the
212 // same register as the anti-dependency, don't attempt to
214 for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
216 if (P->Dep == NextSU ?
217 (!P->isAntiDep || P->Reg != AntiDepReg) :
218 (!P->isCtrl && !P->isAntiDep && P->Reg == AntiDepReg)) {
223 CriticalAntiDeps[SU->getInstr()] = AntiDepReg;
226 // For live regs that are only used in one register class in a live range,
227 // the register class. If the register is not live, the corresponding value
228 // is null. If the register is live but used in multiple register classes,
229 // the corresponding value is -1 casted to a pointer.
230 const TargetRegisterClass *
231 Classes[TargetRegisterInfo::FirstVirtualRegister] = {};
233 // Map registers to all their references within a live range.
234 std::multimap<unsigned, MachineOperand *> RegRefs;
236 // The index of the most recent kill (proceding bottom-up), or -1 if
237 // the register is not live.
238 unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
239 std::fill(KillIndices, array_endof(KillIndices), -1);
240 // The index of the most recent def (proceding bottom up), or -1 if
241 // the register is live.
242 unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
243 std::fill(DefIndices, array_endof(DefIndices), BB->size());
245 // Determine the live-out physregs for this block.
246 if (!BB->empty() && BB->back().getDesc().isReturn())
247 // In a return block, examine the function live-out regs.
248 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
249 E = MRI.liveout_end(); I != E; ++I) {
251 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
252 KillIndices[Reg] = BB->size();
253 DefIndices[Reg] = -1;
254 // Repeat, for all aliases.
255 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
256 unsigned AliasReg = *Alias;
257 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
258 KillIndices[AliasReg] = BB->size();
259 DefIndices[AliasReg] = -1;
263 // In a non-return block, examine the live-in regs of all successors.
264 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
265 SE = BB->succ_end(); SI != SE; ++SI)
266 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
267 E = (*SI)->livein_end(); I != E; ++I) {
269 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
270 KillIndices[Reg] = BB->size();
271 DefIndices[Reg] = -1;
272 // Repeat, for all aliases.
273 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
274 unsigned AliasReg = *Alias;
275 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
276 KillIndices[AliasReg] = BB->size();
277 DefIndices[AliasReg] = -1;
281 // Consider callee-saved registers as live-out, since we're running after
282 // prologue/epilogue insertion so there's no way to add additional
285 // TODO: If the callee saves and restores these, then we can potentially
286 // use them between the save and the restore. To do that, we could scan
287 // the exit blocks to see which of these registers are defined.
288 // Alternatively, calle-saved registers that aren't saved and restored
289 // could be marked live-in in every block.
290 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
292 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
293 KillIndices[Reg] = BB->size();
294 DefIndices[Reg] = -1;
295 // Repeat, for all aliases.
296 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
297 unsigned AliasReg = *Alias;
298 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
299 KillIndices[AliasReg] = BB->size();
300 DefIndices[AliasReg] = -1;
304 // Consider this pattern:
313 // There are three anti-dependencies here, and without special care,
314 // we'd break all of them using the same register:
323 // because at each anti-dependence, B is the first register that
324 // isn't A which is free. This re-introduces anti-dependencies
325 // at all but one of the original anti-dependencies that we were
326 // trying to break. To avoid this, keep track of the most recent
327 // register that each register was replaced with, avoid avoid
328 // using it to repair an anti-dependence on the same register.
329 // This lets us produce this:
338 // This still has an anti-dependence on B, but at least it isn't on the
339 // original critical path.
341 // TODO: If we tracked more than one register here, we could potentially
342 // fix that remaining critical edge too. This is a little more involved,
343 // because unlike the most recent register, less recent registers should
344 // still be considered, though only if no other registers are available.
345 unsigned LastNewReg[TargetRegisterInfo::FirstVirtualRegister] = {};
347 // Attempt to break anti-dependence edges on the critical path. Walk the
348 // instructions from the bottom up, tracking information about liveness
349 // as we go to help determine which registers are available.
350 bool Changed = false;
351 unsigned Count = BB->size() - 1;
352 for (MachineBasicBlock::reverse_iterator I = BB->rbegin(), E = BB->rend();
353 I != E; ++I, --Count) {
354 MachineInstr *MI = &*I;
356 // Check if this instruction has an anti-dependence that we're
358 DenseMap<MachineInstr *, unsigned>::iterator C = CriticalAntiDeps.find(MI);
359 unsigned AntiDepReg = C != CriticalAntiDeps.end() ?
362 // Scan the register operands for this instruction and update
363 // Classes and RegRefs.
364 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
365 MachineOperand &MO = MI->getOperand(i);
366 if (!MO.isReg()) continue;
367 unsigned Reg = MO.getReg();
368 if (Reg == 0) continue;
369 const TargetRegisterClass *NewRC =
370 getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
372 // If this instruction has a use of AntiDepReg, breaking it
374 if (MO.isUse() && AntiDepReg == Reg)
377 // For now, only allow the register to be changed if its register
378 // class is consistent across all uses.
379 if (!Classes[Reg] && NewRC)
380 Classes[Reg] = NewRC;
381 else if (!NewRC || Classes[Reg] != NewRC)
382 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
384 // Now check for aliases.
385 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
386 // If an alias of the reg is used during the live range, give up.
387 // Note that this allows us to skip checking if AntiDepReg
388 // overlaps with any of the aliases, among other things.
389 unsigned AliasReg = *Alias;
390 if (Classes[AliasReg]) {
391 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
392 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
396 // If we're still willing to consider this register, note the reference.
397 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
398 RegRefs.insert(std::make_pair(Reg, &MO));
401 // Determine AntiDepReg's register class, if it is live and is
402 // consistently used within a single class.
403 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
404 assert((AntiDepReg == 0 || RC != NULL) &&
405 "Register should be live if it's causing an anti-dependence!");
406 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
409 // Look for a suitable register to use to break the anti-depenence.
411 // TODO: Instead of picking the first free register, consider which might
413 if (AntiDepReg != 0) {
414 for (TargetRegisterClass::iterator R = RC->allocation_order_begin(*MF),
415 RE = RC->allocation_order_end(*MF); R != RE; ++R) {
416 unsigned NewReg = *R;
417 // Don't replace a register with itself.
418 if (NewReg == AntiDepReg) continue;
419 // Don't replace a register with one that was recently used to repair
420 // an anti-dependence with this AntiDepReg, because that would
421 // re-introduce that anti-dependence.
422 if (NewReg == LastNewReg[AntiDepReg]) continue;
423 // If NewReg is dead and NewReg's most recent def is not before
424 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
425 assert(((KillIndices[AntiDepReg] == -1u) != (DefIndices[AntiDepReg] == -1u)) &&
426 "Kill and Def maps aren't consistent for AntiDepReg!");
427 assert(((KillIndices[NewReg] == -1u) != (DefIndices[NewReg] == -1u)) &&
428 "Kill and Def maps aren't consistent for NewReg!");
429 if (KillIndices[NewReg] == -1u &&
430 KillIndices[AntiDepReg] <= DefIndices[NewReg]) {
431 DOUT << "Breaking anti-dependence edge on reg " << AntiDepReg
432 << " with " << RegRefs.count(AntiDepReg) << " references"
433 << " with new reg " << NewReg << "!\n";
435 // Update the references to the old register to refer to the new
437 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
438 std::multimap<unsigned, MachineOperand *>::iterator>
439 Range = RegRefs.equal_range(AntiDepReg);
440 for (std::multimap<unsigned, MachineOperand *>::iterator
441 Q = Range.first, QE = Range.second; Q != QE; ++Q)
442 Q->second->setReg(NewReg);
444 // We just went back in time and modified history; the
445 // liveness information for the anti-depenence reg is now
446 // inconsistent. Set the state as if it were dead.
447 Classes[NewReg] = Classes[AntiDepReg];
448 DefIndices[NewReg] = DefIndices[AntiDepReg];
449 KillIndices[NewReg] = KillIndices[AntiDepReg];
451 Classes[AntiDepReg] = 0;
452 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
453 KillIndices[AntiDepReg] = -1;
455 RegRefs.erase(AntiDepReg);
457 LastNewReg[AntiDepReg] = NewReg;
464 // Proceding upwards, registers that are defed but not used in this
465 // instruction are now dead.
466 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
467 MachineOperand &MO = MI->getOperand(i);
468 if (!MO.isReg()) continue;
469 unsigned Reg = MO.getReg();
470 if (Reg == 0) continue;
471 if (!MO.isDef()) continue;
472 // Ignore two-addr defs.
473 if (MI->isRegReDefinedByTwoAddr(Reg, i)) continue;
475 DefIndices[Reg] = Count;
476 KillIndices[Reg] = -1;
479 // Repeat, for all subregs.
480 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
482 unsigned SubregReg = *Subreg;
483 DefIndices[SubregReg] = Count;
484 KillIndices[SubregReg] = -1;
485 Classes[SubregReg] = 0;
486 RegRefs.erase(SubregReg);
489 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
490 MachineOperand &MO = MI->getOperand(i);
491 if (!MO.isReg()) continue;
492 unsigned Reg = MO.getReg();
493 if (Reg == 0) continue;
494 if (!MO.isUse()) continue;
496 const TargetRegisterClass *NewRC =
497 getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
499 // For now, only allow the register to be changed if its register
500 // class is consistent across all uses.
501 if (!Classes[Reg] && NewRC)
502 Classes[Reg] = NewRC;
503 else if (!NewRC || Classes[Reg] != NewRC)
504 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
506 RegRefs.insert(std::make_pair(Reg, &MO));
508 // It wasn't previously live but now it is, this is a kill.
509 if (KillIndices[Reg] == -1u) {
510 KillIndices[Reg] = Count;
511 DefIndices[Reg] = -1u;
513 // Repeat, for all aliases.
514 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
515 unsigned AliasReg = *Alias;
516 if (KillIndices[AliasReg] == -1u) {
517 KillIndices[AliasReg] = Count;
518 DefIndices[AliasReg] = -1u;
523 assert(Count == -1u && "Count mismatch!");
528 //===----------------------------------------------------------------------===//
529 // Top-Down Scheduling
530 //===----------------------------------------------------------------------===//
532 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
533 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
534 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SUnit *SuccSU, bool isChain) {
535 --SuccSU->NumPredsLeft;
538 if (SuccSU->NumPredsLeft < 0) {
539 cerr << "*** Scheduling failed! ***\n";
541 cerr << " has been released too many times!\n";
546 // Compute how many cycles it will be before this actually becomes
547 // available. This is the max of the start time of all predecessors plus
549 // If this is a token edge, we don't need to wait for the latency of the
550 // preceeding instruction (e.g. a long-latency load) unless there is also
551 // some other data dependence.
552 unsigned PredDoneCycle = SU->Cycle;
554 PredDoneCycle += SU->Latency;
555 else if (SU->Latency)
557 SuccSU->CycleBound = std::max(SuccSU->CycleBound, PredDoneCycle);
559 if (SuccSU->NumPredsLeft == 0) {
560 PendingQueue.push_back(SuccSU);
564 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
565 /// count of its successors. If a successor pending count is zero, add it to
566 /// the Available queue.
567 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
568 DOUT << "*** Scheduling [" << CurCycle << "]: ";
569 DEBUG(SU->dump(this));
571 Sequence.push_back(SU);
572 SU->Cycle = CurCycle;
574 // Top down: release successors.
575 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
577 ReleaseSucc(SU, I->Dep, I->isCtrl);
579 SU->isScheduled = true;
580 AvailableQueue.ScheduledNode(SU);
583 /// ListScheduleTopDown - The main loop of list scheduling for top-down
585 void SchedulePostRATDList::ListScheduleTopDown() {
586 unsigned CurCycle = 0;
588 // All leaves to Available queue.
589 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
590 // It is available if it has no predecessors.
591 if (SUnits[i].Preds.empty()) {
592 AvailableQueue.push(&SUnits[i]);
593 SUnits[i].isAvailable = true;
597 // While Available queue is not empty, grab the node with the highest
598 // priority. If it is not ready put it back. Schedule the node.
599 Sequence.reserve(SUnits.size());
600 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
601 // Check to see if any of the pending instructions are ready to issue. If
602 // so, add them to the available queue.
603 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
604 if (PendingQueue[i]->CycleBound == CurCycle) {
605 AvailableQueue.push(PendingQueue[i]);
606 PendingQueue[i]->isAvailable = true;
607 PendingQueue[i] = PendingQueue.back();
608 PendingQueue.pop_back();
611 assert(PendingQueue[i]->CycleBound > CurCycle && "Negative latency?");
615 // If there are no instructions available, don't try to issue anything.
616 if (AvailableQueue.empty()) {
621 SUnit *FoundSUnit = AvailableQueue.pop();
623 // If we found a node to schedule, do it now.
625 ScheduleNodeTopDown(FoundSUnit, CurCycle);
627 // If this is a pseudo-op node, we don't want to increment the current
629 if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
632 // Otherwise, we have a pipeline stall, but no other problem, just advance
633 // the current cycle and try again.
634 DOUT << "*** Advancing cycle, no work to do\n";
641 VerifySchedule(/*isBottomUp=*/false);
645 //===----------------------------------------------------------------------===//
646 // Public Constructor Functions
647 //===----------------------------------------------------------------------===//
649 FunctionPass *llvm::createPostRAScheduler() {
650 return new PostRAScheduler();