1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "post-RA-sched"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
24 #include "llvm/CodeGen/LatencyPriorityQueue.h"
25 #include "llvm/CodeGen/SchedulerRegistry.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/ADT/Statistic.h"
32 STATISTIC(NumStalls, "Number of pipeline stalls");
35 class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
38 PostRAScheduler() : MachineFunctionPass(&ID) {}
41 const TargetMachine *TM;
43 const char *getPassName() const {
44 return "Post RA top-down list latency scheduler (STUB)";
47 bool runOnMachineFunction(MachineFunction &Fn);
49 char PostRAScheduler::ID = 0;
51 class VISIBILITY_HIDDEN SchedulePostRATDList : public ScheduleDAGInstrs {
53 SchedulePostRATDList(MachineBasicBlock *mbb, const TargetMachine &tm)
54 : ScheduleDAGInstrs(mbb, tm) {}
57 const TargetMachine *TM;
59 /// AvailableQueue - The priority queue to use for the available SUnits.
61 LatencyPriorityQueue AvailableQueue;
63 /// PendingQueue - This contains all of the instructions whose operands have
64 /// been issued, but their results are not ready yet (due to the latency of
65 /// the operation). Once the operands becomes available, the instruction is
66 /// added to the AvailableQueue.
67 std::vector<SUnit*> PendingQueue;
70 const char *getPassName() const {
71 return "Post RA top-down list latency scheduler (STUB)";
74 bool runOnMachineFunction(MachineFunction &Fn);
79 void ReleaseSucc(SUnit *SU, SUnit *SuccSU, bool isChain);
80 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
81 void ListScheduleTopDown();
85 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
86 DOUT << "PostRAScheduler\n";
88 TM = &MF->getTarget();
90 // Loop over all of the basic blocks
91 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
94 SchedulePostRATDList Scheduler(MBB, *TM);
98 Scheduler.EmitSchedule();
104 /// Schedule - Schedule the DAG using list scheduling.
105 void SchedulePostRATDList::Schedule() {
106 DOUT << "********** List Scheduling **********\n";
108 // Build scheduling units.
111 AvailableQueue.initNodes(SUnits);
113 ListScheduleTopDown();
115 AvailableQueue.releaseState();
118 //===----------------------------------------------------------------------===//
119 // Top-Down Scheduling
120 //===----------------------------------------------------------------------===//
122 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
123 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
124 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SUnit *SuccSU, bool isChain) {
125 --SuccSU->NumPredsLeft;
128 if (SuccSU->NumPredsLeft < 0) {
129 cerr << "*** Scheduling failed! ***\n";
131 cerr << " has been released too many times!\n";
136 // Compute how many cycles it will be before this actually becomes
137 // available. This is the max of the start time of all predecessors plus
139 // If this is a token edge, we don't need to wait for the latency of the
140 // preceeding instruction (e.g. a long-latency load) unless there is also
141 // some other data dependence.
142 unsigned PredDoneCycle = SU->Cycle;
144 PredDoneCycle += SU->Latency;
145 else if (SU->Latency)
147 SuccSU->CycleBound = std::max(SuccSU->CycleBound, PredDoneCycle);
149 if (SuccSU->NumPredsLeft == 0) {
150 PendingQueue.push_back(SuccSU);
154 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
155 /// count of its successors. If a successor pending count is zero, add it to
156 /// the Available queue.
157 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
158 DOUT << "*** Scheduling [" << CurCycle << "]: ";
159 DEBUG(SU->dump(this));
161 Sequence.push_back(SU);
162 SU->Cycle = CurCycle;
164 // Top down: release successors.
165 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
167 ReleaseSucc(SU, I->Dep, I->isCtrl);
169 SU->isScheduled = true;
170 AvailableQueue.ScheduledNode(SU);
173 /// ListScheduleTopDown - The main loop of list scheduling for top-down
175 void SchedulePostRATDList::ListScheduleTopDown() {
176 unsigned CurCycle = 0;
178 // All leaves to Available queue.
179 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
180 // It is available if it has no predecessors.
181 if (SUnits[i].Preds.empty()) {
182 AvailableQueue.push(&SUnits[i]);
183 SUnits[i].isAvailable = true;
187 // While Available queue is not empty, grab the node with the highest
188 // priority. If it is not ready put it back. Schedule the node.
189 Sequence.reserve(SUnits.size());
190 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
191 // Check to see if any of the pending instructions are ready to issue. If
192 // so, add them to the available queue.
193 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
194 if (PendingQueue[i]->CycleBound == CurCycle) {
195 AvailableQueue.push(PendingQueue[i]);
196 PendingQueue[i]->isAvailable = true;
197 PendingQueue[i] = PendingQueue.back();
198 PendingQueue.pop_back();
201 assert(PendingQueue[i]->CycleBound > CurCycle && "Negative latency?");
205 // If there are no instructions available, don't try to issue anything, and
206 // don't advance the hazard recognizer.
207 if (AvailableQueue.empty()) {
212 SUnit *FoundSUnit = AvailableQueue.pop();
214 // If we found a node to schedule, do it now.
216 ScheduleNodeTopDown(FoundSUnit, CurCycle);
218 // If this is a pseudo-op node, we don't want to increment the current
220 if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
223 // Otherwise, we have a pipeline stall, but no other problem, just advance
224 // the current cycle and try again.
225 DOUT << "*** Advancing cycle, no work to do\n";
232 VerifySchedule(/*isBottomUp=*/false);
236 //===----------------------------------------------------------------------===//
237 // Public Constructor Functions
238 //===----------------------------------------------------------------------===//
240 FunctionPass *llvm::createPostRAScheduler() {
241 return new PostRAScheduler();