1 //===-- PreAllocSplitting.cpp - Pre-allocation Interval Spltting Pass. ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine instruction level pre-register allocation
11 // live interval splitting pass. It finds live interval barriers, i.e.
12 // instructions which will kill all physical registers in certain register
13 // classes, and split all live intervals which cross the barrier.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "pre-alloc-split"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/LiveStackAnalysis.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/DenseMap.h"
34 #include "llvm/ADT/DepthFirstIterator.h"
35 #include "llvm/ADT/SmallPtrSet.h"
36 #include "llvm/ADT/Statistic.h"
39 static cl::opt<int> PreSplitLimit("pre-split-limit", cl::init(-1), cl::Hidden);
41 STATISTIC(NumSplits, "Number of intervals split");
42 STATISTIC(NumRemats, "Number of intervals split by rematerialization");
43 STATISTIC(NumFolds, "Number of intervals split with spill folding");
44 STATISTIC(NumRenumbers, "Number of intervals renumbered into new registers");
47 class VISIBILITY_HIDDEN PreAllocSplitting : public MachineFunctionPass {
48 MachineFunction *CurrMF;
49 const TargetMachine *TM;
50 const TargetInstrInfo *TII;
51 MachineFrameInfo *MFI;
52 MachineRegisterInfo *MRI;
56 // Barrier - Current barrier being processed.
57 MachineInstr *Barrier;
59 // BarrierMBB - Basic block where the barrier resides in.
60 MachineBasicBlock *BarrierMBB;
62 // Barrier - Current barrier index.
65 // CurrLI - Current live interval being split.
68 // CurrSLI - Current stack slot live interval.
69 LiveInterval *CurrSLI;
71 // CurrSValNo - Current val# for the stack slot live interval.
74 // IntervalSSMap - A map from live interval to spill slots.
75 DenseMap<unsigned, int> IntervalSSMap;
77 // Def2SpillMap - A map from a def instruction index to spill index.
78 DenseMap<unsigned, unsigned> Def2SpillMap;
82 PreAllocSplitting() : MachineFunctionPass(&ID) {}
84 virtual bool runOnMachineFunction(MachineFunction &MF);
86 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
87 AU.addRequired<LiveIntervals>();
88 AU.addPreserved<LiveIntervals>();
89 AU.addRequired<LiveStacks>();
90 AU.addPreserved<LiveStacks>();
91 AU.addPreserved<RegisterCoalescer>();
93 AU.addPreservedID(StrongPHIEliminationID);
95 AU.addPreservedID(PHIEliminationID);
96 AU.addRequired<MachineDominatorTree>();
97 AU.addRequired<MachineLoopInfo>();
98 AU.addPreserved<MachineDominatorTree>();
99 AU.addPreserved<MachineLoopInfo>();
100 MachineFunctionPass::getAnalysisUsage(AU);
103 virtual void releaseMemory() {
104 IntervalSSMap.clear();
105 Def2SpillMap.clear();
108 virtual const char *getPassName() const {
109 return "Pre-Register Allocaton Live Interval Splitting";
112 /// print - Implement the dump method.
113 virtual void print(std::ostream &O, const Module* M = 0) const {
117 void print(std::ostream *O, const Module* M = 0) const {
122 MachineBasicBlock::iterator
123 findNextEmptySlot(MachineBasicBlock*, MachineInstr*,
126 MachineBasicBlock::iterator
127 findSpillPoint(MachineBasicBlock*, MachineInstr*, MachineInstr*,
128 SmallPtrSet<MachineInstr*, 4>&, unsigned&);
130 MachineBasicBlock::iterator
131 findRestorePoint(MachineBasicBlock*, MachineInstr*, unsigned,
132 SmallPtrSet<MachineInstr*, 4>&, unsigned&);
134 int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
136 bool IsAvailableInStack(MachineBasicBlock*, unsigned, unsigned, unsigned,
137 unsigned&, int&) const;
139 void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned);
141 VNInfo* UpdateRegisterInterval(VNInfo*, unsigned, unsigned);
143 bool ShrinkWrapToLastUse(MachineBasicBlock*, VNInfo*,
144 SmallVector<MachineOperand*, 4>&,
145 SmallPtrSet<MachineInstr*, 4>&);
147 void ShrinkWrapLiveInterval(VNInfo*, MachineBasicBlock*, MachineBasicBlock*,
148 MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8>&,
149 DenseMap<MachineBasicBlock*, SmallVector<MachineOperand*, 4> >&,
150 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 4> >&,
151 SmallVector<MachineBasicBlock*, 4>&);
153 bool SplitRegLiveInterval(LiveInterval*);
155 bool SplitRegLiveIntervals(const TargetRegisterClass **);
157 void RepairLiveInterval(LiveInterval* CurrLI, VNInfo* ValNo,
158 MachineInstr* DefMI, unsigned RestoreIdx);
160 bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB,
161 MachineBasicBlock* BarrierMBB);
162 bool Rematerialize(unsigned vreg, VNInfo* ValNo,
164 MachineBasicBlock::iterator RestorePt,
166 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
167 MachineInstr* FoldSpill(unsigned vreg, const TargetRegisterClass* RC,
169 MachineInstr* Barrier,
170 MachineBasicBlock* MBB,
172 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
173 void RenumberValno(VNInfo* VN);
174 void ReconstructLiveInterval(LiveInterval* LI);
175 VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator use,
176 MachineBasicBlock* MBB,
178 SmallPtrSet<MachineInstr*, 4>& Visited,
179 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
180 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
181 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
182 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
183 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
184 bool toplevel, bool intrablock);
186 } // end anonymous namespace
188 char PreAllocSplitting::ID = 0;
190 static RegisterPass<PreAllocSplitting>
191 X("pre-alloc-splitting", "Pre-Register Allocation Live Interval Splitting");
193 const PassInfo *const llvm::PreAllocSplittingID = &X;
196 /// findNextEmptySlot - Find a gap after the given machine instruction in the
197 /// instruction index map. If there isn't one, return end().
198 MachineBasicBlock::iterator
199 PreAllocSplitting::findNextEmptySlot(MachineBasicBlock *MBB, MachineInstr *MI,
200 unsigned &SpotIndex) {
201 MachineBasicBlock::iterator MII = MI;
202 if (++MII != MBB->end()) {
203 unsigned Index = LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
212 /// findSpillPoint - Find a gap as far away from the given MI that's suitable
213 /// for spilling the current live interval. The index must be before any
214 /// defs and uses of the live interval register in the mbb. Return begin() if
216 MachineBasicBlock::iterator
217 PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
219 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
220 unsigned &SpillIndex) {
221 MachineBasicBlock::iterator Pt = MBB->begin();
223 // Go top down if RefsInMBB is empty.
224 if (RefsInMBB.empty() && !DefMI) {
225 MachineBasicBlock::iterator MII = MBB->begin();
226 MachineBasicBlock::iterator EndPt = MI;
229 unsigned Index = LIs->getInstructionIndex(MII);
230 unsigned Gap = LIs->findGapBeforeInstr(Index);
236 } while (MII != EndPt);
238 MachineBasicBlock::iterator MII = MI;
239 MachineBasicBlock::iterator EndPt = DefMI
240 ? MachineBasicBlock::iterator(DefMI) : MBB->begin();
241 while (MII != EndPt && !RefsInMBB.count(MII)) {
242 unsigned Index = LIs->getInstructionIndex(MII);
243 if (LIs->hasGapBeforeInstr(Index)) {
245 SpillIndex = LIs->findGapBeforeInstr(Index, true);
254 /// findRestorePoint - Find a gap in the instruction index map that's suitable
255 /// for restoring the current live interval value. The index must be before any
256 /// uses of the live interval register in the mbb. Return end() if none is
258 MachineBasicBlock::iterator
259 PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
261 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
262 unsigned &RestoreIndex) {
263 // FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
264 // begin index accordingly.
265 MachineBasicBlock::iterator Pt = MBB->end();
266 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
268 // Go bottom up if RefsInMBB is empty and the end of the mbb isn't beyond
269 // the last index in the live range.
270 if (RefsInMBB.empty() && LastIdx >= EndIdx) {
271 MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
272 MachineBasicBlock::iterator EndPt = MI;
275 unsigned Index = LIs->getInstructionIndex(MII);
276 unsigned Gap = LIs->findGapBeforeInstr(Index);
283 } while (MII != EndPt);
285 MachineBasicBlock::iterator MII = MI;
287 // FIXME: Limit the number of instructions to examine to reduce
289 while (MII != MBB->end()) {
290 unsigned Index = LIs->getInstructionIndex(MII);
293 unsigned Gap = LIs->findGapBeforeInstr(Index);
298 if (RefsInMBB.count(MII))
307 /// CreateSpillStackSlot - Create a stack slot for the live interval being
308 /// split. If the live interval was previously split, just reuse the same
310 int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
311 const TargetRegisterClass *RC) {
313 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
314 if (I != IntervalSSMap.end()) {
317 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
318 IntervalSSMap[Reg] = SS;
321 // Create live interval for stack slot.
322 CurrSLI = &LSs->getOrCreateInterval(SS);
323 if (CurrSLI->hasAtLeastOneValue())
324 CurrSValNo = CurrSLI->getValNumInfo(0);
326 CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
330 /// IsAvailableInStack - Return true if register is available in a split stack
331 /// slot at the specified index.
333 PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
334 unsigned Reg, unsigned DefIndex,
335 unsigned RestoreIndex, unsigned &SpillIndex,
340 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
341 if (I == IntervalSSMap.end())
343 DenseMap<unsigned, unsigned>::iterator II = Def2SpillMap.find(DefIndex);
344 if (II == Def2SpillMap.end())
347 // If last spill of def is in the same mbb as barrier mbb (where restore will
348 // be), make sure it's not below the intended restore index.
349 // FIXME: Undo the previous spill?
350 assert(LIs->getMBBFromIndex(II->second) == DefMBB);
351 if (DefMBB == BarrierMBB && II->second >= RestoreIndex)
355 SpillIndex = II->second;
359 /// UpdateSpillSlotInterval - Given the specified val# of the register live
360 /// interval being split, and the spill and restore indicies, update the live
361 /// interval of the spill stack slot.
363 PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
364 unsigned RestoreIndex) {
365 assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
366 "Expect restore in the barrier mbb");
368 MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
369 if (MBB == BarrierMBB) {
370 // Intra-block spill + restore. We are done.
371 LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo);
372 CurrSLI->addRange(SLR);
376 SmallPtrSet<MachineBasicBlock*, 4> Processed;
377 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
378 LiveRange SLR(SpillIndex, EndIdx+1, CurrSValNo);
379 CurrSLI->addRange(SLR);
380 Processed.insert(MBB);
382 // Start from the spill mbb, figure out the extend of the spill slot's
384 SmallVector<MachineBasicBlock*, 4> WorkList;
385 const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
386 if (LR->end > EndIdx)
387 // If live range extend beyond end of mbb, add successors to work list.
388 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
389 SE = MBB->succ_end(); SI != SE; ++SI)
390 WorkList.push_back(*SI);
392 while (!WorkList.empty()) {
393 MachineBasicBlock *MBB = WorkList.back();
395 if (Processed.count(MBB))
397 unsigned Idx = LIs->getMBBStartIdx(MBB);
398 LR = CurrLI->getLiveRangeContaining(Idx);
399 if (LR && LR->valno == ValNo) {
400 EndIdx = LIs->getMBBEndIdx(MBB);
401 if (Idx <= RestoreIndex && RestoreIndex < EndIdx) {
402 // Spill slot live interval stops at the restore.
403 LiveRange SLR(Idx, RestoreIndex, CurrSValNo);
404 CurrSLI->addRange(SLR);
405 } else if (LR->end > EndIdx) {
406 // Live range extends beyond end of mbb, process successors.
407 LiveRange SLR(Idx, EndIdx+1, CurrSValNo);
408 CurrSLI->addRange(SLR);
409 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
410 SE = MBB->succ_end(); SI != SE; ++SI)
411 WorkList.push_back(*SI);
413 LiveRange SLR(Idx, LR->end, CurrSValNo);
414 CurrSLI->addRange(SLR);
416 Processed.insert(MBB);
421 /// UpdateRegisterInterval - Given the specified val# of the current live
422 /// interval is being split, and the spill and restore indices, update the live
423 /// interval accordingly.
425 PreAllocSplitting::UpdateRegisterInterval(VNInfo *ValNo, unsigned SpillIndex,
426 unsigned RestoreIndex) {
427 assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
428 "Expect restore in the barrier mbb");
430 SmallVector<std::pair<unsigned,unsigned>, 4> Before;
431 SmallVector<std::pair<unsigned,unsigned>, 4> After;
432 SmallVector<unsigned, 4> BeforeKills;
433 SmallVector<unsigned, 4> AfterKills;
434 SmallPtrSet<const LiveRange*, 4> Processed;
436 // First, let's figure out which parts of the live interval is now defined
437 // by the restore, which are defined by the original definition.
438 const LiveRange *LR = CurrLI->getLiveRangeContaining(RestoreIndex);
439 After.push_back(std::make_pair(RestoreIndex, LR->end));
440 if (CurrLI->isKill(ValNo, LR->end))
441 AfterKills.push_back(LR->end);
443 assert(LR->contains(SpillIndex));
444 if (SpillIndex > LR->start) {
445 Before.push_back(std::make_pair(LR->start, SpillIndex));
446 BeforeKills.push_back(SpillIndex);
448 Processed.insert(LR);
450 // Start from the restore mbb, figure out what part of the live interval
451 // are defined by the restore.
452 SmallVector<MachineBasicBlock*, 4> WorkList;
453 MachineBasicBlock *MBB = BarrierMBB;
454 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
455 SE = MBB->succ_end(); SI != SE; ++SI)
456 WorkList.push_back(*SI);
458 SmallPtrSet<MachineBasicBlock*, 4> ProcessedBlocks;
459 ProcessedBlocks.insert(MBB);
461 while (!WorkList.empty()) {
462 MBB = WorkList.back();
464 unsigned Idx = LIs->getMBBStartIdx(MBB);
465 LR = CurrLI->getLiveRangeContaining(Idx);
466 if (LR && LR->valno == ValNo && !Processed.count(LR)) {
467 After.push_back(std::make_pair(LR->start, LR->end));
468 if (CurrLI->isKill(ValNo, LR->end))
469 AfterKills.push_back(LR->end);
470 Idx = LIs->getMBBEndIdx(MBB);
472 // Live range extend beyond at least one mbb. Let's see what other
474 LIs->findReachableMBBs(LR->start, LR->end, WorkList);
476 Processed.insert(LR);
479 ProcessedBlocks.insert(MBB);
481 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
482 SE = MBB->succ_end(); SI != SE; ++SI)
483 if (!ProcessedBlocks.count(*SI))
484 WorkList.push_back(*SI);
487 for (LiveInterval::iterator I = CurrLI->begin(), E = CurrLI->end();
490 if (LR->valno == ValNo && !Processed.count(LR)) {
491 Before.push_back(std::make_pair(LR->start, LR->end));
492 if (CurrLI->isKill(ValNo, LR->end))
493 BeforeKills.push_back(LR->end);
497 // Now create new val#s to represent the live ranges defined by the old def
498 // those defined by the restore.
499 unsigned AfterDef = ValNo->def;
500 MachineInstr *AfterCopy = ValNo->copy;
501 bool HasPHIKill = ValNo->hasPHIKill;
502 CurrLI->removeValNo(ValNo);
503 VNInfo *BValNo = (Before.empty())
505 : CurrLI->getNextValue(AfterDef, AfterCopy, LIs->getVNInfoAllocator());
507 CurrLI->addKills(BValNo, BeforeKills);
509 VNInfo *AValNo = (After.empty())
511 : CurrLI->getNextValue(RestoreIndex, 0, LIs->getVNInfoAllocator());
513 AValNo->hasPHIKill = HasPHIKill;
514 CurrLI->addKills(AValNo, AfterKills);
517 for (unsigned i = 0, e = Before.size(); i != e; ++i) {
518 unsigned Start = Before[i].first;
519 unsigned End = Before[i].second;
520 CurrLI->addRange(LiveRange(Start, End, BValNo));
522 for (unsigned i = 0, e = After.size(); i != e; ++i) {
523 unsigned Start = After[i].first;
524 unsigned End = After[i].second;
525 CurrLI->addRange(LiveRange(Start, End, AValNo));
531 /// ShrinkWrapToLastUse - There are uses of the current live interval in the
532 /// given block, shrink wrap the live interval to the last use (i.e. remove
533 /// from last use to the end of the mbb). In case mbb is the where the barrier
534 /// is, remove from the last use to the barrier.
536 PreAllocSplitting::ShrinkWrapToLastUse(MachineBasicBlock *MBB, VNInfo *ValNo,
537 SmallVector<MachineOperand*, 4> &Uses,
538 SmallPtrSet<MachineInstr*, 4> &UseMIs) {
539 MachineOperand *LastMO = 0;
540 MachineInstr *LastMI = 0;
541 if (MBB != BarrierMBB && Uses.size() == 1) {
542 // Single use, no need to traverse the block. We can't assume this for the
543 // barrier bb though since the use is probably below the barrier.
545 LastMI = LastMO->getParent();
547 MachineBasicBlock::iterator MEE = MBB->begin();
548 MachineBasicBlock::iterator MII;
549 if (MBB == BarrierMBB)
555 MachineInstr *UseMI = &*MII;
556 if (!UseMIs.count(UseMI))
558 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
559 MachineOperand &MO = UseMI->getOperand(i);
560 if (MO.isReg() && MO.getReg() == CurrLI->reg) {
570 // Cut off live range from last use (or beginning of the mbb if there
571 // are no uses in it) to the end of the mbb.
572 unsigned RangeStart, RangeEnd = LIs->getMBBEndIdx(MBB)+1;
574 RangeStart = LIs->getUseIndex(LIs->getInstructionIndex(LastMI))+1;
575 assert(!LastMO->isKill() && "Last use already terminates the interval?");
578 assert(MBB == BarrierMBB);
579 RangeStart = LIs->getMBBStartIdx(MBB);
581 if (MBB == BarrierMBB)
582 RangeEnd = LIs->getUseIndex(BarrierIdx)+1;
583 CurrLI->removeRange(RangeStart, RangeEnd);
585 CurrLI->addKill(ValNo, RangeStart);
587 // Return true if the last use becomes a new kill.
591 /// PerformPHIConstruction - From properly set up use and def lists, use a PHI
592 /// construction algorithm to compute the ranges and valnos for an interval.
593 VNInfo* PreAllocSplitting::PerformPHIConstruction(
594 MachineBasicBlock::iterator use,
595 MachineBasicBlock* MBB,
597 SmallPtrSet<MachineInstr*, 4>& Visited,
598 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
599 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
600 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
601 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
602 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
603 bool toplevel, bool intrablock) {
604 // Return memoized result if it's available.
605 if (toplevel && Visited.count(use) && NewVNs.count(use))
607 else if (!toplevel && intrablock && NewVNs.count(use))
609 else if (!intrablock && LiveOut.count(MBB))
612 typedef DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> > RegMap;
614 // Check if our block contains any uses or defs.
615 bool ContainsDefs = Defs.count(MBB);
616 bool ContainsUses = Uses.count(MBB);
620 // Enumerate the cases of use/def contaning blocks.
621 if (!ContainsDefs && !ContainsUses) {
623 // NOTE: Because this is the fallback case from other cases, we do NOT
624 // assume that we are not intrablock here.
625 if (Phis.count(MBB)) return Phis[MBB];
627 unsigned StartIndex = LIs->getMBBStartIdx(MBB);
629 if (MBB->pred_size() == 1) {
630 Phis[MBB] = ret = PerformPHIConstruction((*MBB->pred_begin())->end(),
631 *(MBB->pred_begin()), LI, Visited,
632 Defs, Uses, NewVNs, LiveOut, Phis,
634 unsigned EndIndex = 0;
636 EndIndex = LIs->getInstructionIndex(use);
637 EndIndex = LiveIntervals::getUseIndex(EndIndex);
639 EndIndex = LIs->getMBBEndIdx(MBB);
641 LI->addRange(LiveRange(StartIndex, EndIndex+1, ret));
643 LI->addKill(ret, EndIndex);
645 Phis[MBB] = ret = LI->getNextValue(~0U, /*FIXME*/ 0,
646 LIs->getVNInfoAllocator());
647 if (!intrablock) LiveOut[MBB] = ret;
649 // If there are no uses or defs between our starting point and the
650 // beginning of the block, then recursive perform phi construction
651 // on our predecessors.
652 DenseMap<MachineBasicBlock*, VNInfo*> IncomingVNs;
653 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
654 PE = MBB->pred_end(); PI != PE; ++PI) {
655 VNInfo* Incoming = PerformPHIConstruction((*PI)->end(), *PI, LI,
656 Visited, Defs, Uses, NewVNs,
657 LiveOut, Phis, false, false);
659 IncomingVNs[*PI] = Incoming;
662 // Otherwise, merge the incoming VNInfos with a phi join. Create a new
663 // VNInfo to represent the joined value.
664 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator I =
665 IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) {
666 I->second->hasPHIKill = true;
667 unsigned KillIndex = LIs->getMBBEndIdx(I->first);
668 LI->addKill(I->second, KillIndex);
671 unsigned EndIndex = 0;
673 EndIndex = LIs->getInstructionIndex(use);
674 EndIndex = LiveIntervals::getUseIndex(EndIndex);
676 EndIndex = LIs->getMBBEndIdx(MBB);
677 LI->addRange(LiveRange(StartIndex, EndIndex+1, ret));
679 LI->addKill(ret, EndIndex);
681 } else if (ContainsDefs && !ContainsUses) {
682 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
684 // Search for the def in this block. If we don't find it before the
685 // instruction we care about, go to the fallback case. Note that that
686 // should never happen: this cannot be intrablock, so use should
687 // always be an end() iterator.
688 assert(use == MBB->end() && "No use marked in intrablock");
690 MachineBasicBlock::iterator walker = use;
692 while (walker != MBB->begin())
693 if (BlockDefs.count(walker)) {
698 // Once we've found it, extend its VNInfo to our instruction.
699 unsigned DefIndex = LIs->getInstructionIndex(walker);
700 DefIndex = LiveIntervals::getDefIndex(DefIndex);
701 unsigned EndIndex = LIs->getMBBEndIdx(MBB);
703 ret = NewVNs[walker];
704 LI->addRange(LiveRange(DefIndex, EndIndex+1, ret));
705 } else if (!ContainsDefs && ContainsUses) {
706 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
708 // Search for the use in this block that precedes the instruction we care
709 // about, going to the fallback case if we don't find it.
711 if (use == MBB->begin())
714 MachineBasicBlock::iterator walker = use;
717 while (walker != MBB->begin())
718 if (BlockUses.count(walker)) {
724 // Must check begin() too.
726 if (BlockUses.count(walker))
732 unsigned UseIndex = LIs->getInstructionIndex(walker);
733 UseIndex = LiveIntervals::getUseIndex(UseIndex);
734 unsigned EndIndex = 0;
736 EndIndex = LIs->getInstructionIndex(use);
737 EndIndex = LiveIntervals::getUseIndex(EndIndex);
739 EndIndex = LIs->getMBBEndIdx(MBB);
741 // Now, recursively phi construct the VNInfo for the use we found,
742 // and then extend it to include the instruction we care about
743 ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses,
744 NewVNs, LiveOut, Phis, false, true);
746 // FIXME: Need to set kills properly for inter-block stuff.
747 if (LI->isKill(ret, UseIndex)) LI->removeKill(ret, UseIndex);
749 LI->addKill(ret, EndIndex);
751 LI->addRange(LiveRange(UseIndex, EndIndex+1, ret));
752 } else if (ContainsDefs && ContainsUses){
753 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
754 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
756 // This case is basically a merging of the two preceding case, with the
757 // special note that checking for defs must take precedence over checking
758 // for uses, because of two-address instructions.
760 if (use == MBB->begin())
763 MachineBasicBlock::iterator walker = use;
765 bool foundDef = false;
766 bool foundUse = false;
767 while (walker != MBB->begin())
768 if (BlockDefs.count(walker)) {
771 } else if (BlockUses.count(walker)) {
777 // Must check begin() too.
778 if (!foundDef && !foundUse) {
779 if (BlockDefs.count(walker))
781 else if (BlockUses.count(walker))
787 unsigned StartIndex = LIs->getInstructionIndex(walker);
788 StartIndex = foundDef ? LiveIntervals::getDefIndex(StartIndex) :
789 LiveIntervals::getUseIndex(StartIndex);
790 unsigned EndIndex = 0;
792 EndIndex = LIs->getInstructionIndex(use);
793 EndIndex = LiveIntervals::getUseIndex(EndIndex);
795 EndIndex = LIs->getMBBEndIdx(MBB);
798 ret = NewVNs[walker];
800 ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses,
801 NewVNs, LiveOut, Phis, false, true);
803 if (foundUse && LI->isKill(ret, StartIndex))
804 LI->removeKill(ret, StartIndex);
806 LI->addKill(ret, EndIndex);
809 LI->addRange(LiveRange(StartIndex, EndIndex+1, ret));
812 // Memoize results so we don't have to recompute them.
813 if (!intrablock) LiveOut[MBB] = ret;
815 if (!NewVNs.count(use))
823 /// ReconstructLiveInterval - Recompute a live interval from scratch.
824 void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) {
825 BumpPtrAllocator& Alloc = LIs->getVNInfoAllocator();
827 // Clear the old ranges and valnos;
830 // Cache the uses and defs of the register
831 typedef DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> > RegMap;
834 // Keep track of the new VNs we're creating.
835 DenseMap<MachineInstr*, VNInfo*> NewVNs;
836 SmallPtrSet<VNInfo*, 2> PhiVNs;
838 // Cache defs, and create a new VNInfo for each def.
839 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
840 DE = MRI->def_end(); DI != DE; ++DI) {
841 Defs[(*DI).getParent()].insert(&*DI);
843 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
844 DefIdx = LiveIntervals::getDefIndex(DefIdx);
846 VNInfo* NewVN = LI->getNextValue(DefIdx, 0, Alloc);
848 // If the def is a move, set the copy field.
849 unsigned source, dest;
850 if (TII->isMoveInstr(*DI, source, dest))
854 NewVNs[&*DI] = NewVN;
857 // Cache uses as a separate pass from actually processing them.
858 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
859 UE = MRI->use_end(); UI != UE; ++UI)
860 Uses[(*UI).getParent()].insert(&*UI);
862 // Now, actually process every use and use a phi construction algorithm
863 // to walk from it to its reaching definitions, building VNInfos along
865 DenseMap<MachineBasicBlock*, VNInfo*> LiveOut;
866 DenseMap<MachineBasicBlock*, VNInfo*> Phis;
867 SmallPtrSet<MachineInstr*, 4> Visited;
868 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
869 UE = MRI->use_end(); UI != UE; ++UI) {
870 PerformPHIConstruction(&*UI, UI->getParent(), LI, Visited, Defs,
871 Uses, NewVNs, LiveOut, Phis, true, true);
874 // Add ranges for dead defs
875 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
876 DE = MRI->def_end(); DI != DE; ++DI) {
877 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
878 DefIdx = LiveIntervals::getDefIndex(DefIdx);
880 if (LI->liveAt(DefIdx)) continue;
882 VNInfo* DeadVN = NewVNs[&*DI];
883 LI->addRange(LiveRange(DefIdx, DefIdx+1, DeadVN));
884 LI->addKill(DeadVN, DefIdx);
888 /// ShrinkWrapLiveInterval - Recursively traverse the predecessor
889 /// chain to find the new 'kills' and shrink wrap the live interval to the
890 /// new kill indices.
892 PreAllocSplitting::ShrinkWrapLiveInterval(VNInfo *ValNo, MachineBasicBlock *MBB,
893 MachineBasicBlock *SuccMBB, MachineBasicBlock *DefMBB,
894 SmallPtrSet<MachineBasicBlock*, 8> &Visited,
895 DenseMap<MachineBasicBlock*, SmallVector<MachineOperand*, 4> > &Uses,
896 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 4> > &UseMIs,
897 SmallVector<MachineBasicBlock*, 4> &UseMBBs) {
898 if (Visited.count(MBB))
901 // If live interval is live in another successor path, then we can't process
902 // this block. But we may able to do so after all the successors have been
904 if (MBB != BarrierMBB) {
905 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
906 SE = MBB->succ_end(); SI != SE; ++SI) {
907 MachineBasicBlock *SMBB = *SI;
910 if (CurrLI->liveAt(LIs->getMBBStartIdx(SMBB)))
917 DenseMap<MachineBasicBlock*, SmallVector<MachineOperand*, 4> >::iterator
918 UMII = Uses.find(MBB);
919 if (UMII != Uses.end()) {
920 // At least one use in this mbb, lets look for the kill.
921 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 4> >::iterator
922 UMII2 = UseMIs.find(MBB);
923 if (ShrinkWrapToLastUse(MBB, ValNo, UMII->second, UMII2->second))
924 // Found a kill, shrink wrapping of this path ends here.
926 } else if (MBB == DefMBB) {
927 // There are no uses after the def.
928 MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def);
929 if (UseMBBs.empty()) {
930 // The only use must be below barrier in the barrier block. It's safe to
932 LIs->RemoveMachineInstrFromMaps(DefMI);
933 DefMI->eraseFromParent();
934 CurrLI->removeRange(ValNo->def, LIs->getMBBEndIdx(MBB)+1);
936 } else if (MBB == BarrierMBB) {
937 // Remove entire live range from start of mbb to barrier.
938 CurrLI->removeRange(LIs->getMBBStartIdx(MBB),
939 LIs->getUseIndex(BarrierIdx)+1);
941 // Remove entire live range of the mbb out of the live interval.
942 CurrLI->removeRange(LIs->getMBBStartIdx(MBB), LIs->getMBBEndIdx(MBB)+1);
946 // Reached the def mbb, stop traversing this path further.
949 // Traverse the pathes up the predecessor chains further.
950 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
951 PE = MBB->pred_end(); PI != PE; ++PI) {
952 MachineBasicBlock *Pred = *PI;
955 if (Pred == DefMBB && ValNo->hasPHIKill)
956 // Pred is the def bb and the def reaches other val#s, we must
957 // allow the value to be live out of the bb.
959 if (!CurrLI->liveAt(LIs->getMBBEndIdx(Pred)-1))
961 ShrinkWrapLiveInterval(ValNo, Pred, MBB, DefMBB, Visited,
962 Uses, UseMIs, UseMBBs);
969 void PreAllocSplitting::RepairLiveInterval(LiveInterval* CurrLI,
972 unsigned RestoreIdx) {
973 // Shrink wrap the live interval by walking up the CFG and find the
975 // Now let's find all the uses of the val#.
976 DenseMap<MachineBasicBlock*, SmallVector<MachineOperand*, 4> > Uses;
977 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 4> > UseMIs;
978 SmallPtrSet<MachineBasicBlock*, 4> Seen;
979 SmallVector<MachineBasicBlock*, 4> UseMBBs;
980 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(CurrLI->reg),
981 UE = MRI->use_end(); UI != UE; ++UI) {
982 MachineOperand &UseMO = UI.getOperand();
983 MachineInstr *UseMI = UseMO.getParent();
984 unsigned UseIdx = LIs->getInstructionIndex(UseMI);
985 LiveInterval::iterator ULR = CurrLI->FindLiveRangeContaining(UseIdx);
986 if (ULR->valno != ValNo)
988 MachineBasicBlock *UseMBB = UseMI->getParent();
989 // Remember which other mbb's use this val#.
990 if (Seen.insert(UseMBB) && UseMBB != BarrierMBB)
991 UseMBBs.push_back(UseMBB);
992 DenseMap<MachineBasicBlock*, SmallVector<MachineOperand*, 4> >::iterator
993 UMII = Uses.find(UseMBB);
994 if (UMII != Uses.end()) {
995 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 4> >::iterator
996 UMII2 = UseMIs.find(UseMBB);
997 UMII->second.push_back(&UseMO);
998 UMII2->second.insert(UseMI);
1000 SmallVector<MachineOperand*, 4> Ops;
1001 Ops.push_back(&UseMO);
1002 Uses.insert(std::make_pair(UseMBB, Ops));
1003 SmallPtrSet<MachineInstr*, 4> MIs;
1005 UseMIs.insert(std::make_pair(UseMBB, MIs));
1009 // Walk up the predecessor chains.
1010 SmallPtrSet<MachineBasicBlock*, 8> Visited;
1011 ShrinkWrapLiveInterval(ValNo, BarrierMBB, NULL, DefMI->getParent(), Visited,
1012 Uses, UseMIs, UseMBBs);
1014 // Remove live range from barrier to the restore. FIXME: Find a better
1015 // point to re-start the live interval.
1016 VNInfo* AfterValNo = UpdateRegisterInterval(ValNo,
1017 LIs->getUseIndex(BarrierIdx)+1,
1018 LIs->getDefIndex(RestoreIdx));
1020 // Attempt to renumber the new valno into a new vreg.
1021 RenumberValno(AfterValNo);
1024 /// RenumberValno - Split the given valno out into a new vreg, allowing it to
1025 /// be allocated to a different register. This function creates a new vreg,
1026 /// copies the valno and its live ranges over to the new vreg's interval,
1027 /// removes them from the old interval, and rewrites all uses and defs of
1028 /// the original reg to the new vreg within those ranges.
1029 void PreAllocSplitting::RenumberValno(VNInfo* VN) {
1030 SmallVector<VNInfo*, 4> Stack;
1031 SmallVector<VNInfo*, 4> VNsToCopy;
1032 Stack.push_back(VN);
1034 // Walk through and copy the valno we care about, and any other valnos
1035 // that are two-address redefinitions of the one we care about. These
1036 // will need to be rewritten as well. We also check for safety of the
1037 // renumbering here, by making sure that none of the valno involved has
1039 while (!Stack.empty()) {
1040 VNInfo* OldVN = Stack.back();
1043 // Bail out if we ever encounter a valno that has a PHI kill. We can't
1045 if (OldVN->hasPHIKill) return;
1047 VNsToCopy.push_back(OldVN);
1049 // Locate two-address redefinitions
1050 for (SmallVector<unsigned, 4>::iterator KI = OldVN->kills.begin(),
1051 KE = OldVN->kills.end(); KI != KE; ++KI) {
1052 MachineInstr* MI = LIs->getInstructionFromIndex(*KI);
1053 //if (!MI) continue;
1054 unsigned DefIdx = MI->findRegisterDefOperandIdx(CurrLI->reg);
1055 if (DefIdx == ~0U) continue;
1056 if (MI->isRegReDefinedByTwoAddr(DefIdx)) {
1058 CurrLI->findDefinedVNInfo(LiveIntervals::getDefIndex(*KI));
1059 Stack.push_back(NextVN);
1064 // Create the new vreg
1065 unsigned NewVReg = MRI->createVirtualRegister(MRI->getRegClass(CurrLI->reg));
1067 // Create the new live interval
1068 LiveInterval& NewLI = LIs->getOrCreateInterval(NewVReg);
1070 for (SmallVector<VNInfo*, 4>::iterator OI = VNsToCopy.begin(), OE =
1071 VNsToCopy.end(); OI != OE; ++OI) {
1072 VNInfo* OldVN = *OI;
1074 // Copy the valno over
1075 VNInfo* NewVN = NewLI.getNextValue(OldVN->def, OldVN->copy,
1076 LIs->getVNInfoAllocator());
1077 NewLI.copyValNumInfo(NewVN, OldVN);
1078 NewLI.MergeValueInAsValue(*CurrLI, OldVN, NewVN);
1080 // Remove the valno from the old interval
1081 CurrLI->removeValNo(OldVN);
1084 // Rewrite defs and uses. This is done in two stages to avoid invalidating
1085 // the reg_iterator.
1086 SmallVector<std::pair<MachineInstr*, unsigned>, 8> OpsToChange;
1088 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
1089 E = MRI->reg_end(); I != E; ++I) {
1090 MachineOperand& MO = I.getOperand();
1091 unsigned InstrIdx = LIs->getInstructionIndex(&*I);
1093 if ((MO.isUse() && NewLI.liveAt(LiveIntervals::getUseIndex(InstrIdx))) ||
1094 (MO.isDef() && NewLI.liveAt(LiveIntervals::getDefIndex(InstrIdx))))
1095 OpsToChange.push_back(std::make_pair(&*I, I.getOperandNo()));
1098 for (SmallVector<std::pair<MachineInstr*, unsigned>, 8>::iterator I =
1099 OpsToChange.begin(), E = OpsToChange.end(); I != E; ++I) {
1100 MachineInstr* Inst = I->first;
1101 unsigned OpIdx = I->second;
1102 MachineOperand& MO = Inst->getOperand(OpIdx);
1109 bool PreAllocSplitting::Rematerialize(unsigned vreg, VNInfo* ValNo,
1110 MachineInstr* DefMI,
1111 MachineBasicBlock::iterator RestorePt,
1112 unsigned RestoreIdx,
1113 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
1114 MachineBasicBlock& MBB = *RestorePt->getParent();
1116 MachineBasicBlock::iterator KillPt = BarrierMBB->end();
1117 unsigned KillIdx = 0;
1118 if (ValNo->def == ~0U || DefMI->getParent() == BarrierMBB)
1119 KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, KillIdx);
1121 KillPt = findNextEmptySlot(DefMI->getParent(), DefMI, KillIdx);
1123 if (KillPt == DefMI->getParent()->end())
1126 TII->reMaterialize(MBB, RestorePt, vreg, DefMI);
1127 LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx);
1129 if (KillPt->getParent() == BarrierMBB) {
1130 UpdateRegisterInterval(ValNo, LIs->getUseIndex(KillIdx)+1,
1131 LIs->getDefIndex(RestoreIdx));
1138 RepairLiveInterval(CurrLI, ValNo, DefMI, RestoreIdx);
1145 MachineInstr* PreAllocSplitting::FoldSpill(unsigned vreg,
1146 const TargetRegisterClass* RC,
1147 MachineInstr* DefMI,
1148 MachineInstr* Barrier,
1149 MachineBasicBlock* MBB,
1151 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
1152 MachineBasicBlock::iterator Pt = MBB->begin();
1154 // Go top down if RefsInMBB is empty.
1155 if (RefsInMBB.empty())
1158 MachineBasicBlock::iterator FoldPt = Barrier;
1159 while (&*FoldPt != DefMI && FoldPt != MBB->begin() &&
1160 !RefsInMBB.count(FoldPt))
1163 int OpIdx = FoldPt->findRegisterDefOperandIdx(vreg, false);
1167 SmallVector<unsigned, 1> Ops;
1168 Ops.push_back(OpIdx);
1170 if (!TII->canFoldMemoryOperand(FoldPt, Ops))
1173 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(vreg);
1174 if (I != IntervalSSMap.end()) {
1177 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
1181 MachineInstr* FMI = TII->foldMemoryOperand(*MBB->getParent(),
1185 LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
1186 FMI = MBB->insert(MBB->erase(FoldPt), FMI);
1189 IntervalSSMap[vreg] = SS;
1190 CurrSLI = &LSs->getOrCreateInterval(SS);
1191 if (CurrSLI->hasAtLeastOneValue())
1192 CurrSValNo = CurrSLI->getValNumInfo(0);
1194 CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
1200 /// SplitRegLiveInterval - Split (spill and restore) the given live interval
1201 /// so it would not cross the barrier that's being processed. Shrink wrap
1202 /// (minimize) the live interval to the last uses.
1203 bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
1206 // Find live range where current interval cross the barrier.
1207 LiveInterval::iterator LR =
1208 CurrLI->FindLiveRangeContaining(LIs->getUseIndex(BarrierIdx));
1209 VNInfo *ValNo = LR->valno;
1211 if (ValNo->def == ~1U) {
1212 // Defined by a dead def? How can this be?
1213 assert(0 && "Val# is defined by a dead def?");
1217 MachineInstr *DefMI = (ValNo->def != ~0U)
1218 ? LIs->getInstructionFromIndex(ValNo->def) : NULL;
1220 // Find all references in the barrier mbb.
1221 SmallPtrSet<MachineInstr*, 4> RefsInMBB;
1222 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
1223 E = MRI->reg_end(); I != E; ++I) {
1224 MachineInstr *RefMI = &*I;
1225 if (RefMI->getParent() == BarrierMBB)
1226 RefsInMBB.insert(RefMI);
1229 // Find a point to restore the value after the barrier.
1230 unsigned RestoreIndex;
1231 MachineBasicBlock::iterator RestorePt =
1232 findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB, RestoreIndex);
1233 if (RestorePt == BarrierMBB->end())
1236 if (DefMI && LIs->isReMaterializable(*LI, ValNo, DefMI))
1237 if (Rematerialize(LI->reg, ValNo, DefMI, RestorePt,
1238 RestoreIndex, RefsInMBB))
1241 // Add a spill either before the barrier or after the definition.
1242 MachineBasicBlock *DefMBB = DefMI ? DefMI->getParent() : NULL;
1243 const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg);
1244 unsigned SpillIndex = 0;
1245 MachineInstr *SpillMI = NULL;
1247 if (ValNo->def == ~0U) {
1248 // If it's defined by a phi, we must split just before the barrier.
1249 if ((SpillMI = FoldSpill(LI->reg, RC, 0, Barrier,
1250 BarrierMBB, SS, RefsInMBB))) {
1251 SpillIndex = LIs->getInstructionIndex(SpillMI);
1253 MachineBasicBlock::iterator SpillPt =
1254 findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, SpillIndex);
1255 if (SpillPt == BarrierMBB->begin())
1256 return false; // No gap to insert spill.
1259 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1260 TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
1261 SpillMI = prior(SpillPt);
1262 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1264 } else if (!IsAvailableInStack(DefMBB, CurrLI->reg, ValNo->def,
1265 RestoreIndex, SpillIndex, SS)) {
1266 // If it's already split, just restore the value. There is no need to spill
1269 return false; // Def is dead. Do nothing.
1271 if ((SpillMI = FoldSpill(LI->reg, RC, DefMI, Barrier,
1272 BarrierMBB, SS, RefsInMBB))) {
1273 SpillIndex = LIs->getInstructionIndex(SpillMI);
1275 // Check if it's possible to insert a spill after the def MI.
1276 MachineBasicBlock::iterator SpillPt;
1277 if (DefMBB == BarrierMBB) {
1278 // Add spill after the def and the last use before the barrier.
1279 SpillPt = findSpillPoint(BarrierMBB, Barrier, DefMI,
1280 RefsInMBB, SpillIndex);
1281 if (SpillPt == DefMBB->begin())
1282 return false; // No gap to insert spill.
1284 SpillPt = findNextEmptySlot(DefMBB, DefMI, SpillIndex);
1285 if (SpillPt == DefMBB->end())
1286 return false; // No gap to insert spill.
1288 // Add spill. The store instruction kills the register if def is before
1289 // the barrier in the barrier block.
1290 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1291 TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg,
1292 DefMBB == BarrierMBB, SS, RC);
1293 SpillMI = prior(SpillPt);
1294 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1298 // Remember def instruction index to spill index mapping.
1299 if (DefMI && SpillMI)
1300 Def2SpillMap[ValNo->def] = SpillIndex;
1303 TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
1304 MachineInstr *LoadMI = prior(RestorePt);
1305 LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex);
1307 // If live interval is spilled in the same block as the barrier, just
1308 // create a hole in the interval.
1310 (SpillMI && SpillMI->getParent() == BarrierMBB)) {
1311 // Update spill stack slot live interval.
1312 UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
1313 LIs->getDefIndex(RestoreIndex));
1315 UpdateRegisterInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
1316 LIs->getDefIndex(RestoreIndex));
1322 // Update spill stack slot live interval.
1323 UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
1324 LIs->getDefIndex(RestoreIndex));
1326 RepairLiveInterval(CurrLI, ValNo, DefMI, RestoreIndex);
1332 /// SplitRegLiveIntervals - Split all register live intervals that cross the
1333 /// barrier that's being processed.
1335 PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs) {
1336 // First find all the virtual registers whose live intervals are intercepted
1337 // by the current barrier.
1338 SmallVector<LiveInterval*, 8> Intervals;
1339 for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
1340 if (TII->IgnoreRegisterClassBarriers(*RC))
1342 std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
1343 for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
1344 unsigned Reg = VRs[i];
1345 if (!LIs->hasInterval(Reg))
1347 LiveInterval *LI = &LIs->getInterval(Reg);
1348 if (LI->liveAt(BarrierIdx) && !Barrier->readsRegister(Reg))
1349 // Virtual register live interval is intercepted by the barrier. We
1350 // should split and shrink wrap its interval if possible.
1351 Intervals.push_back(LI);
1355 // Process the affected live intervals.
1356 bool Change = false;
1357 while (!Intervals.empty()) {
1358 if (PreSplitLimit != -1 && (int)NumSplits == PreSplitLimit)
1360 else if (NumSplits == 4)
1362 LiveInterval *LI = Intervals.back();
1363 Intervals.pop_back();
1364 Change |= SplitRegLiveInterval(LI);
1370 bool PreAllocSplitting::createsNewJoin(LiveRange* LR,
1371 MachineBasicBlock* DefMBB,
1372 MachineBasicBlock* BarrierMBB) {
1373 if (DefMBB == BarrierMBB)
1376 if (LR->valno->hasPHIKill)
1379 unsigned MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
1380 if (LR->end < MBBEnd)
1383 MachineLoopInfo& MLI = getAnalysis<MachineLoopInfo>();
1384 if (MLI.getLoopFor(DefMBB) != MLI.getLoopFor(BarrierMBB))
1387 MachineDominatorTree& MDT = getAnalysis<MachineDominatorTree>();
1388 SmallPtrSet<MachineBasicBlock*, 4> Visited;
1389 typedef std::pair<MachineBasicBlock*,
1390 MachineBasicBlock::succ_iterator> ItPair;
1391 SmallVector<ItPair, 4> Stack;
1392 Stack.push_back(std::make_pair(BarrierMBB, BarrierMBB->succ_begin()));
1394 while (!Stack.empty()) {
1395 ItPair P = Stack.back();
1398 MachineBasicBlock* PredMBB = P.first;
1399 MachineBasicBlock::succ_iterator S = P.second;
1401 if (S == PredMBB->succ_end())
1403 else if (Visited.count(*S)) {
1404 Stack.push_back(std::make_pair(PredMBB, ++S));
1407 Stack.push_back(std::make_pair(PredMBB, S+1));
1409 MachineBasicBlock* MBB = *S;
1410 Visited.insert(MBB);
1412 if (MBB == BarrierMBB)
1415 MachineDomTreeNode* DefMDTN = MDT.getNode(DefMBB);
1416 MachineDomTreeNode* BarrierMDTN = MDT.getNode(BarrierMBB);
1417 MachineDomTreeNode* MDTN = MDT.getNode(MBB)->getIDom();
1419 if (MDTN == DefMDTN)
1421 else if (MDTN == BarrierMDTN)
1423 MDTN = MDTN->getIDom();
1426 MBBEnd = LIs->getMBBEndIdx(MBB);
1427 if (LR->end > MBBEnd)
1428 Stack.push_back(std::make_pair(MBB, MBB->succ_begin()));
1435 bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
1437 TM = &MF.getTarget();
1438 TII = TM->getInstrInfo();
1439 MFI = MF.getFrameInfo();
1440 MRI = &MF.getRegInfo();
1441 LIs = &getAnalysis<LiveIntervals>();
1442 LSs = &getAnalysis<LiveStacks>();
1444 bool MadeChange = false;
1446 // Make sure blocks are numbered in order.
1447 MF.RenumberBlocks();
1449 MachineBasicBlock *Entry = MF.begin();
1450 SmallPtrSet<MachineBasicBlock*,16> Visited;
1452 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
1453 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
1456 for (MachineBasicBlock::iterator I = BarrierMBB->begin(),
1457 E = BarrierMBB->end(); I != E; ++I) {
1459 const TargetRegisterClass **BarrierRCs =
1460 Barrier->getDesc().getRegClassBarriers();
1463 BarrierIdx = LIs->getInstructionIndex(Barrier);
1464 MadeChange |= SplitRegLiveIntervals(BarrierRCs);