1 //===-- PreAllocSplitting.cpp - Pre-allocation Interval Spltting Pass. ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine instruction level pre-register allocation
11 // live interval splitting pass. It finds live interval barriers, i.e.
12 // instructions which will kill all physical registers in certain register
13 // classes, and split all live intervals which cross the barrier.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "pre-alloc-split"
18 #include "VirtRegMap.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/ADT/DenseMap.h"
35 #include "llvm/ADT/DepthFirstIterator.h"
36 #include "llvm/ADT/SmallPtrSet.h"
37 #include "llvm/ADT/Statistic.h"
40 static cl::opt<int> PreSplitLimit("pre-split-limit", cl::init(-1), cl::Hidden);
41 static cl::opt<int> DeadSplitLimit("dead-split-limit", cl::init(-1), cl::Hidden);
42 static cl::opt<int> RestoreFoldLimit("restore-fold-limit", cl::init(-1), cl::Hidden);
44 STATISTIC(NumSplits, "Number of intervals split");
45 STATISTIC(NumRemats, "Number of intervals split by rematerialization");
46 STATISTIC(NumFolds, "Number of intervals split with spill folding");
47 STATISTIC(NumRestoreFolds, "Number of intervals split with restore folding");
48 STATISTIC(NumRenumbers, "Number of intervals renumbered into new registers");
49 STATISTIC(NumDeadSpills, "Number of dead spills removed");
52 class VISIBILITY_HIDDEN PreAllocSplitting : public MachineFunctionPass {
53 MachineFunction *CurrMF;
54 const TargetMachine *TM;
55 const TargetInstrInfo *TII;
56 const TargetRegisterInfo* TRI;
57 MachineFrameInfo *MFI;
58 MachineRegisterInfo *MRI;
63 // Barrier - Current barrier being processed.
64 MachineInstr *Barrier;
66 // BarrierMBB - Basic block where the barrier resides in.
67 MachineBasicBlock *BarrierMBB;
69 // Barrier - Current barrier index.
72 // CurrLI - Current live interval being split.
75 // CurrSLI - Current stack slot live interval.
76 LiveInterval *CurrSLI;
78 // CurrSValNo - Current val# for the stack slot live interval.
81 // IntervalSSMap - A map from live interval to spill slots.
82 DenseMap<unsigned, int> IntervalSSMap;
84 // Def2SpillMap - A map from a def instruction index to spill index.
85 DenseMap<unsigned, unsigned> Def2SpillMap;
89 PreAllocSplitting() : MachineFunctionPass(&ID) {}
91 virtual bool runOnMachineFunction(MachineFunction &MF);
93 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
94 AU.addRequired<LiveIntervals>();
95 AU.addPreserved<LiveIntervals>();
96 AU.addRequired<LiveStacks>();
97 AU.addPreserved<LiveStacks>();
98 AU.addPreserved<RegisterCoalescer>();
100 AU.addPreservedID(StrongPHIEliminationID);
102 AU.addPreservedID(PHIEliminationID);
103 AU.addRequired<MachineDominatorTree>();
104 AU.addRequired<MachineLoopInfo>();
105 AU.addRequired<VirtRegMap>();
106 AU.addPreserved<MachineDominatorTree>();
107 AU.addPreserved<MachineLoopInfo>();
108 AU.addPreserved<VirtRegMap>();
109 MachineFunctionPass::getAnalysisUsage(AU);
112 virtual void releaseMemory() {
113 IntervalSSMap.clear();
114 Def2SpillMap.clear();
117 virtual const char *getPassName() const {
118 return "Pre-Register Allocaton Live Interval Splitting";
121 /// print - Implement the dump method.
122 virtual void print(std::ostream &O, const Module* M = 0) const {
126 void print(std::ostream *O, const Module* M = 0) const {
131 MachineBasicBlock::iterator
132 findNextEmptySlot(MachineBasicBlock*, MachineInstr*,
135 MachineBasicBlock::iterator
136 findSpillPoint(MachineBasicBlock*, MachineInstr*, MachineInstr*,
137 SmallPtrSet<MachineInstr*, 4>&, unsigned&);
139 MachineBasicBlock::iterator
140 findRestorePoint(MachineBasicBlock*, MachineInstr*, unsigned,
141 SmallPtrSet<MachineInstr*, 4>&, unsigned&);
143 int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
145 bool IsAvailableInStack(MachineBasicBlock*, unsigned, unsigned, unsigned,
146 unsigned&, int&) const;
148 void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned);
150 bool SplitRegLiveInterval(LiveInterval*);
152 bool SplitRegLiveIntervals(const TargetRegisterClass **,
153 SmallPtrSet<LiveInterval*, 8>&);
155 bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB,
156 MachineBasicBlock* BarrierMBB);
157 bool Rematerialize(unsigned vreg, VNInfo* ValNo,
159 MachineBasicBlock::iterator RestorePt,
161 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
162 MachineInstr* FoldSpill(unsigned vreg, const TargetRegisterClass* RC,
164 MachineInstr* Barrier,
165 MachineBasicBlock* MBB,
167 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
168 MachineInstr* FoldRestore(unsigned vreg,
169 const TargetRegisterClass* RC,
170 MachineInstr* Barrier,
171 MachineBasicBlock* MBB,
173 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
174 void RenumberValno(VNInfo* VN);
175 void ReconstructLiveInterval(LiveInterval* LI);
176 bool removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split);
177 unsigned getNumberOfNonSpills(SmallPtrSet<MachineInstr*, 4>& MIs,
178 unsigned Reg, int FrameIndex, bool& TwoAddr);
179 VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator Use,
180 MachineBasicBlock* MBB, LiveInterval* LI,
181 SmallPtrSet<MachineInstr*, 4>& Visited,
182 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
183 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
184 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
185 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
186 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
187 bool IsTopLevel, bool IsIntraBlock);
188 VNInfo* PerformPHIConstructionFallBack(MachineBasicBlock::iterator Use,
189 MachineBasicBlock* MBB, LiveInterval* LI,
190 SmallPtrSet<MachineInstr*, 4>& Visited,
191 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
192 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
193 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
194 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
195 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
196 bool IsTopLevel, bool IsIntraBlock);
198 } // end anonymous namespace
200 char PreAllocSplitting::ID = 0;
202 static RegisterPass<PreAllocSplitting>
203 X("pre-alloc-splitting", "Pre-Register Allocation Live Interval Splitting");
205 const PassInfo *const llvm::PreAllocSplittingID = &X;
208 /// findNextEmptySlot - Find a gap after the given machine instruction in the
209 /// instruction index map. If there isn't one, return end().
210 MachineBasicBlock::iterator
211 PreAllocSplitting::findNextEmptySlot(MachineBasicBlock *MBB, MachineInstr *MI,
212 unsigned &SpotIndex) {
213 MachineBasicBlock::iterator MII = MI;
214 if (++MII != MBB->end()) {
215 unsigned Index = LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
224 /// findSpillPoint - Find a gap as far away from the given MI that's suitable
225 /// for spilling the current live interval. The index must be before any
226 /// defs and uses of the live interval register in the mbb. Return begin() if
228 MachineBasicBlock::iterator
229 PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
231 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
232 unsigned &SpillIndex) {
233 MachineBasicBlock::iterator Pt = MBB->begin();
235 MachineBasicBlock::iterator MII = MI;
236 MachineBasicBlock::iterator EndPt = DefMI
237 ? MachineBasicBlock::iterator(DefMI) : MBB->begin();
239 while (MII != EndPt && !RefsInMBB.count(MII) &&
240 MII->getOpcode() != TRI->getCallFrameSetupOpcode())
242 if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
244 while (MII != EndPt && !RefsInMBB.count(MII)) {
245 unsigned Index = LIs->getInstructionIndex(MII);
247 // We can't insert the spill between the barrier (a call), and its
248 // corresponding call frame setup.
249 if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) {
250 while (MII->getOpcode() != TRI->getCallFrameSetupOpcode()) {
257 } else if (LIs->hasGapBeforeInstr(Index)) {
259 SpillIndex = LIs->findGapBeforeInstr(Index, true);
262 if (RefsInMBB.count(MII))
272 /// findRestorePoint - Find a gap in the instruction index map that's suitable
273 /// for restoring the current live interval value. The index must be before any
274 /// uses of the live interval register in the mbb. Return end() if none is
276 MachineBasicBlock::iterator
277 PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
279 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
280 unsigned &RestoreIndex) {
281 // FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
282 // begin index accordingly.
283 MachineBasicBlock::iterator Pt = MBB->end();
284 MachineBasicBlock::iterator EndPt = MBB->getFirstTerminator();
286 // We start at the call, so walk forward until we find the call frame teardown
287 // since we can't insert restores before that. Bail if we encounter a use
289 MachineBasicBlock::iterator MII = MI;
290 if (MII == EndPt) return Pt;
292 while (MII != EndPt && !RefsInMBB.count(MII) &&
293 MII->getOpcode() != TRI->getCallFrameDestroyOpcode())
295 if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
298 // FIXME: Limit the number of instructions to examine to reduce
300 while (MII != EndPt) {
301 unsigned Index = LIs->getInstructionIndex(MII);
304 unsigned Gap = LIs->findGapBeforeInstr(Index);
306 // We can't insert a restore between the barrier (a call) and its
307 // corresponding call frame teardown.
308 if (MII->getOpcode() == TRI->getCallFrameSetupOpcode()) {
310 if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
312 } while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode());
318 if (RefsInMBB.count(MII))
327 /// CreateSpillStackSlot - Create a stack slot for the live interval being
328 /// split. If the live interval was previously split, just reuse the same
330 int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
331 const TargetRegisterClass *RC) {
333 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
334 if (I != IntervalSSMap.end()) {
337 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
338 IntervalSSMap[Reg] = SS;
341 // Create live interval for stack slot.
342 CurrSLI = &LSs->getOrCreateInterval(SS);
343 if (CurrSLI->hasAtLeastOneValue())
344 CurrSValNo = CurrSLI->getValNumInfo(0);
346 CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
350 /// IsAvailableInStack - Return true if register is available in a split stack
351 /// slot at the specified index.
353 PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
354 unsigned Reg, unsigned DefIndex,
355 unsigned RestoreIndex, unsigned &SpillIndex,
360 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
361 if (I == IntervalSSMap.end())
363 DenseMap<unsigned, unsigned>::iterator II = Def2SpillMap.find(DefIndex);
364 if (II == Def2SpillMap.end())
367 // If last spill of def is in the same mbb as barrier mbb (where restore will
368 // be), make sure it's not below the intended restore index.
369 // FIXME: Undo the previous spill?
370 assert(LIs->getMBBFromIndex(II->second) == DefMBB);
371 if (DefMBB == BarrierMBB && II->second >= RestoreIndex)
375 SpillIndex = II->second;
379 /// UpdateSpillSlotInterval - Given the specified val# of the register live
380 /// interval being split, and the spill and restore indicies, update the live
381 /// interval of the spill stack slot.
383 PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
384 unsigned RestoreIndex) {
385 assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
386 "Expect restore in the barrier mbb");
388 MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
389 if (MBB == BarrierMBB) {
390 // Intra-block spill + restore. We are done.
391 LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo);
392 CurrSLI->addRange(SLR);
396 SmallPtrSet<MachineBasicBlock*, 4> Processed;
397 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
398 LiveRange SLR(SpillIndex, EndIdx+1, CurrSValNo);
399 CurrSLI->addRange(SLR);
400 Processed.insert(MBB);
402 // Start from the spill mbb, figure out the extend of the spill slot's
404 SmallVector<MachineBasicBlock*, 4> WorkList;
405 const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
406 if (LR->end > EndIdx)
407 // If live range extend beyond end of mbb, add successors to work list.
408 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
409 SE = MBB->succ_end(); SI != SE; ++SI)
410 WorkList.push_back(*SI);
412 while (!WorkList.empty()) {
413 MachineBasicBlock *MBB = WorkList.back();
415 if (Processed.count(MBB))
417 unsigned Idx = LIs->getMBBStartIdx(MBB);
418 LR = CurrLI->getLiveRangeContaining(Idx);
419 if (LR && LR->valno == ValNo) {
420 EndIdx = LIs->getMBBEndIdx(MBB);
421 if (Idx <= RestoreIndex && RestoreIndex < EndIdx) {
422 // Spill slot live interval stops at the restore.
423 LiveRange SLR(Idx, RestoreIndex, CurrSValNo);
424 CurrSLI->addRange(SLR);
425 } else if (LR->end > EndIdx) {
426 // Live range extends beyond end of mbb, process successors.
427 LiveRange SLR(Idx, EndIdx+1, CurrSValNo);
428 CurrSLI->addRange(SLR);
429 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
430 SE = MBB->succ_end(); SI != SE; ++SI)
431 WorkList.push_back(*SI);
433 LiveRange SLR(Idx, LR->end, CurrSValNo);
434 CurrSLI->addRange(SLR);
436 Processed.insert(MBB);
441 /// PerformPHIConstruction - From properly set up use and def lists, use a PHI
442 /// construction algorithm to compute the ranges and valnos for an interval.
444 PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI,
445 MachineBasicBlock* MBB, LiveInterval* LI,
446 SmallPtrSet<MachineInstr*, 4>& Visited,
447 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
448 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
449 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
450 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
451 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
452 bool IsTopLevel, bool IsIntraBlock) {
453 // Return memoized result if it's available.
454 if (IsTopLevel && Visited.count(UseI) && NewVNs.count(UseI))
456 else if (!IsTopLevel && IsIntraBlock && NewVNs.count(UseI))
458 else if (!IsIntraBlock && LiveOut.count(MBB))
461 // Check if our block contains any uses or defs.
462 bool ContainsDefs = Defs.count(MBB);
463 bool ContainsUses = Uses.count(MBB);
467 // Enumerate the cases of use/def contaning blocks.
468 if (!ContainsDefs && !ContainsUses) {
469 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses,
470 NewVNs, LiveOut, Phis,
471 IsTopLevel, IsIntraBlock);
472 } else if (ContainsDefs && !ContainsUses) {
473 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
475 // Search for the def in this block. If we don't find it before the
476 // instruction we care about, go to the fallback case. Note that that
477 // should never happen: this cannot be intrablock, so use should
478 // always be an end() iterator.
479 assert(UseI == MBB->end() && "No use marked in intrablock");
481 MachineBasicBlock::iterator Walker = UseI;
483 while (Walker != MBB->begin()) {
484 if (BlockDefs.count(Walker))
489 // Once we've found it, extend its VNInfo to our instruction.
490 unsigned DefIndex = LIs->getInstructionIndex(Walker);
491 DefIndex = LiveIntervals::getDefIndex(DefIndex);
492 unsigned EndIndex = LIs->getMBBEndIdx(MBB);
494 RetVNI = NewVNs[Walker];
495 LI->addRange(LiveRange(DefIndex, EndIndex+1, RetVNI));
496 } else if (!ContainsDefs && ContainsUses) {
497 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
499 // Search for the use in this block that precedes the instruction we care
500 // about, going to the fallback case if we don't find it.
501 if (UseI == MBB->begin())
502 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
503 Uses, NewVNs, LiveOut, Phis,
504 IsTopLevel, IsIntraBlock);
506 MachineBasicBlock::iterator Walker = UseI;
509 while (Walker != MBB->begin()) {
510 if (BlockUses.count(Walker)) {
517 // Must check begin() too.
519 if (BlockUses.count(Walker))
522 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
523 Uses, NewVNs, LiveOut, Phis,
524 IsTopLevel, IsIntraBlock);
527 unsigned UseIndex = LIs->getInstructionIndex(Walker);
528 UseIndex = LiveIntervals::getUseIndex(UseIndex);
529 unsigned EndIndex = 0;
531 EndIndex = LIs->getInstructionIndex(UseI);
532 EndIndex = LiveIntervals::getUseIndex(EndIndex);
534 EndIndex = LIs->getMBBEndIdx(MBB);
536 // Now, recursively phi construct the VNInfo for the use we found,
537 // and then extend it to include the instruction we care about
538 RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
539 NewVNs, LiveOut, Phis, false, true);
541 LI->addRange(LiveRange(UseIndex, EndIndex+1, RetVNI));
543 // FIXME: Need to set kills properly for inter-block stuff.
544 if (LI->isKill(RetVNI, UseIndex)) LI->removeKill(RetVNI, UseIndex);
546 LI->addKill(RetVNI, EndIndex);
547 } else if (ContainsDefs && ContainsUses) {
548 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
549 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
551 // This case is basically a merging of the two preceding case, with the
552 // special note that checking for defs must take precedence over checking
553 // for uses, because of two-address instructions.
555 if (UseI == MBB->begin())
556 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses,
557 NewVNs, LiveOut, Phis,
558 IsTopLevel, IsIntraBlock);
560 MachineBasicBlock::iterator Walker = UseI;
562 bool foundDef = false;
563 bool foundUse = false;
564 while (Walker != MBB->begin()) {
565 if (BlockDefs.count(Walker)) {
568 } else if (BlockUses.count(Walker)) {
575 // Must check begin() too.
576 if (!foundDef && !foundUse) {
577 if (BlockDefs.count(Walker))
579 else if (BlockUses.count(Walker))
582 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
583 Uses, NewVNs, LiveOut, Phis,
584 IsTopLevel, IsIntraBlock);
587 unsigned StartIndex = LIs->getInstructionIndex(Walker);
588 StartIndex = foundDef ? LiveIntervals::getDefIndex(StartIndex) :
589 LiveIntervals::getUseIndex(StartIndex);
590 unsigned EndIndex = 0;
592 EndIndex = LIs->getInstructionIndex(UseI);
593 EndIndex = LiveIntervals::getUseIndex(EndIndex);
595 EndIndex = LIs->getMBBEndIdx(MBB);
598 RetVNI = NewVNs[Walker];
600 RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
601 NewVNs, LiveOut, Phis, false, true);
603 LI->addRange(LiveRange(StartIndex, EndIndex+1, RetVNI));
605 if (foundUse && LI->isKill(RetVNI, StartIndex))
606 LI->removeKill(RetVNI, StartIndex);
608 LI->addKill(RetVNI, EndIndex);
612 // Memoize results so we don't have to recompute them.
613 if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
615 if (!NewVNs.count(UseI))
616 NewVNs[UseI] = RetVNI;
617 Visited.insert(UseI);
623 /// PerformPHIConstructionFallBack - PerformPHIConstruction fall back path.
626 PreAllocSplitting::PerformPHIConstructionFallBack(MachineBasicBlock::iterator UseI,
627 MachineBasicBlock* MBB, LiveInterval* LI,
628 SmallPtrSet<MachineInstr*, 4>& Visited,
629 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
630 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
631 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
632 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
633 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
634 bool IsTopLevel, bool IsIntraBlock) {
635 // NOTE: Because this is the fallback case from other cases, we do NOT
636 // assume that we are not intrablock here.
637 if (Phis.count(MBB)) return Phis[MBB];
639 unsigned StartIndex = LIs->getMBBStartIdx(MBB);
640 VNInfo *RetVNI = Phis[MBB] = LI->getNextValue(~0U, /*FIXME*/ 0,
641 LIs->getVNInfoAllocator());
642 if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
644 // If there are no uses or defs between our starting point and the
645 // beginning of the block, then recursive perform phi construction
646 // on our predecessors.
647 DenseMap<MachineBasicBlock*, VNInfo*> IncomingVNs;
648 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
649 PE = MBB->pred_end(); PI != PE; ++PI) {
650 VNInfo* Incoming = PerformPHIConstruction((*PI)->end(), *PI, LI,
651 Visited, Defs, Uses, NewVNs,
652 LiveOut, Phis, false, false);
654 IncomingVNs[*PI] = Incoming;
657 if (MBB->pred_size() == 1 && !RetVNI->hasPHIKill) {
658 VNInfo* OldVN = RetVNI;
659 VNInfo* NewVN = IncomingVNs.begin()->second;
660 VNInfo* MergedVN = LI->MergeValueNumberInto(OldVN, NewVN);
661 if (MergedVN == OldVN) std::swap(OldVN, NewVN);
663 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator LOI = LiveOut.begin(),
664 LOE = LiveOut.end(); LOI != LOE; ++LOI)
665 if (LOI->second == OldVN)
666 LOI->second = MergedVN;
667 for (DenseMap<MachineInstr*, VNInfo*>::iterator NVI = NewVNs.begin(),
668 NVE = NewVNs.end(); NVI != NVE; ++NVI)
669 if (NVI->second == OldVN)
670 NVI->second = MergedVN;
671 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator PI = Phis.begin(),
672 PE = Phis.end(); PI != PE; ++PI)
673 if (PI->second == OldVN)
674 PI->second = MergedVN;
677 // Otherwise, merge the incoming VNInfos with a phi join. Create a new
678 // VNInfo to represent the joined value.
679 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator I =
680 IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) {
681 I->second->hasPHIKill = true;
682 unsigned KillIndex = LIs->getMBBEndIdx(I->first);
683 if (!LiveInterval::isKill(I->second, KillIndex))
684 LI->addKill(I->second, KillIndex);
688 unsigned EndIndex = 0;
690 EndIndex = LIs->getInstructionIndex(UseI);
691 EndIndex = LiveIntervals::getUseIndex(EndIndex);
693 EndIndex = LIs->getMBBEndIdx(MBB);
694 LI->addRange(LiveRange(StartIndex, EndIndex+1, RetVNI));
696 LI->addKill(RetVNI, EndIndex);
698 // Memoize results so we don't have to recompute them.
700 LiveOut[MBB] = RetVNI;
702 if (!NewVNs.count(UseI))
703 NewVNs[UseI] = RetVNI;
704 Visited.insert(UseI);
710 /// ReconstructLiveInterval - Recompute a live interval from scratch.
711 void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) {
712 BumpPtrAllocator& Alloc = LIs->getVNInfoAllocator();
714 // Clear the old ranges and valnos;
717 // Cache the uses and defs of the register
718 typedef DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> > RegMap;
721 // Keep track of the new VNs we're creating.
722 DenseMap<MachineInstr*, VNInfo*> NewVNs;
723 SmallPtrSet<VNInfo*, 2> PhiVNs;
725 // Cache defs, and create a new VNInfo for each def.
726 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
727 DE = MRI->def_end(); DI != DE; ++DI) {
728 Defs[(*DI).getParent()].insert(&*DI);
730 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
731 DefIdx = LiveIntervals::getDefIndex(DefIdx);
733 VNInfo* NewVN = LI->getNextValue(DefIdx, 0, Alloc);
735 // If the def is a move, set the copy field.
736 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
737 if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
738 if (DstReg == LI->reg)
741 NewVNs[&*DI] = NewVN;
744 // Cache uses as a separate pass from actually processing them.
745 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
746 UE = MRI->use_end(); UI != UE; ++UI)
747 Uses[(*UI).getParent()].insert(&*UI);
749 // Now, actually process every use and use a phi construction algorithm
750 // to walk from it to its reaching definitions, building VNInfos along
752 DenseMap<MachineBasicBlock*, VNInfo*> LiveOut;
753 DenseMap<MachineBasicBlock*, VNInfo*> Phis;
754 SmallPtrSet<MachineInstr*, 4> Visited;
755 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
756 UE = MRI->use_end(); UI != UE; ++UI) {
757 PerformPHIConstruction(&*UI, UI->getParent(), LI, Visited, Defs,
758 Uses, NewVNs, LiveOut, Phis, true, true);
761 // Add ranges for dead defs
762 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
763 DE = MRI->def_end(); DI != DE; ++DI) {
764 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
765 DefIdx = LiveIntervals::getDefIndex(DefIdx);
767 if (LI->liveAt(DefIdx)) continue;
769 VNInfo* DeadVN = NewVNs[&*DI];
770 LI->addRange(LiveRange(DefIdx, DefIdx+1, DeadVN));
771 LI->addKill(DeadVN, DefIdx);
775 /// RenumberValno - Split the given valno out into a new vreg, allowing it to
776 /// be allocated to a different register. This function creates a new vreg,
777 /// copies the valno and its live ranges over to the new vreg's interval,
778 /// removes them from the old interval, and rewrites all uses and defs of
779 /// the original reg to the new vreg within those ranges.
780 void PreAllocSplitting::RenumberValno(VNInfo* VN) {
781 SmallVector<VNInfo*, 4> Stack;
782 SmallVector<VNInfo*, 4> VNsToCopy;
785 // Walk through and copy the valno we care about, and any other valnos
786 // that are two-address redefinitions of the one we care about. These
787 // will need to be rewritten as well. We also check for safety of the
788 // renumbering here, by making sure that none of the valno involved has
790 while (!Stack.empty()) {
791 VNInfo* OldVN = Stack.back();
794 // Bail out if we ever encounter a valno that has a PHI kill. We can't
796 if (OldVN->hasPHIKill) return;
798 VNsToCopy.push_back(OldVN);
800 // Locate two-address redefinitions
801 for (SmallVector<unsigned, 4>::iterator KI = OldVN->kills.begin(),
802 KE = OldVN->kills.end(); KI != KE; ++KI) {
803 MachineInstr* MI = LIs->getInstructionFromIndex(*KI);
804 unsigned DefIdx = MI->findRegisterDefOperandIdx(CurrLI->reg);
805 if (DefIdx == ~0U) continue;
806 if (MI->isRegTiedToUseOperand(DefIdx)) {
808 CurrLI->findDefinedVNInfo(LiveIntervals::getDefIndex(*KI));
809 if (NextVN == OldVN) continue;
810 Stack.push_back(NextVN);
815 // Create the new vreg
816 unsigned NewVReg = MRI->createVirtualRegister(MRI->getRegClass(CurrLI->reg));
818 // Create the new live interval
819 LiveInterval& NewLI = LIs->getOrCreateInterval(NewVReg);
821 for (SmallVector<VNInfo*, 4>::iterator OI = VNsToCopy.begin(), OE =
822 VNsToCopy.end(); OI != OE; ++OI) {
825 // Copy the valno over
826 VNInfo* NewVN = NewLI.getNextValue(OldVN->def, OldVN->copy,
827 LIs->getVNInfoAllocator());
828 NewLI.copyValNumInfo(NewVN, OldVN);
829 NewLI.MergeValueInAsValue(*CurrLI, OldVN, NewVN);
831 // Remove the valno from the old interval
832 CurrLI->removeValNo(OldVN);
835 // Rewrite defs and uses. This is done in two stages to avoid invalidating
837 SmallVector<std::pair<MachineInstr*, unsigned>, 8> OpsToChange;
839 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
840 E = MRI->reg_end(); I != E; ++I) {
841 MachineOperand& MO = I.getOperand();
842 unsigned InstrIdx = LIs->getInstructionIndex(&*I);
844 if ((MO.isUse() && NewLI.liveAt(LiveIntervals::getUseIndex(InstrIdx))) ||
845 (MO.isDef() && NewLI.liveAt(LiveIntervals::getDefIndex(InstrIdx))))
846 OpsToChange.push_back(std::make_pair(&*I, I.getOperandNo()));
849 for (SmallVector<std::pair<MachineInstr*, unsigned>, 8>::iterator I =
850 OpsToChange.begin(), E = OpsToChange.end(); I != E; ++I) {
851 MachineInstr* Inst = I->first;
852 unsigned OpIdx = I->second;
853 MachineOperand& MO = Inst->getOperand(OpIdx);
857 // Grow the VirtRegMap, since we've created a new vreg.
860 // The renumbered vreg shares a stack slot with the old register.
861 if (IntervalSSMap.count(CurrLI->reg))
862 IntervalSSMap[NewVReg] = IntervalSSMap[CurrLI->reg];
867 bool PreAllocSplitting::Rematerialize(unsigned vreg, VNInfo* ValNo,
869 MachineBasicBlock::iterator RestorePt,
871 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
872 MachineBasicBlock& MBB = *RestorePt->getParent();
874 MachineBasicBlock::iterator KillPt = BarrierMBB->end();
875 unsigned KillIdx = 0;
876 if (ValNo->def == ~0U || DefMI->getParent() == BarrierMBB)
877 KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, KillIdx);
879 KillPt = findNextEmptySlot(DefMI->getParent(), DefMI, KillIdx);
881 if (KillPt == DefMI->getParent()->end())
884 TII->reMaterialize(MBB, RestorePt, vreg, DefMI);
885 LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx);
887 ReconstructLiveInterval(CurrLI);
888 unsigned RematIdx = LIs->getInstructionIndex(prior(RestorePt));
889 RematIdx = LiveIntervals::getDefIndex(RematIdx);
890 RenumberValno(CurrLI->findDefinedVNInfo(RematIdx));
897 MachineInstr* PreAllocSplitting::FoldSpill(unsigned vreg,
898 const TargetRegisterClass* RC,
900 MachineInstr* Barrier,
901 MachineBasicBlock* MBB,
903 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
904 MachineBasicBlock::iterator Pt = MBB->begin();
906 // Go top down if RefsInMBB is empty.
907 if (RefsInMBB.empty())
910 MachineBasicBlock::iterator FoldPt = Barrier;
911 while (&*FoldPt != DefMI && FoldPt != MBB->begin() &&
912 !RefsInMBB.count(FoldPt))
915 int OpIdx = FoldPt->findRegisterDefOperandIdx(vreg, false);
919 SmallVector<unsigned, 1> Ops;
920 Ops.push_back(OpIdx);
922 if (!TII->canFoldMemoryOperand(FoldPt, Ops))
925 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(vreg);
926 if (I != IntervalSSMap.end()) {
929 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
933 MachineInstr* FMI = TII->foldMemoryOperand(*MBB->getParent(),
937 LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
938 FMI = MBB->insert(MBB->erase(FoldPt), FMI);
941 IntervalSSMap[vreg] = SS;
942 CurrSLI = &LSs->getOrCreateInterval(SS);
943 if (CurrSLI->hasAtLeastOneValue())
944 CurrSValNo = CurrSLI->getValNumInfo(0);
946 CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
952 MachineInstr* PreAllocSplitting::FoldRestore(unsigned vreg,
953 const TargetRegisterClass* RC,
954 MachineInstr* Barrier,
955 MachineBasicBlock* MBB,
957 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
958 if ((int)RestoreFoldLimit != -1 && RestoreFoldLimit == (int)NumRestoreFolds)
961 // Go top down if RefsInMBB is empty.
962 if (RefsInMBB.empty())
965 // Can't fold a restore between a call stack setup and teardown.
966 MachineBasicBlock::iterator FoldPt = Barrier;
968 // Advance from barrier to call frame teardown.
969 while (FoldPt != MBB->getFirstTerminator() &&
970 FoldPt->getOpcode() != TRI->getCallFrameDestroyOpcode()) {
971 if (RefsInMBB.count(FoldPt))
977 if (FoldPt == MBB->getFirstTerminator())
982 // Now find the restore point.
983 while (FoldPt != MBB->getFirstTerminator() && !RefsInMBB.count(FoldPt)) {
984 if (FoldPt->getOpcode() == TRI->getCallFrameSetupOpcode()) {
985 while (FoldPt != MBB->getFirstTerminator() &&
986 FoldPt->getOpcode() != TRI->getCallFrameDestroyOpcode()) {
987 if (RefsInMBB.count(FoldPt))
993 if (FoldPt == MBB->getFirstTerminator())
1000 if (FoldPt == MBB->getFirstTerminator())
1003 int OpIdx = FoldPt->findRegisterUseOperandIdx(vreg, true);
1007 SmallVector<unsigned, 1> Ops;
1008 Ops.push_back(OpIdx);
1010 if (!TII->canFoldMemoryOperand(FoldPt, Ops))
1013 MachineInstr* FMI = TII->foldMemoryOperand(*MBB->getParent(),
1017 LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
1018 FMI = MBB->insert(MBB->erase(FoldPt), FMI);
1025 /// SplitRegLiveInterval - Split (spill and restore) the given live interval
1026 /// so it would not cross the barrier that's being processed. Shrink wrap
1027 /// (minimize) the live interval to the last uses.
1028 bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
1031 // Find live range where current interval cross the barrier.
1032 LiveInterval::iterator LR =
1033 CurrLI->FindLiveRangeContaining(LIs->getUseIndex(BarrierIdx));
1034 VNInfo *ValNo = LR->valno;
1036 if (ValNo->def == ~1U) {
1037 // Defined by a dead def? How can this be?
1038 assert(0 && "Val# is defined by a dead def?");
1042 MachineInstr *DefMI = (ValNo->def != ~0U)
1043 ? LIs->getInstructionFromIndex(ValNo->def) : NULL;
1045 // If this would create a new join point, do not split.
1046 if (DefMI && createsNewJoin(LR, DefMI->getParent(), Barrier->getParent()))
1049 // Find all references in the barrier mbb.
1050 SmallPtrSet<MachineInstr*, 4> RefsInMBB;
1051 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
1052 E = MRI->reg_end(); I != E; ++I) {
1053 MachineInstr *RefMI = &*I;
1054 if (RefMI->getParent() == BarrierMBB)
1055 RefsInMBB.insert(RefMI);
1058 // Find a point to restore the value after the barrier.
1059 unsigned RestoreIndex = 0;
1060 MachineBasicBlock::iterator RestorePt =
1061 findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB, RestoreIndex);
1062 if (RestorePt == BarrierMBB->end())
1065 if (DefMI && LIs->isReMaterializable(*LI, ValNo, DefMI))
1066 if (Rematerialize(LI->reg, ValNo, DefMI, RestorePt,
1067 RestoreIndex, RefsInMBB))
1070 // Add a spill either before the barrier or after the definition.
1071 MachineBasicBlock *DefMBB = DefMI ? DefMI->getParent() : NULL;
1072 const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg);
1073 unsigned SpillIndex = 0;
1074 MachineInstr *SpillMI = NULL;
1076 if (ValNo->def == ~0U) {
1077 // If it's defined by a phi, we must split just before the barrier.
1078 if ((SpillMI = FoldSpill(LI->reg, RC, 0, Barrier,
1079 BarrierMBB, SS, RefsInMBB))) {
1080 SpillIndex = LIs->getInstructionIndex(SpillMI);
1082 MachineBasicBlock::iterator SpillPt =
1083 findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, SpillIndex);
1084 if (SpillPt == BarrierMBB->begin())
1085 return false; // No gap to insert spill.
1088 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1089 TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
1090 SpillMI = prior(SpillPt);
1091 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1093 } else if (!IsAvailableInStack(DefMBB, CurrLI->reg, ValNo->def,
1094 RestoreIndex, SpillIndex, SS)) {
1095 // If it's already split, just restore the value. There is no need to spill
1098 return false; // Def is dead. Do nothing.
1100 if ((SpillMI = FoldSpill(LI->reg, RC, DefMI, Barrier,
1101 BarrierMBB, SS, RefsInMBB))) {
1102 SpillIndex = LIs->getInstructionIndex(SpillMI);
1104 // Check if it's possible to insert a spill after the def MI.
1105 MachineBasicBlock::iterator SpillPt;
1106 if (DefMBB == BarrierMBB) {
1107 // Add spill after the def and the last use before the barrier.
1108 SpillPt = findSpillPoint(BarrierMBB, Barrier, DefMI,
1109 RefsInMBB, SpillIndex);
1110 if (SpillPt == DefMBB->begin())
1111 return false; // No gap to insert spill.
1113 SpillPt = findNextEmptySlot(DefMBB, DefMI, SpillIndex);
1114 if (SpillPt == DefMBB->end())
1115 return false; // No gap to insert spill.
1117 // Add spill. The store instruction kills the register if def is before
1118 // the barrier in the barrier block.
1119 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1120 TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg,
1121 DefMBB == BarrierMBB, SS, RC);
1122 SpillMI = prior(SpillPt);
1123 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1127 // Remember def instruction index to spill index mapping.
1128 if (DefMI && SpillMI)
1129 Def2SpillMap[ValNo->def] = SpillIndex;
1132 bool FoldedRestore = false;
1133 if (MachineInstr* LMI = FoldRestore(CurrLI->reg, RC, Barrier,
1134 BarrierMBB, SS, RefsInMBB)) {
1136 RestoreIndex = LIs->getInstructionIndex(RestorePt);
1137 FoldedRestore = true;
1139 TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
1140 MachineInstr *LoadMI = prior(RestorePt);
1141 LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex);
1144 // Update spill stack slot live interval.
1145 UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
1146 LIs->getDefIndex(RestoreIndex));
1148 ReconstructLiveInterval(CurrLI);
1150 if (!FoldedRestore) {
1151 unsigned RestoreIdx = LIs->getInstructionIndex(prior(RestorePt));
1152 RestoreIdx = LiveIntervals::getDefIndex(RestoreIdx);
1153 RenumberValno(CurrLI->findDefinedVNInfo(RestoreIdx));
1160 /// SplitRegLiveIntervals - Split all register live intervals that cross the
1161 /// barrier that's being processed.
1163 PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs,
1164 SmallPtrSet<LiveInterval*, 8>& Split) {
1165 // First find all the virtual registers whose live intervals are intercepted
1166 // by the current barrier.
1167 SmallVector<LiveInterval*, 8> Intervals;
1168 for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
1169 // FIXME: If it's not safe to move any instruction that defines the barrier
1170 // register class, then it means there are some special dependencies which
1171 // codegen is not modelling. Ignore these barriers for now.
1172 if (!TII->isSafeToMoveRegClassDefs(*RC))
1174 std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
1175 for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
1176 unsigned Reg = VRs[i];
1177 if (!LIs->hasInterval(Reg))
1179 LiveInterval *LI = &LIs->getInterval(Reg);
1180 if (LI->liveAt(BarrierIdx) && !Barrier->readsRegister(Reg))
1181 // Virtual register live interval is intercepted by the barrier. We
1182 // should split and shrink wrap its interval if possible.
1183 Intervals.push_back(LI);
1187 // Process the affected live intervals.
1188 bool Change = false;
1189 while (!Intervals.empty()) {
1190 if (PreSplitLimit != -1 && (int)NumSplits == PreSplitLimit)
1192 else if (NumSplits == 4)
1194 LiveInterval *LI = Intervals.back();
1195 Intervals.pop_back();
1196 bool result = SplitRegLiveInterval(LI);
1197 if (result) Split.insert(LI);
1204 unsigned PreAllocSplitting::getNumberOfNonSpills(
1205 SmallPtrSet<MachineInstr*, 4>& MIs,
1206 unsigned Reg, int FrameIndex,
1207 bool& FeedsTwoAddr) {
1208 unsigned NonSpills = 0;
1209 for (SmallPtrSet<MachineInstr*, 4>::iterator UI = MIs.begin(), UE = MIs.end();
1211 int StoreFrameIndex;
1212 unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1213 if (StoreVReg != Reg || StoreFrameIndex != FrameIndex)
1216 int DefIdx = (*UI)->findRegisterDefOperandIdx(Reg);
1217 if (DefIdx != -1 && (*UI)->isRegTiedToUseOperand(DefIdx))
1218 FeedsTwoAddr = true;
1224 /// removeDeadSpills - After doing splitting, filter through all intervals we've
1225 /// split, and see if any of the spills are unnecessary. If so, remove them.
1226 bool PreAllocSplitting::removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split) {
1227 bool changed = false;
1229 // Walk over all of the live intervals that were touched by the splitter,
1230 // and see if we can do any DCE and/or folding.
1231 for (SmallPtrSet<LiveInterval*, 8>::iterator LI = split.begin(),
1232 LE = split.end(); LI != LE; ++LI) {
1233 DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> > VNUseCount;
1235 // First, collect all the uses of the vreg, and sort them by their
1236 // reaching definition (VNInfo).
1237 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin((*LI)->reg),
1238 UE = MRI->use_end(); UI != UE; ++UI) {
1239 unsigned index = LIs->getInstructionIndex(&*UI);
1240 index = LiveIntervals::getUseIndex(index);
1242 const LiveRange* LR = (*LI)->getLiveRangeContaining(index);
1243 VNUseCount[LR->valno].insert(&*UI);
1246 // Now, take the definitions (VNInfo's) one at a time and try to DCE
1247 // and/or fold them away.
1248 for (LiveInterval::vni_iterator VI = (*LI)->vni_begin(),
1249 VE = (*LI)->vni_end(); VI != VE; ++VI) {
1251 if (DeadSplitLimit != -1 && (int)NumDeadSpills == DeadSplitLimit)
1254 VNInfo* CurrVN = *VI;
1256 // We don't currently try to handle definitions with PHI kills, because
1257 // it would involve processing more than one VNInfo at once.
1258 if (CurrVN->hasPHIKill) continue;
1260 // We also don't try to handle the results of PHI joins, since there's
1261 // no defining instruction to analyze.
1262 unsigned DefIdx = CurrVN->def;
1263 if (DefIdx == ~0U || DefIdx == ~1U) continue;
1265 // We're only interested in eliminating cruft introduced by the splitter,
1266 // is of the form load-use or load-use-store. First, check that the
1267 // definition is a load, and remember what stack slot we loaded it from.
1268 MachineInstr* DefMI = LIs->getInstructionFromIndex(DefIdx);
1270 if (!TII->isLoadFromStackSlot(DefMI, FrameIndex)) continue;
1272 // If the definition has no uses at all, just DCE it.
1273 if (VNUseCount[CurrVN].size() == 0) {
1274 LIs->RemoveMachineInstrFromMaps(DefMI);
1275 (*LI)->removeValNo(CurrVN);
1276 DefMI->eraseFromParent();
1277 VNUseCount.erase(CurrVN);
1283 // Second, get the number of non-store uses of the definition, as well as
1284 // a flag indicating whether it feeds into a later two-address definition.
1285 bool FeedsTwoAddr = false;
1286 unsigned NonSpillCount = getNumberOfNonSpills(VNUseCount[CurrVN],
1287 (*LI)->reg, FrameIndex,
1290 // If there's one non-store use and it doesn't feed a two-addr, then
1291 // this is a load-use-store case that we can try to fold.
1292 if (NonSpillCount == 1 && !FeedsTwoAddr) {
1293 // Start by finding the non-store use MachineInstr.
1294 SmallPtrSet<MachineInstr*, 4>::iterator UI = VNUseCount[CurrVN].begin();
1295 int StoreFrameIndex;
1296 unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1297 while (UI != VNUseCount[CurrVN].end() &&
1298 (StoreVReg == (*LI)->reg && StoreFrameIndex == FrameIndex)) {
1300 if (UI != VNUseCount[CurrVN].end())
1301 StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1303 if (UI == VNUseCount[CurrVN].end()) continue;
1305 MachineInstr* use = *UI;
1307 // Attempt to fold it away!
1308 int OpIdx = use->findRegisterUseOperandIdx((*LI)->reg, false);
1309 if (OpIdx == -1) continue;
1310 SmallVector<unsigned, 1> Ops;
1311 Ops.push_back(OpIdx);
1312 if (!TII->canFoldMemoryOperand(use, Ops)) continue;
1314 MachineInstr* NewMI =
1315 TII->foldMemoryOperand(*use->getParent()->getParent(),
1316 use, Ops, FrameIndex);
1318 if (!NewMI) continue;
1320 // Update relevant analyses.
1321 LIs->RemoveMachineInstrFromMaps(DefMI);
1322 LIs->ReplaceMachineInstrInMaps(use, NewMI);
1323 (*LI)->removeValNo(CurrVN);
1325 DefMI->eraseFromParent();
1326 MachineBasicBlock* MBB = use->getParent();
1327 NewMI = MBB->insert(MBB->erase(use), NewMI);
1328 VNUseCount[CurrVN].erase(use);
1330 // Remove deleted instructions. Note that we need to remove them from
1331 // the VNInfo->use map as well, just to be safe.
1332 for (SmallPtrSet<MachineInstr*, 4>::iterator II =
1333 VNUseCount[CurrVN].begin(), IE = VNUseCount[CurrVN].end();
1335 for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
1336 VNI = VNUseCount.begin(), VNE = VNUseCount.end(); VNI != VNE;
1338 if (VNI->first != CurrVN)
1339 VNI->second.erase(*II);
1340 LIs->RemoveMachineInstrFromMaps(*II);
1341 (*II)->eraseFromParent();
1344 VNUseCount.erase(CurrVN);
1346 for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
1347 VI = VNUseCount.begin(), VE = VNUseCount.end(); VI != VE; ++VI)
1348 if (VI->second.erase(use))
1349 VI->second.insert(NewMI);
1356 // If there's more than one non-store instruction, we can't profitably
1357 // fold it, so bail.
1358 if (NonSpillCount) continue;
1360 // Otherwise, this is a load-store case, so DCE them.
1361 for (SmallPtrSet<MachineInstr*, 4>::iterator UI =
1362 VNUseCount[CurrVN].begin(), UE = VNUseCount[CurrVN].end();
1364 LIs->RemoveMachineInstrFromMaps(*UI);
1365 (*UI)->eraseFromParent();
1368 VNUseCount.erase(CurrVN);
1370 LIs->RemoveMachineInstrFromMaps(DefMI);
1371 (*LI)->removeValNo(CurrVN);
1372 DefMI->eraseFromParent();
1381 bool PreAllocSplitting::createsNewJoin(LiveRange* LR,
1382 MachineBasicBlock* DefMBB,
1383 MachineBasicBlock* BarrierMBB) {
1384 if (DefMBB == BarrierMBB)
1387 if (LR->valno->hasPHIKill)
1390 unsigned MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
1391 if (LR->end < MBBEnd)
1394 MachineLoopInfo& MLI = getAnalysis<MachineLoopInfo>();
1395 if (MLI.getLoopFor(DefMBB) != MLI.getLoopFor(BarrierMBB))
1398 MachineDominatorTree& MDT = getAnalysis<MachineDominatorTree>();
1399 SmallPtrSet<MachineBasicBlock*, 4> Visited;
1400 typedef std::pair<MachineBasicBlock*,
1401 MachineBasicBlock::succ_iterator> ItPair;
1402 SmallVector<ItPair, 4> Stack;
1403 Stack.push_back(std::make_pair(BarrierMBB, BarrierMBB->succ_begin()));
1405 while (!Stack.empty()) {
1406 ItPair P = Stack.back();
1409 MachineBasicBlock* PredMBB = P.first;
1410 MachineBasicBlock::succ_iterator S = P.second;
1412 if (S == PredMBB->succ_end())
1414 else if (Visited.count(*S)) {
1415 Stack.push_back(std::make_pair(PredMBB, ++S));
1418 Stack.push_back(std::make_pair(PredMBB, S+1));
1420 MachineBasicBlock* MBB = *S;
1421 Visited.insert(MBB);
1423 if (MBB == BarrierMBB)
1426 MachineDomTreeNode* DefMDTN = MDT.getNode(DefMBB);
1427 MachineDomTreeNode* BarrierMDTN = MDT.getNode(BarrierMBB);
1428 MachineDomTreeNode* MDTN = MDT.getNode(MBB)->getIDom();
1430 if (MDTN == DefMDTN)
1432 else if (MDTN == BarrierMDTN)
1434 MDTN = MDTN->getIDom();
1437 MBBEnd = LIs->getMBBEndIdx(MBB);
1438 if (LR->end > MBBEnd)
1439 Stack.push_back(std::make_pair(MBB, MBB->succ_begin()));
1446 bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
1448 TM = &MF.getTarget();
1449 TRI = TM->getRegisterInfo();
1450 TII = TM->getInstrInfo();
1451 MFI = MF.getFrameInfo();
1452 MRI = &MF.getRegInfo();
1453 LIs = &getAnalysis<LiveIntervals>();
1454 LSs = &getAnalysis<LiveStacks>();
1455 VRM = &getAnalysis<VirtRegMap>();
1457 bool MadeChange = false;
1459 // Make sure blocks are numbered in order.
1460 MF.RenumberBlocks();
1462 MachineBasicBlock *Entry = MF.begin();
1463 SmallPtrSet<MachineBasicBlock*,16> Visited;
1465 SmallPtrSet<LiveInterval*, 8> Split;
1467 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
1468 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
1471 for (MachineBasicBlock::iterator I = BarrierMBB->begin(),
1472 E = BarrierMBB->end(); I != E; ++I) {
1474 const TargetRegisterClass **BarrierRCs =
1475 Barrier->getDesc().getRegClassBarriers();
1478 BarrierIdx = LIs->getInstructionIndex(Barrier);
1479 MadeChange |= SplitRegLiveIntervals(BarrierRCs, Split);
1483 MadeChange |= removeDeadSpills(Split);