1 //===-- PreAllocSplitting.cpp - Pre-allocation Interval Spltting Pass. ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine instruction level pre-register allocation
11 // live interval splitting pass. It finds live interval barriers, i.e.
12 // instructions which will kill all physical registers in certain register
13 // classes, and split all live intervals which cross the barrier.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "pre-alloc-split"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/LiveStackAnalysis.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/DenseMap.h"
34 #include "llvm/ADT/DepthFirstIterator.h"
35 #include "llvm/ADT/SmallPtrSet.h"
36 #include "llvm/ADT/Statistic.h"
39 static cl::opt<int> PreSplitLimit("pre-split-limit", cl::init(-1), cl::Hidden);
40 static cl::opt<int> DeadSplitLimit("dead-split-limit", cl::init(-1), cl::Hidden);
42 STATISTIC(NumSplits, "Number of intervals split");
43 STATISTIC(NumRemats, "Number of intervals split by rematerialization");
44 STATISTIC(NumFolds, "Number of intervals split with spill folding");
45 STATISTIC(NumRenumbers, "Number of intervals renumbered into new registers");
46 STATISTIC(NumDeadSpills, "Number of dead spills removed");
49 class VISIBILITY_HIDDEN PreAllocSplitting : public MachineFunctionPass {
50 MachineFunction *CurrMF;
51 const TargetMachine *TM;
52 const TargetInstrInfo *TII;
53 const TargetRegisterInfo* TRI;
54 MachineFrameInfo *MFI;
55 MachineRegisterInfo *MRI;
59 // Barrier - Current barrier being processed.
60 MachineInstr *Barrier;
62 // BarrierMBB - Basic block where the barrier resides in.
63 MachineBasicBlock *BarrierMBB;
65 // Barrier - Current barrier index.
68 // CurrLI - Current live interval being split.
71 // CurrSLI - Current stack slot live interval.
72 LiveInterval *CurrSLI;
74 // CurrSValNo - Current val# for the stack slot live interval.
77 // IntervalSSMap - A map from live interval to spill slots.
78 DenseMap<unsigned, int> IntervalSSMap;
80 // Def2SpillMap - A map from a def instruction index to spill index.
81 DenseMap<unsigned, unsigned> Def2SpillMap;
85 PreAllocSplitting() : MachineFunctionPass(&ID) {}
87 virtual bool runOnMachineFunction(MachineFunction &MF);
89 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
90 AU.addRequired<LiveIntervals>();
91 AU.addPreserved<LiveIntervals>();
92 AU.addRequired<LiveStacks>();
93 AU.addPreserved<LiveStacks>();
94 AU.addPreserved<RegisterCoalescer>();
96 AU.addPreservedID(StrongPHIEliminationID);
98 AU.addPreservedID(PHIEliminationID);
99 AU.addRequired<MachineDominatorTree>();
100 AU.addRequired<MachineLoopInfo>();
101 AU.addPreserved<MachineDominatorTree>();
102 AU.addPreserved<MachineLoopInfo>();
103 MachineFunctionPass::getAnalysisUsage(AU);
106 virtual void releaseMemory() {
107 IntervalSSMap.clear();
108 Def2SpillMap.clear();
111 virtual const char *getPassName() const {
112 return "Pre-Register Allocaton Live Interval Splitting";
115 /// print - Implement the dump method.
116 virtual void print(std::ostream &O, const Module* M = 0) const {
120 void print(std::ostream *O, const Module* M = 0) const {
125 MachineBasicBlock::iterator
126 findNextEmptySlot(MachineBasicBlock*, MachineInstr*,
129 MachineBasicBlock::iterator
130 findSpillPoint(MachineBasicBlock*, MachineInstr*, MachineInstr*,
131 SmallPtrSet<MachineInstr*, 4>&, unsigned&);
133 MachineBasicBlock::iterator
134 findRestorePoint(MachineBasicBlock*, MachineInstr*, unsigned,
135 SmallPtrSet<MachineInstr*, 4>&, unsigned&);
137 int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
139 bool IsAvailableInStack(MachineBasicBlock*, unsigned, unsigned, unsigned,
140 unsigned&, int&) const;
142 void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned);
144 bool SplitRegLiveInterval(LiveInterval*);
146 bool SplitRegLiveIntervals(const TargetRegisterClass **,
147 SmallPtrSet<LiveInterval*, 8>&);
149 bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB,
150 MachineBasicBlock* BarrierMBB);
151 bool Rematerialize(unsigned vreg, VNInfo* ValNo,
153 MachineBasicBlock::iterator RestorePt,
155 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
156 MachineInstr* FoldSpill(unsigned vreg, const TargetRegisterClass* RC,
158 MachineInstr* Barrier,
159 MachineBasicBlock* MBB,
161 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
162 void RenumberValno(VNInfo* VN);
163 void ReconstructLiveInterval(LiveInterval* LI);
164 bool removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split);
165 unsigned getNumberOfNonSpills(SmallPtrSet<MachineInstr*, 4>& MIs,
166 unsigned Reg, int FrameIndex, bool& TwoAddr);
167 VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator use,
168 MachineBasicBlock* MBB,
170 SmallPtrSet<MachineInstr*, 4>& Visited,
171 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
172 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
173 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
174 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
175 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
176 bool toplevel, bool intrablock);
178 } // end anonymous namespace
180 char PreAllocSplitting::ID = 0;
182 static RegisterPass<PreAllocSplitting>
183 X("pre-alloc-splitting", "Pre-Register Allocation Live Interval Splitting");
185 const PassInfo *const llvm::PreAllocSplittingID = &X;
188 /// findNextEmptySlot - Find a gap after the given machine instruction in the
189 /// instruction index map. If there isn't one, return end().
190 MachineBasicBlock::iterator
191 PreAllocSplitting::findNextEmptySlot(MachineBasicBlock *MBB, MachineInstr *MI,
192 unsigned &SpotIndex) {
193 MachineBasicBlock::iterator MII = MI;
194 if (++MII != MBB->end()) {
195 unsigned Index = LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
204 /// findSpillPoint - Find a gap as far away from the given MI that's suitable
205 /// for spilling the current live interval. The index must be before any
206 /// defs and uses of the live interval register in the mbb. Return begin() if
208 MachineBasicBlock::iterator
209 PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
211 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
212 unsigned &SpillIndex) {
213 MachineBasicBlock::iterator Pt = MBB->begin();
215 // Go top down if RefsInMBB is empty.
216 if (RefsInMBB.empty() && !DefMI) {
217 MachineBasicBlock::iterator MII = MBB->begin();
218 MachineBasicBlock::iterator EndPt = MI;
221 unsigned Index = LIs->getInstructionIndex(MII);
222 unsigned Gap = LIs->findGapBeforeInstr(Index);
228 // We can't insert the spill between the barrier (a call), and its
229 // corresponding call frame setup.
230 } else if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode() &&
231 MII == MachineBasicBlock::iterator(MI))
233 } while (MII != EndPt);
235 MachineBasicBlock::iterator MII = MI;
236 MachineBasicBlock::iterator EndPt = DefMI
237 ? MachineBasicBlock::iterator(DefMI) : MBB->begin();
239 // We can't insert the spill between the barrier (a call), and its
240 // corresponding call frame setup.
241 if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) --MII;
242 while (MII != EndPt && !RefsInMBB.count(MII)) {
243 unsigned Index = LIs->getInstructionIndex(MII);
244 if (LIs->hasGapBeforeInstr(Index)) {
246 SpillIndex = LIs->findGapBeforeInstr(Index, true);
255 /// findRestorePoint - Find a gap in the instruction index map that's suitable
256 /// for restoring the current live interval value. The index must be before any
257 /// uses of the live interval register in the mbb. Return end() if none is
259 MachineBasicBlock::iterator
260 PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
262 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
263 unsigned &RestoreIndex) {
264 // FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
265 // begin index accordingly.
266 MachineBasicBlock::iterator Pt = MBB->end();
267 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
269 // Go bottom up if RefsInMBB is empty and the end of the mbb isn't beyond
270 // the last index in the live range.
271 if (RefsInMBB.empty() && LastIdx >= EndIdx) {
272 MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
273 MachineBasicBlock::iterator EndPt = MI;
276 unsigned Index = LIs->getInstructionIndex(MII);
277 unsigned Gap = LIs->findGapBeforeInstr(Index);
283 // We can't insert a restore between the barrier (a call) and its
284 // corresponding call frame teardown.
285 } else if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode() &&
286 prior(MII) == MachineBasicBlock::iterator(MI))
289 } while (MII != EndPt);
291 MachineBasicBlock::iterator MII = MI;
293 // We can't insert a restore between the barrier (a call) and its
294 // corresponding call frame teardown.
295 if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode())
298 // FIXME: Limit the number of instructions to examine to reduce
300 while (MII != MBB->getFirstTerminator()) {
301 unsigned Index = LIs->getInstructionIndex(MII);
304 unsigned Gap = LIs->findGapBeforeInstr(Index);
309 if (RefsInMBB.count(MII))
318 /// CreateSpillStackSlot - Create a stack slot for the live interval being
319 /// split. If the live interval was previously split, just reuse the same
321 int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
322 const TargetRegisterClass *RC) {
324 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
325 if (I != IntervalSSMap.end()) {
328 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
329 IntervalSSMap[Reg] = SS;
332 // Create live interval for stack slot.
333 CurrSLI = &LSs->getOrCreateInterval(SS);
334 if (CurrSLI->hasAtLeastOneValue())
335 CurrSValNo = CurrSLI->getValNumInfo(0);
337 CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
341 /// IsAvailableInStack - Return true if register is available in a split stack
342 /// slot at the specified index.
344 PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
345 unsigned Reg, unsigned DefIndex,
346 unsigned RestoreIndex, unsigned &SpillIndex,
351 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
352 if (I == IntervalSSMap.end())
354 DenseMap<unsigned, unsigned>::iterator II = Def2SpillMap.find(DefIndex);
355 if (II == Def2SpillMap.end())
358 // If last spill of def is in the same mbb as barrier mbb (where restore will
359 // be), make sure it's not below the intended restore index.
360 // FIXME: Undo the previous spill?
361 assert(LIs->getMBBFromIndex(II->second) == DefMBB);
362 if (DefMBB == BarrierMBB && II->second >= RestoreIndex)
366 SpillIndex = II->second;
370 /// UpdateSpillSlotInterval - Given the specified val# of the register live
371 /// interval being split, and the spill and restore indicies, update the live
372 /// interval of the spill stack slot.
374 PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
375 unsigned RestoreIndex) {
376 assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
377 "Expect restore in the barrier mbb");
379 MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
380 if (MBB == BarrierMBB) {
381 // Intra-block spill + restore. We are done.
382 LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo);
383 CurrSLI->addRange(SLR);
387 SmallPtrSet<MachineBasicBlock*, 4> Processed;
388 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
389 LiveRange SLR(SpillIndex, EndIdx+1, CurrSValNo);
390 CurrSLI->addRange(SLR);
391 Processed.insert(MBB);
393 // Start from the spill mbb, figure out the extend of the spill slot's
395 SmallVector<MachineBasicBlock*, 4> WorkList;
396 const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
397 if (LR->end > EndIdx)
398 // If live range extend beyond end of mbb, add successors to work list.
399 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
400 SE = MBB->succ_end(); SI != SE; ++SI)
401 WorkList.push_back(*SI);
403 while (!WorkList.empty()) {
404 MachineBasicBlock *MBB = WorkList.back();
406 if (Processed.count(MBB))
408 unsigned Idx = LIs->getMBBStartIdx(MBB);
409 LR = CurrLI->getLiveRangeContaining(Idx);
410 if (LR && LR->valno == ValNo) {
411 EndIdx = LIs->getMBBEndIdx(MBB);
412 if (Idx <= RestoreIndex && RestoreIndex < EndIdx) {
413 // Spill slot live interval stops at the restore.
414 LiveRange SLR(Idx, RestoreIndex, CurrSValNo);
415 CurrSLI->addRange(SLR);
416 } else if (LR->end > EndIdx) {
417 // Live range extends beyond end of mbb, process successors.
418 LiveRange SLR(Idx, EndIdx+1, CurrSValNo);
419 CurrSLI->addRange(SLR);
420 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
421 SE = MBB->succ_end(); SI != SE; ++SI)
422 WorkList.push_back(*SI);
424 LiveRange SLR(Idx, LR->end, CurrSValNo);
425 CurrSLI->addRange(SLR);
427 Processed.insert(MBB);
432 /// PerformPHIConstruction - From properly set up use and def lists, use a PHI
433 /// construction algorithm to compute the ranges and valnos for an interval.
434 VNInfo* PreAllocSplitting::PerformPHIConstruction(
435 MachineBasicBlock::iterator use,
436 MachineBasicBlock* MBB,
438 SmallPtrSet<MachineInstr*, 4>& Visited,
439 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
440 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
441 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
442 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
443 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
444 bool toplevel, bool intrablock) {
445 // Return memoized result if it's available.
446 if (toplevel && Visited.count(use) && NewVNs.count(use))
448 else if (!toplevel && intrablock && NewVNs.count(use))
450 else if (!intrablock && LiveOut.count(MBB))
453 typedef DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> > RegMap;
455 // Check if our block contains any uses or defs.
456 bool ContainsDefs = Defs.count(MBB);
457 bool ContainsUses = Uses.count(MBB);
461 // Enumerate the cases of use/def contaning blocks.
462 if (!ContainsDefs && !ContainsUses) {
464 // NOTE: Because this is the fallback case from other cases, we do NOT
465 // assume that we are not intrablock here.
466 if (Phis.count(MBB)) return Phis[MBB];
468 unsigned StartIndex = LIs->getMBBStartIdx(MBB);
470 Phis[MBB] = ret = LI->getNextValue(~0U, /*FIXME*/ 0,
471 LIs->getVNInfoAllocator());
472 if (!intrablock) LiveOut[MBB] = ret;
474 // If there are no uses or defs between our starting point and the
475 // beginning of the block, then recursive perform phi construction
476 // on our predecessors.
477 DenseMap<MachineBasicBlock*, VNInfo*> IncomingVNs;
478 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
479 PE = MBB->pred_end(); PI != PE; ++PI) {
480 VNInfo* Incoming = PerformPHIConstruction((*PI)->end(), *PI, LI,
481 Visited, Defs, Uses, NewVNs,
482 LiveOut, Phis, false, false);
484 IncomingVNs[*PI] = Incoming;
487 if (MBB->pred_size() == 1 && !ret->hasPHIKill) {
488 LI->MergeValueNumberInto(ret, IncomingVNs.begin()->second);
490 // Otherwise, merge the incoming VNInfos with a phi join. Create a new
491 // VNInfo to represent the joined value.
492 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator I =
493 IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) {
494 I->second->hasPHIKill = true;
495 unsigned KillIndex = LIs->getMBBEndIdx(I->first);
496 if (!LiveInterval::isKill(I->second, KillIndex))
497 LI->addKill(I->second, KillIndex);
501 unsigned EndIndex = 0;
503 EndIndex = LIs->getInstructionIndex(use);
504 EndIndex = LiveIntervals::getUseIndex(EndIndex);
506 EndIndex = LIs->getMBBEndIdx(MBB);
507 LI->addRange(LiveRange(StartIndex, EndIndex+1, ret));
509 LI->addKill(ret, EndIndex);
510 } else if (ContainsDefs && !ContainsUses) {
511 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
513 // Search for the def in this block. If we don't find it before the
514 // instruction we care about, go to the fallback case. Note that that
515 // should never happen: this cannot be intrablock, so use should
516 // always be an end() iterator.
517 assert(use == MBB->end() && "No use marked in intrablock");
519 MachineBasicBlock::iterator walker = use;
521 while (walker != MBB->begin())
522 if (BlockDefs.count(walker)) {
527 // Once we've found it, extend its VNInfo to our instruction.
528 unsigned DefIndex = LIs->getInstructionIndex(walker);
529 DefIndex = LiveIntervals::getDefIndex(DefIndex);
530 unsigned EndIndex = LIs->getMBBEndIdx(MBB);
532 ret = NewVNs[walker];
533 LI->addRange(LiveRange(DefIndex, EndIndex+1, ret));
534 } else if (!ContainsDefs && ContainsUses) {
535 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
537 // Search for the use in this block that precedes the instruction we care
538 // about, going to the fallback case if we don't find it.
540 if (use == MBB->begin())
543 MachineBasicBlock::iterator walker = use;
546 while (walker != MBB->begin())
547 if (BlockUses.count(walker)) {
553 // Must check begin() too.
555 if (BlockUses.count(walker))
561 unsigned UseIndex = LIs->getInstructionIndex(walker);
562 UseIndex = LiveIntervals::getUseIndex(UseIndex);
563 unsigned EndIndex = 0;
565 EndIndex = LIs->getInstructionIndex(use);
566 EndIndex = LiveIntervals::getUseIndex(EndIndex);
568 EndIndex = LIs->getMBBEndIdx(MBB);
570 // Now, recursively phi construct the VNInfo for the use we found,
571 // and then extend it to include the instruction we care about
572 ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses,
573 NewVNs, LiveOut, Phis, false, true);
575 LI->addRange(LiveRange(UseIndex, EndIndex+1, ret));
577 // FIXME: Need to set kills properly for inter-block stuff.
578 if (LI->isKill(ret, UseIndex)) LI->removeKill(ret, UseIndex);
580 LI->addKill(ret, EndIndex);
581 } else if (ContainsDefs && ContainsUses){
582 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
583 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
585 // This case is basically a merging of the two preceding case, with the
586 // special note that checking for defs must take precedence over checking
587 // for uses, because of two-address instructions.
589 if (use == MBB->begin())
592 MachineBasicBlock::iterator walker = use;
594 bool foundDef = false;
595 bool foundUse = false;
596 while (walker != MBB->begin())
597 if (BlockDefs.count(walker)) {
600 } else if (BlockUses.count(walker)) {
606 // Must check begin() too.
607 if (!foundDef && !foundUse) {
608 if (BlockDefs.count(walker))
610 else if (BlockUses.count(walker))
616 unsigned StartIndex = LIs->getInstructionIndex(walker);
617 StartIndex = foundDef ? LiveIntervals::getDefIndex(StartIndex) :
618 LiveIntervals::getUseIndex(StartIndex);
619 unsigned EndIndex = 0;
621 EndIndex = LIs->getInstructionIndex(use);
622 EndIndex = LiveIntervals::getUseIndex(EndIndex);
624 EndIndex = LIs->getMBBEndIdx(MBB);
627 ret = NewVNs[walker];
629 ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses,
630 NewVNs, LiveOut, Phis, false, true);
632 LI->addRange(LiveRange(StartIndex, EndIndex+1, ret));
634 if (foundUse && LI->isKill(ret, StartIndex))
635 LI->removeKill(ret, StartIndex);
637 LI->addKill(ret, EndIndex);
641 // Memoize results so we don't have to recompute them.
642 if (!intrablock) LiveOut[MBB] = ret;
644 if (!NewVNs.count(use))
652 /// ReconstructLiveInterval - Recompute a live interval from scratch.
653 void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) {
654 BumpPtrAllocator& Alloc = LIs->getVNInfoAllocator();
656 // Clear the old ranges and valnos;
659 // Cache the uses and defs of the register
660 typedef DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> > RegMap;
663 // Keep track of the new VNs we're creating.
664 DenseMap<MachineInstr*, VNInfo*> NewVNs;
665 SmallPtrSet<VNInfo*, 2> PhiVNs;
667 // Cache defs, and create a new VNInfo for each def.
668 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
669 DE = MRI->def_end(); DI != DE; ++DI) {
670 Defs[(*DI).getParent()].insert(&*DI);
672 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
673 DefIdx = LiveIntervals::getDefIndex(DefIdx);
675 VNInfo* NewVN = LI->getNextValue(DefIdx, 0, Alloc);
677 // If the def is a move, set the copy field.
678 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
679 if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
680 if (DstReg == LI->reg)
683 NewVNs[&*DI] = NewVN;
686 // Cache uses as a separate pass from actually processing them.
687 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
688 UE = MRI->use_end(); UI != UE; ++UI)
689 Uses[(*UI).getParent()].insert(&*UI);
691 // Now, actually process every use and use a phi construction algorithm
692 // to walk from it to its reaching definitions, building VNInfos along
694 DenseMap<MachineBasicBlock*, VNInfo*> LiveOut;
695 DenseMap<MachineBasicBlock*, VNInfo*> Phis;
696 SmallPtrSet<MachineInstr*, 4> Visited;
697 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
698 UE = MRI->use_end(); UI != UE; ++UI) {
699 PerformPHIConstruction(&*UI, UI->getParent(), LI, Visited, Defs,
700 Uses, NewVNs, LiveOut, Phis, true, true);
703 // Add ranges for dead defs
704 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
705 DE = MRI->def_end(); DI != DE; ++DI) {
706 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
707 DefIdx = LiveIntervals::getDefIndex(DefIdx);
709 if (LI->liveAt(DefIdx)) continue;
711 VNInfo* DeadVN = NewVNs[&*DI];
712 LI->addRange(LiveRange(DefIdx, DefIdx+1, DeadVN));
713 LI->addKill(DeadVN, DefIdx);
717 /// RenumberValno - Split the given valno out into a new vreg, allowing it to
718 /// be allocated to a different register. This function creates a new vreg,
719 /// copies the valno and its live ranges over to the new vreg's interval,
720 /// removes them from the old interval, and rewrites all uses and defs of
721 /// the original reg to the new vreg within those ranges.
722 void PreAllocSplitting::RenumberValno(VNInfo* VN) {
723 SmallVector<VNInfo*, 4> Stack;
724 SmallVector<VNInfo*, 4> VNsToCopy;
727 // Walk through and copy the valno we care about, and any other valnos
728 // that are two-address redefinitions of the one we care about. These
729 // will need to be rewritten as well. We also check for safety of the
730 // renumbering here, by making sure that none of the valno involved has
732 while (!Stack.empty()) {
733 VNInfo* OldVN = Stack.back();
736 // Bail out if we ever encounter a valno that has a PHI kill. We can't
738 if (OldVN->hasPHIKill) return;
740 VNsToCopy.push_back(OldVN);
742 // Locate two-address redefinitions
743 for (SmallVector<unsigned, 4>::iterator KI = OldVN->kills.begin(),
744 KE = OldVN->kills.end(); KI != KE; ++KI) {
745 MachineInstr* MI = LIs->getInstructionFromIndex(*KI);
746 unsigned DefIdx = MI->findRegisterDefOperandIdx(CurrLI->reg);
747 if (DefIdx == ~0U) continue;
748 if (MI->isRegReDefinedByTwoAddr(DefIdx)) {
750 CurrLI->findDefinedVNInfo(LiveIntervals::getDefIndex(*KI));
751 if (NextVN == OldVN) continue;
752 Stack.push_back(NextVN);
757 // Create the new vreg
758 unsigned NewVReg = MRI->createVirtualRegister(MRI->getRegClass(CurrLI->reg));
760 // Create the new live interval
761 LiveInterval& NewLI = LIs->getOrCreateInterval(NewVReg);
763 for (SmallVector<VNInfo*, 4>::iterator OI = VNsToCopy.begin(), OE =
764 VNsToCopy.end(); OI != OE; ++OI) {
767 // Copy the valno over
768 VNInfo* NewVN = NewLI.getNextValue(OldVN->def, OldVN->copy,
769 LIs->getVNInfoAllocator());
770 NewLI.copyValNumInfo(NewVN, OldVN);
771 NewLI.MergeValueInAsValue(*CurrLI, OldVN, NewVN);
773 // Remove the valno from the old interval
774 CurrLI->removeValNo(OldVN);
777 // Rewrite defs and uses. This is done in two stages to avoid invalidating
779 SmallVector<std::pair<MachineInstr*, unsigned>, 8> OpsToChange;
781 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
782 E = MRI->reg_end(); I != E; ++I) {
783 MachineOperand& MO = I.getOperand();
784 unsigned InstrIdx = LIs->getInstructionIndex(&*I);
786 if ((MO.isUse() && NewLI.liveAt(LiveIntervals::getUseIndex(InstrIdx))) ||
787 (MO.isDef() && NewLI.liveAt(LiveIntervals::getDefIndex(InstrIdx))))
788 OpsToChange.push_back(std::make_pair(&*I, I.getOperandNo()));
791 for (SmallVector<std::pair<MachineInstr*, unsigned>, 8>::iterator I =
792 OpsToChange.begin(), E = OpsToChange.end(); I != E; ++I) {
793 MachineInstr* Inst = I->first;
794 unsigned OpIdx = I->second;
795 MachineOperand& MO = Inst->getOperand(OpIdx);
799 // The renumbered vreg shares a stack slot with the old register.
800 if (IntervalSSMap.count(CurrLI->reg))
801 IntervalSSMap[NewVReg] = IntervalSSMap[CurrLI->reg];
806 bool PreAllocSplitting::Rematerialize(unsigned vreg, VNInfo* ValNo,
808 MachineBasicBlock::iterator RestorePt,
810 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
811 MachineBasicBlock& MBB = *RestorePt->getParent();
813 MachineBasicBlock::iterator KillPt = BarrierMBB->end();
814 unsigned KillIdx = 0;
815 if (ValNo->def == ~0U || DefMI->getParent() == BarrierMBB)
816 KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, KillIdx);
818 KillPt = findNextEmptySlot(DefMI->getParent(), DefMI, KillIdx);
820 if (KillPt == DefMI->getParent()->end())
823 TII->reMaterialize(MBB, RestorePt, vreg, DefMI);
824 LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx);
826 ReconstructLiveInterval(CurrLI);
827 unsigned RematIdx = LIs->getInstructionIndex(prior(RestorePt));
828 RematIdx = LiveIntervals::getDefIndex(RematIdx);
829 RenumberValno(CurrLI->findDefinedVNInfo(RematIdx));
836 MachineInstr* PreAllocSplitting::FoldSpill(unsigned vreg,
837 const TargetRegisterClass* RC,
839 MachineInstr* Barrier,
840 MachineBasicBlock* MBB,
842 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
843 MachineBasicBlock::iterator Pt = MBB->begin();
845 // Go top down if RefsInMBB is empty.
846 if (RefsInMBB.empty())
849 MachineBasicBlock::iterator FoldPt = Barrier;
850 while (&*FoldPt != DefMI && FoldPt != MBB->begin() &&
851 !RefsInMBB.count(FoldPt))
854 int OpIdx = FoldPt->findRegisterDefOperandIdx(vreg, false);
858 SmallVector<unsigned, 1> Ops;
859 Ops.push_back(OpIdx);
861 if (!TII->canFoldMemoryOperand(FoldPt, Ops))
864 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(vreg);
865 if (I != IntervalSSMap.end()) {
868 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
872 MachineInstr* FMI = TII->foldMemoryOperand(*MBB->getParent(),
876 LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
877 FMI = MBB->insert(MBB->erase(FoldPt), FMI);
880 IntervalSSMap[vreg] = SS;
881 CurrSLI = &LSs->getOrCreateInterval(SS);
882 if (CurrSLI->hasAtLeastOneValue())
883 CurrSValNo = CurrSLI->getValNumInfo(0);
885 CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
891 /// SplitRegLiveInterval - Split (spill and restore) the given live interval
892 /// so it would not cross the barrier that's being processed. Shrink wrap
893 /// (minimize) the live interval to the last uses.
894 bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
897 // Find live range where current interval cross the barrier.
898 LiveInterval::iterator LR =
899 CurrLI->FindLiveRangeContaining(LIs->getUseIndex(BarrierIdx));
900 VNInfo *ValNo = LR->valno;
902 if (ValNo->def == ~1U) {
903 // Defined by a dead def? How can this be?
904 assert(0 && "Val# is defined by a dead def?");
908 MachineInstr *DefMI = (ValNo->def != ~0U)
909 ? LIs->getInstructionFromIndex(ValNo->def) : NULL;
911 // If this would create a new join point, do not split.
912 if (DefMI && createsNewJoin(LR, DefMI->getParent(), Barrier->getParent()))
915 // Find all references in the barrier mbb.
916 SmallPtrSet<MachineInstr*, 4> RefsInMBB;
917 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
918 E = MRI->reg_end(); I != E; ++I) {
919 MachineInstr *RefMI = &*I;
920 if (RefMI->getParent() == BarrierMBB)
921 RefsInMBB.insert(RefMI);
924 // Find a point to restore the value after the barrier.
925 unsigned RestoreIndex = 0;
926 MachineBasicBlock::iterator RestorePt =
927 findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB, RestoreIndex);
928 if (RestorePt == BarrierMBB->end())
931 if (DefMI && LIs->isReMaterializable(*LI, ValNo, DefMI))
932 if (Rematerialize(LI->reg, ValNo, DefMI, RestorePt,
933 RestoreIndex, RefsInMBB))
936 // Add a spill either before the barrier or after the definition.
937 MachineBasicBlock *DefMBB = DefMI ? DefMI->getParent() : NULL;
938 const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg);
939 unsigned SpillIndex = 0;
940 MachineInstr *SpillMI = NULL;
942 if (ValNo->def == ~0U) {
943 // If it's defined by a phi, we must split just before the barrier.
944 if ((SpillMI = FoldSpill(LI->reg, RC, 0, Barrier,
945 BarrierMBB, SS, RefsInMBB))) {
946 SpillIndex = LIs->getInstructionIndex(SpillMI);
948 MachineBasicBlock::iterator SpillPt =
949 findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, SpillIndex);
950 if (SpillPt == BarrierMBB->begin())
951 return false; // No gap to insert spill.
954 SS = CreateSpillStackSlot(CurrLI->reg, RC);
955 TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
956 SpillMI = prior(SpillPt);
957 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
959 } else if (!IsAvailableInStack(DefMBB, CurrLI->reg, ValNo->def,
960 RestoreIndex, SpillIndex, SS)) {
961 // If it's already split, just restore the value. There is no need to spill
964 return false; // Def is dead. Do nothing.
966 if ((SpillMI = FoldSpill(LI->reg, RC, DefMI, Barrier,
967 BarrierMBB, SS, RefsInMBB))) {
968 SpillIndex = LIs->getInstructionIndex(SpillMI);
970 // Check if it's possible to insert a spill after the def MI.
971 MachineBasicBlock::iterator SpillPt;
972 if (DefMBB == BarrierMBB) {
973 // Add spill after the def and the last use before the barrier.
974 SpillPt = findSpillPoint(BarrierMBB, Barrier, DefMI,
975 RefsInMBB, SpillIndex);
976 if (SpillPt == DefMBB->begin())
977 return false; // No gap to insert spill.
979 SpillPt = findNextEmptySlot(DefMBB, DefMI, SpillIndex);
980 if (SpillPt == DefMBB->end())
981 return false; // No gap to insert spill.
983 // Add spill. The store instruction kills the register if def is before
984 // the barrier in the barrier block.
985 SS = CreateSpillStackSlot(CurrLI->reg, RC);
986 TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg,
987 DefMBB == BarrierMBB, SS, RC);
988 SpillMI = prior(SpillPt);
989 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
993 // Remember def instruction index to spill index mapping.
994 if (DefMI && SpillMI)
995 Def2SpillMap[ValNo->def] = SpillIndex;
998 TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
999 MachineInstr *LoadMI = prior(RestorePt);
1000 LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex);
1002 // Update spill stack slot live interval.
1003 UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
1004 LIs->getDefIndex(RestoreIndex));
1006 ReconstructLiveInterval(CurrLI);
1007 unsigned RestoreIdx = LIs->getInstructionIndex(prior(RestorePt));
1008 RestoreIdx = LiveIntervals::getDefIndex(RestoreIdx);
1009 RenumberValno(CurrLI->findDefinedVNInfo(RestoreIdx));
1015 /// SplitRegLiveIntervals - Split all register live intervals that cross the
1016 /// barrier that's being processed.
1018 PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs,
1019 SmallPtrSet<LiveInterval*, 8>& Split) {
1020 // First find all the virtual registers whose live intervals are intercepted
1021 // by the current barrier.
1022 SmallVector<LiveInterval*, 8> Intervals;
1023 for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
1024 if (TII->IgnoreRegisterClassBarriers(*RC))
1026 std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
1027 for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
1028 unsigned Reg = VRs[i];
1029 if (!LIs->hasInterval(Reg))
1031 LiveInterval *LI = &LIs->getInterval(Reg);
1032 if (LI->liveAt(BarrierIdx) && !Barrier->readsRegister(Reg))
1033 // Virtual register live interval is intercepted by the barrier. We
1034 // should split and shrink wrap its interval if possible.
1035 Intervals.push_back(LI);
1039 // Process the affected live intervals.
1040 bool Change = false;
1041 while (!Intervals.empty()) {
1042 if (PreSplitLimit != -1 && (int)NumSplits == PreSplitLimit)
1044 else if (NumSplits == 4)
1046 LiveInterval *LI = Intervals.back();
1047 Intervals.pop_back();
1048 bool result = SplitRegLiveInterval(LI);
1049 if (result) Split.insert(LI);
1056 unsigned PreAllocSplitting::getNumberOfNonSpills(
1057 SmallPtrSet<MachineInstr*, 4>& MIs,
1058 unsigned Reg, int FrameIndex,
1059 bool& FeedsTwoAddr) {
1060 unsigned NonSpills = 0;
1061 for (SmallPtrSet<MachineInstr*, 4>::iterator UI = MIs.begin(), UE = MIs.end();
1063 int StoreFrameIndex;
1064 unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1065 if (StoreVReg != Reg || StoreFrameIndex != FrameIndex)
1068 int DefIdx = (*UI)->findRegisterDefOperandIdx(Reg);
1069 if (DefIdx != -1 && (*UI)->isRegReDefinedByTwoAddr(DefIdx))
1070 FeedsTwoAddr = true;
1076 /// removeDeadSpills - After doing splitting, filter through all intervals we've
1077 /// split, and see if any of the spills are unnecessary. If so, remove them.
1078 bool PreAllocSplitting::removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split) {
1079 bool changed = false;
1081 // Walk over all of the live intervals that were touched by the splitter,
1082 // and see if we can do any DCE and/or folding.
1083 for (SmallPtrSet<LiveInterval*, 8>::iterator LI = split.begin(),
1084 LE = split.end(); LI != LE; ++LI) {
1085 DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> > VNUseCount;
1087 // First, collect all the uses of the vreg, and sort them by their
1088 // reaching definition (VNInfo).
1089 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin((*LI)->reg),
1090 UE = MRI->use_end(); UI != UE; ++UI) {
1091 unsigned index = LIs->getInstructionIndex(&*UI);
1092 index = LiveIntervals::getUseIndex(index);
1094 const LiveRange* LR = (*LI)->getLiveRangeContaining(index);
1095 VNUseCount[LR->valno].insert(&*UI);
1098 // Now, take the definitions (VNInfo's) one at a time and try to DCE
1099 // and/or fold them away.
1100 for (LiveInterval::vni_iterator VI = (*LI)->vni_begin(),
1101 VE = (*LI)->vni_end(); VI != VE; ++VI) {
1103 if (DeadSplitLimit != -1 && (int)NumDeadSpills == DeadSplitLimit)
1106 VNInfo* CurrVN = *VI;
1108 // We don't currently try to handle definitions with PHI kills, because
1109 // it would involve processing more than one VNInfo at once.
1110 if (CurrVN->hasPHIKill) continue;
1112 // We also don't try to handle the results of PHI joins, since there's
1113 // no defining instruction to analyze.
1114 unsigned DefIdx = CurrVN->def;
1115 if (DefIdx == ~0U || DefIdx == ~1U) continue;
1117 // We're only interested in eliminating cruft introduced by the splitter,
1118 // is of the form load-use or load-use-store. First, check that the
1119 // definition is a load, and remember what stack slot we loaded it from.
1120 MachineInstr* DefMI = LIs->getInstructionFromIndex(DefIdx);
1122 if (!TII->isLoadFromStackSlot(DefMI, FrameIndex)) continue;
1124 // If the definition has no uses at all, just DCE it.
1125 if (VNUseCount[CurrVN].size() == 0) {
1126 LIs->RemoveMachineInstrFromMaps(DefMI);
1127 (*LI)->removeValNo(CurrVN);
1128 DefMI->eraseFromParent();
1129 VNUseCount.erase(CurrVN);
1135 // Second, get the number of non-store uses of the definition, as well as
1136 // a flag indicating whether it feeds into a later two-address definition.
1137 bool FeedsTwoAddr = false;
1138 unsigned NonSpillCount = getNumberOfNonSpills(VNUseCount[CurrVN],
1139 (*LI)->reg, FrameIndex,
1142 // If there's one non-store use and it doesn't feed a two-addr, then
1143 // this is a load-use-store case that we can try to fold.
1144 if (NonSpillCount == 1 && !FeedsTwoAddr) {
1145 // Start by finding the non-store use MachineInstr.
1146 SmallPtrSet<MachineInstr*, 4>::iterator UI = VNUseCount[CurrVN].begin();
1147 int StoreFrameIndex;
1148 unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1149 while (UI != VNUseCount[CurrVN].end() &&
1150 (StoreVReg == (*LI)->reg && StoreFrameIndex == FrameIndex)) {
1152 if (UI != VNUseCount[CurrVN].end())
1153 StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1155 if (UI == VNUseCount[CurrVN].end()) continue;
1157 MachineInstr* use = *UI;
1159 // Attempt to fold it away!
1160 int OpIdx = use->findRegisterUseOperandIdx((*LI)->reg, false);
1161 if (OpIdx == -1) continue;
1162 SmallVector<unsigned, 1> Ops;
1163 Ops.push_back(OpIdx);
1164 if (!TII->canFoldMemoryOperand(use, Ops)) continue;
1166 MachineInstr* NewMI =
1167 TII->foldMemoryOperand(*use->getParent()->getParent(),
1168 use, Ops, FrameIndex);
1170 if (!NewMI) continue;
1172 // Update relevant analyses.
1173 LIs->RemoveMachineInstrFromMaps(DefMI);
1174 LIs->ReplaceMachineInstrInMaps(use, NewMI);
1175 (*LI)->removeValNo(CurrVN);
1177 DefMI->eraseFromParent();
1178 MachineBasicBlock* MBB = use->getParent();
1179 NewMI = MBB->insert(MBB->erase(use), NewMI);
1180 VNUseCount[CurrVN].erase(use);
1182 // Remove deleted instructions. Note that we need to remove them from
1183 // the VNInfo->use map as well, just to be safe.
1184 for (SmallPtrSet<MachineInstr*, 4>::iterator II =
1185 VNUseCount[CurrVN].begin(), IE = VNUseCount[CurrVN].end();
1187 for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
1188 VNI = VNUseCount.begin(), VNE = VNUseCount.end(); VNI != VNE;
1190 if (VNI->first != CurrVN)
1191 VNI->second.erase(*II);
1192 LIs->RemoveMachineInstrFromMaps(*II);
1193 (*II)->eraseFromParent();
1196 VNUseCount.erase(CurrVN);
1198 for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
1199 VI = VNUseCount.begin(), VE = VNUseCount.end(); VI != VE; ++VI)
1200 if (VI->second.erase(use))
1201 VI->second.insert(NewMI);
1208 // If there's more than one non-store instruction, we can't profitably
1209 // fold it, so bail.
1210 if (NonSpillCount) continue;
1212 // Otherwise, this is a load-store case, so DCE them.
1213 for (SmallPtrSet<MachineInstr*, 4>::iterator UI =
1214 VNUseCount[CurrVN].begin(), UE = VNUseCount[CurrVN].end();
1216 LIs->RemoveMachineInstrFromMaps(*UI);
1217 (*UI)->eraseFromParent();
1220 VNUseCount.erase(CurrVN);
1222 LIs->RemoveMachineInstrFromMaps(DefMI);
1223 (*LI)->removeValNo(CurrVN);
1224 DefMI->eraseFromParent();
1233 bool PreAllocSplitting::createsNewJoin(LiveRange* LR,
1234 MachineBasicBlock* DefMBB,
1235 MachineBasicBlock* BarrierMBB) {
1236 if (DefMBB == BarrierMBB)
1239 if (LR->valno->hasPHIKill)
1242 unsigned MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
1243 if (LR->end < MBBEnd)
1246 MachineLoopInfo& MLI = getAnalysis<MachineLoopInfo>();
1247 if (MLI.getLoopFor(DefMBB) != MLI.getLoopFor(BarrierMBB))
1250 MachineDominatorTree& MDT = getAnalysis<MachineDominatorTree>();
1251 SmallPtrSet<MachineBasicBlock*, 4> Visited;
1252 typedef std::pair<MachineBasicBlock*,
1253 MachineBasicBlock::succ_iterator> ItPair;
1254 SmallVector<ItPair, 4> Stack;
1255 Stack.push_back(std::make_pair(BarrierMBB, BarrierMBB->succ_begin()));
1257 while (!Stack.empty()) {
1258 ItPair P = Stack.back();
1261 MachineBasicBlock* PredMBB = P.first;
1262 MachineBasicBlock::succ_iterator S = P.second;
1264 if (S == PredMBB->succ_end())
1266 else if (Visited.count(*S)) {
1267 Stack.push_back(std::make_pair(PredMBB, ++S));
1270 Stack.push_back(std::make_pair(PredMBB, S+1));
1272 MachineBasicBlock* MBB = *S;
1273 Visited.insert(MBB);
1275 if (MBB == BarrierMBB)
1278 MachineDomTreeNode* DefMDTN = MDT.getNode(DefMBB);
1279 MachineDomTreeNode* BarrierMDTN = MDT.getNode(BarrierMBB);
1280 MachineDomTreeNode* MDTN = MDT.getNode(MBB)->getIDom();
1282 if (MDTN == DefMDTN)
1284 else if (MDTN == BarrierMDTN)
1286 MDTN = MDTN->getIDom();
1289 MBBEnd = LIs->getMBBEndIdx(MBB);
1290 if (LR->end > MBBEnd)
1291 Stack.push_back(std::make_pair(MBB, MBB->succ_begin()));
1298 bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
1300 TM = &MF.getTarget();
1301 TRI = TM->getRegisterInfo();
1302 TII = TM->getInstrInfo();
1303 MFI = MF.getFrameInfo();
1304 MRI = &MF.getRegInfo();
1305 LIs = &getAnalysis<LiveIntervals>();
1306 LSs = &getAnalysis<LiveStacks>();
1308 bool MadeChange = false;
1310 // Make sure blocks are numbered in order.
1311 MF.RenumberBlocks();
1313 MachineBasicBlock *Entry = MF.begin();
1314 SmallPtrSet<MachineBasicBlock*,16> Visited;
1316 SmallPtrSet<LiveInterval*, 8> Split;
1318 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
1319 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
1322 for (MachineBasicBlock::iterator I = BarrierMBB->begin(),
1323 E = BarrierMBB->end(); I != E; ++I) {
1325 const TargetRegisterClass **BarrierRCs =
1326 Barrier->getDesc().getRegClassBarriers();
1329 BarrierIdx = LIs->getInstructionIndex(Barrier);
1330 MadeChange |= SplitRegLiveIntervals(BarrierRCs, Split);
1334 MadeChange |= removeDeadSpills(Split);