1 //===-- PreAllocSplitting.cpp - Pre-allocation Interval Spltting Pass. ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine instruction level pre-register allocation
11 // live interval splitting pass. It finds live interval barriers, i.e.
12 // instructions which will kill all physical registers in certain register
13 // classes, and split all live intervals which cross the barrier.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "pre-alloc-split"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/LiveStackAnalysis.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/DenseMap.h"
34 #include "llvm/ADT/DepthFirstIterator.h"
35 #include "llvm/ADT/SmallPtrSet.h"
36 #include "llvm/ADT/Statistic.h"
39 static cl::opt<int> PreSplitLimit("pre-split-limit", cl::init(-1), cl::Hidden);
40 static cl::opt<int> DeadSplitLimit("dead-split-limit", cl::init(-1), cl::Hidden);
42 STATISTIC(NumSplits, "Number of intervals split");
43 STATISTIC(NumRemats, "Number of intervals split by rematerialization");
44 STATISTIC(NumFolds, "Number of intervals split with spill folding");
45 STATISTIC(NumRenumbers, "Number of intervals renumbered into new registers");
46 STATISTIC(NumDeadSpills, "Number of dead spills removed");
49 class VISIBILITY_HIDDEN PreAllocSplitting : public MachineFunctionPass {
50 MachineFunction *CurrMF;
51 const TargetMachine *TM;
52 const TargetInstrInfo *TII;
53 const TargetRegisterInfo* TRI;
54 MachineFrameInfo *MFI;
55 MachineRegisterInfo *MRI;
59 // Barrier - Current barrier being processed.
60 MachineInstr *Barrier;
62 // BarrierMBB - Basic block where the barrier resides in.
63 MachineBasicBlock *BarrierMBB;
65 // Barrier - Current barrier index.
68 // CurrLI - Current live interval being split.
71 // CurrSLI - Current stack slot live interval.
72 LiveInterval *CurrSLI;
74 // CurrSValNo - Current val# for the stack slot live interval.
77 // IntervalSSMap - A map from live interval to spill slots.
78 DenseMap<unsigned, int> IntervalSSMap;
80 // Def2SpillMap - A map from a def instruction index to spill index.
81 DenseMap<unsigned, unsigned> Def2SpillMap;
85 PreAllocSplitting() : MachineFunctionPass(&ID) {}
87 virtual bool runOnMachineFunction(MachineFunction &MF);
89 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
90 AU.addRequired<LiveIntervals>();
91 AU.addPreserved<LiveIntervals>();
92 AU.addRequired<LiveStacks>();
93 AU.addPreserved<LiveStacks>();
94 AU.addPreserved<RegisterCoalescer>();
96 AU.addPreservedID(StrongPHIEliminationID);
98 AU.addPreservedID(PHIEliminationID);
99 AU.addRequired<MachineDominatorTree>();
100 AU.addRequired<MachineLoopInfo>();
101 AU.addPreserved<MachineDominatorTree>();
102 AU.addPreserved<MachineLoopInfo>();
103 MachineFunctionPass::getAnalysisUsage(AU);
106 virtual void releaseMemory() {
107 IntervalSSMap.clear();
108 Def2SpillMap.clear();
111 virtual const char *getPassName() const {
112 return "Pre-Register Allocaton Live Interval Splitting";
115 /// print - Implement the dump method.
116 virtual void print(std::ostream &O, const Module* M = 0) const {
120 void print(std::ostream *O, const Module* M = 0) const {
125 MachineBasicBlock::iterator
126 findNextEmptySlot(MachineBasicBlock*, MachineInstr*,
129 MachineBasicBlock::iterator
130 findSpillPoint(MachineBasicBlock*, MachineInstr*, MachineInstr*,
131 SmallPtrSet<MachineInstr*, 4>&, unsigned&);
133 MachineBasicBlock::iterator
134 findRestorePoint(MachineBasicBlock*, MachineInstr*, unsigned,
135 SmallPtrSet<MachineInstr*, 4>&, unsigned&);
137 int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
139 bool IsAvailableInStack(MachineBasicBlock*, unsigned, unsigned, unsigned,
140 unsigned&, int&) const;
142 void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned);
144 bool SplitRegLiveInterval(LiveInterval*);
146 bool SplitRegLiveIntervals(const TargetRegisterClass **,
147 SmallPtrSet<LiveInterval*, 8>&);
149 bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB,
150 MachineBasicBlock* BarrierMBB);
151 bool Rematerialize(unsigned vreg, VNInfo* ValNo,
153 MachineBasicBlock::iterator RestorePt,
155 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
156 MachineInstr* FoldSpill(unsigned vreg, const TargetRegisterClass* RC,
158 MachineInstr* Barrier,
159 MachineBasicBlock* MBB,
161 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
162 void RenumberValno(VNInfo* VN);
163 void ReconstructLiveInterval(LiveInterval* LI);
164 bool removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split);
165 unsigned getNumberOfNonSpills(SmallPtrSet<MachineInstr*, 4>& MIs,
166 unsigned Reg, int FrameIndex, bool& TwoAddr);
167 VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator Use,
168 MachineBasicBlock* MBB, LiveInterval* LI,
169 SmallPtrSet<MachineInstr*, 4>& Visited,
170 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
171 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
172 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
173 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
174 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
175 bool IsTopLevel, bool IsIntraBlock);
176 VNInfo* PerformPHIConstructionFallBack(MachineBasicBlock::iterator Use,
177 MachineBasicBlock* MBB, LiveInterval* LI,
178 SmallPtrSet<MachineInstr*, 4>& Visited,
179 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
180 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
181 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
182 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
183 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
184 bool IsTopLevel, bool IsIntraBlock);
186 } // end anonymous namespace
188 char PreAllocSplitting::ID = 0;
190 static RegisterPass<PreAllocSplitting>
191 X("pre-alloc-splitting", "Pre-Register Allocation Live Interval Splitting");
193 const PassInfo *const llvm::PreAllocSplittingID = &X;
196 /// findNextEmptySlot - Find a gap after the given machine instruction in the
197 /// instruction index map. If there isn't one, return end().
198 MachineBasicBlock::iterator
199 PreAllocSplitting::findNextEmptySlot(MachineBasicBlock *MBB, MachineInstr *MI,
200 unsigned &SpotIndex) {
201 MachineBasicBlock::iterator MII = MI;
202 if (++MII != MBB->end()) {
203 unsigned Index = LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
212 /// findSpillPoint - Find a gap as far away from the given MI that's suitable
213 /// for spilling the current live interval. The index must be before any
214 /// defs and uses of the live interval register in the mbb. Return begin() if
216 MachineBasicBlock::iterator
217 PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
219 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
220 unsigned &SpillIndex) {
221 MachineBasicBlock::iterator Pt = MBB->begin();
223 // Go top down if RefsInMBB is empty.
224 if (RefsInMBB.empty() && !DefMI) {
225 MachineBasicBlock::iterator MII = MBB->begin();
226 MachineBasicBlock::iterator EndPt = MI;
229 unsigned Index = LIs->getInstructionIndex(MII);
230 unsigned Gap = LIs->findGapBeforeInstr(Index);
232 // We can't insert the spill between the barrier (a call), and its
233 // corresponding call frame setup/teardown.
234 if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) {
235 bool reachedBarrier = false;
238 reachedBarrier = true;
242 } while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode());
244 if (reachedBarrier) break;
250 } while (MII != EndPt);
252 MachineBasicBlock::iterator MII = MI;
253 MachineBasicBlock::iterator EndPt = DefMI
254 ? MachineBasicBlock::iterator(DefMI) : MBB->begin();
256 while (MII != EndPt && !RefsInMBB.count(MII)) {
257 unsigned Index = LIs->getInstructionIndex(MII);
259 // We can't insert the spill between the barrier (a call), and its
260 // corresponding call frame setup.
261 if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) {
264 } if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) {
265 bool reachedBarrier = false;
266 while (MII->getOpcode() != TRI->getCallFrameSetupOpcode()) {
269 reachedBarrier = true;
274 if (reachedBarrier) break;
276 } else if (LIs->hasGapBeforeInstr(Index)) {
278 SpillIndex = LIs->findGapBeforeInstr(Index, true);
287 /// findRestorePoint - Find a gap in the instruction index map that's suitable
288 /// for restoring the current live interval value. The index must be before any
289 /// uses of the live interval register in the mbb. Return end() if none is
291 MachineBasicBlock::iterator
292 PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
294 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
295 unsigned &RestoreIndex) {
296 // FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
297 // begin index accordingly.
298 MachineBasicBlock::iterator Pt = MBB->end();
299 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
301 // Go bottom up if RefsInMBB is empty and the end of the mbb isn't beyond
302 // the last index in the live range.
303 if (RefsInMBB.empty() && LastIdx >= EndIdx) {
304 MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
305 MachineBasicBlock::iterator EndPt = MI;
308 unsigned Index = LIs->getInstructionIndex(MII);
309 unsigned Gap = LIs->findGapBeforeInstr(Index);
311 // We can't insert a restore between the barrier (a call) and its
312 // corresponding call frame teardown.
313 if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) {
314 bool reachedBarrier = false;
315 while (MII->getOpcode() != TRI->getCallFrameSetupOpcode()) {
318 reachedBarrier = true;
323 if (reachedBarrier) break;
332 } while (MII != EndPt);
334 MachineBasicBlock::iterator MII = MI;
337 // FIXME: Limit the number of instructions to examine to reduce
339 while (MII != MBB->getFirstTerminator()) {
340 unsigned Index = LIs->getInstructionIndex(MII);
343 unsigned Gap = LIs->findGapBeforeInstr(Index);
345 // We can't insert a restore between the barrier (a call) and its
346 // corresponding call frame teardown.
347 if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) {
350 } else if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) {
351 bool reachedBarrier = false;
353 if (MII == MBB->getFirstTerminator() || RefsInMBB.count(MII)) {
354 reachedBarrier = true;
359 } while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode());
361 if (reachedBarrier) break;
367 if (RefsInMBB.count(MII))
376 /// CreateSpillStackSlot - Create a stack slot for the live interval being
377 /// split. If the live interval was previously split, just reuse the same
379 int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
380 const TargetRegisterClass *RC) {
382 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
383 if (I != IntervalSSMap.end()) {
386 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
387 IntervalSSMap[Reg] = SS;
390 // Create live interval for stack slot.
391 CurrSLI = &LSs->getOrCreateInterval(SS);
392 if (CurrSLI->hasAtLeastOneValue())
393 CurrSValNo = CurrSLI->getValNumInfo(0);
395 CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
399 /// IsAvailableInStack - Return true if register is available in a split stack
400 /// slot at the specified index.
402 PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
403 unsigned Reg, unsigned DefIndex,
404 unsigned RestoreIndex, unsigned &SpillIndex,
409 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
410 if (I == IntervalSSMap.end())
412 DenseMap<unsigned, unsigned>::iterator II = Def2SpillMap.find(DefIndex);
413 if (II == Def2SpillMap.end())
416 // If last spill of def is in the same mbb as barrier mbb (where restore will
417 // be), make sure it's not below the intended restore index.
418 // FIXME: Undo the previous spill?
419 assert(LIs->getMBBFromIndex(II->second) == DefMBB);
420 if (DefMBB == BarrierMBB && II->second >= RestoreIndex)
424 SpillIndex = II->second;
428 /// UpdateSpillSlotInterval - Given the specified val# of the register live
429 /// interval being split, and the spill and restore indicies, update the live
430 /// interval of the spill stack slot.
432 PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
433 unsigned RestoreIndex) {
434 assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
435 "Expect restore in the barrier mbb");
437 MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
438 if (MBB == BarrierMBB) {
439 // Intra-block spill + restore. We are done.
440 LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo);
441 CurrSLI->addRange(SLR);
445 SmallPtrSet<MachineBasicBlock*, 4> Processed;
446 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
447 LiveRange SLR(SpillIndex, EndIdx+1, CurrSValNo);
448 CurrSLI->addRange(SLR);
449 Processed.insert(MBB);
451 // Start from the spill mbb, figure out the extend of the spill slot's
453 SmallVector<MachineBasicBlock*, 4> WorkList;
454 const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
455 if (LR->end > EndIdx)
456 // If live range extend beyond end of mbb, add successors to work list.
457 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
458 SE = MBB->succ_end(); SI != SE; ++SI)
459 WorkList.push_back(*SI);
461 while (!WorkList.empty()) {
462 MachineBasicBlock *MBB = WorkList.back();
464 if (Processed.count(MBB))
466 unsigned Idx = LIs->getMBBStartIdx(MBB);
467 LR = CurrLI->getLiveRangeContaining(Idx);
468 if (LR && LR->valno == ValNo) {
469 EndIdx = LIs->getMBBEndIdx(MBB);
470 if (Idx <= RestoreIndex && RestoreIndex < EndIdx) {
471 // Spill slot live interval stops at the restore.
472 LiveRange SLR(Idx, RestoreIndex, CurrSValNo);
473 CurrSLI->addRange(SLR);
474 } else if (LR->end > EndIdx) {
475 // Live range extends beyond end of mbb, process successors.
476 LiveRange SLR(Idx, EndIdx+1, CurrSValNo);
477 CurrSLI->addRange(SLR);
478 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
479 SE = MBB->succ_end(); SI != SE; ++SI)
480 WorkList.push_back(*SI);
482 LiveRange SLR(Idx, LR->end, CurrSValNo);
483 CurrSLI->addRange(SLR);
485 Processed.insert(MBB);
490 /// PerformPHIConstruction - From properly set up use and def lists, use a PHI
491 /// construction algorithm to compute the ranges and valnos for an interval.
493 PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI,
494 MachineBasicBlock* MBB, LiveInterval* LI,
495 SmallPtrSet<MachineInstr*, 4>& Visited,
496 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
497 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
498 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
499 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
500 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
501 bool IsTopLevel, bool IsIntraBlock) {
502 // Return memoized result if it's available.
503 if (IsTopLevel && Visited.count(UseI) && NewVNs.count(UseI))
505 else if (!IsTopLevel && IsIntraBlock && NewVNs.count(UseI))
507 else if (!IsIntraBlock && LiveOut.count(MBB))
510 // Check if our block contains any uses or defs.
511 bool ContainsDefs = Defs.count(MBB);
512 bool ContainsUses = Uses.count(MBB);
516 // Enumerate the cases of use/def contaning blocks.
517 if (!ContainsDefs && !ContainsUses) {
518 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses,
519 NewVNs, LiveOut, Phis,
520 IsTopLevel, IsIntraBlock);
521 } else if (ContainsDefs && !ContainsUses) {
522 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
524 // Search for the def in this block. If we don't find it before the
525 // instruction we care about, go to the fallback case. Note that that
526 // should never happen: this cannot be intrablock, so use should
527 // always be an end() iterator.
528 assert(UseI == MBB->end() && "No use marked in intrablock");
530 MachineBasicBlock::iterator Walker = UseI;
532 while (Walker != MBB->begin()) {
533 if (BlockDefs.count(Walker))
538 // Once we've found it, extend its VNInfo to our instruction.
539 unsigned DefIndex = LIs->getInstructionIndex(Walker);
540 DefIndex = LiveIntervals::getDefIndex(DefIndex);
541 unsigned EndIndex = LIs->getMBBEndIdx(MBB);
543 RetVNI = NewVNs[Walker];
544 LI->addRange(LiveRange(DefIndex, EndIndex+1, RetVNI));
545 } else if (!ContainsDefs && ContainsUses) {
546 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
548 // Search for the use in this block that precedes the instruction we care
549 // about, going to the fallback case if we don't find it.
550 if (UseI == MBB->begin())
551 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
552 Uses, NewVNs, LiveOut, Phis,
553 IsTopLevel, IsIntraBlock);
555 MachineBasicBlock::iterator Walker = UseI;
558 while (Walker != MBB->begin()) {
559 if (BlockUses.count(Walker)) {
566 // Must check begin() too.
568 if (BlockUses.count(Walker))
571 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
572 Uses, NewVNs, LiveOut, Phis,
573 IsTopLevel, IsIntraBlock);
576 unsigned UseIndex = LIs->getInstructionIndex(Walker);
577 UseIndex = LiveIntervals::getUseIndex(UseIndex);
578 unsigned EndIndex = 0;
580 EndIndex = LIs->getInstructionIndex(UseI);
581 EndIndex = LiveIntervals::getUseIndex(EndIndex);
583 EndIndex = LIs->getMBBEndIdx(MBB);
585 // Now, recursively phi construct the VNInfo for the use we found,
586 // and then extend it to include the instruction we care about
587 RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
588 NewVNs, LiveOut, Phis, false, true);
590 LI->addRange(LiveRange(UseIndex, EndIndex+1, RetVNI));
592 // FIXME: Need to set kills properly for inter-block stuff.
593 if (LI->isKill(RetVNI, UseIndex)) LI->removeKill(RetVNI, UseIndex);
595 LI->addKill(RetVNI, EndIndex);
596 } else if (ContainsDefs && ContainsUses) {
597 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
598 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
600 // This case is basically a merging of the two preceding case, with the
601 // special note that checking for defs must take precedence over checking
602 // for uses, because of two-address instructions.
604 if (UseI == MBB->begin())
605 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses,
606 NewVNs, LiveOut, Phis,
607 IsTopLevel, IsIntraBlock);
609 MachineBasicBlock::iterator Walker = UseI;
611 bool foundDef = false;
612 bool foundUse = false;
613 while (Walker != MBB->begin()) {
614 if (BlockDefs.count(Walker)) {
617 } else if (BlockUses.count(Walker)) {
624 // Must check begin() too.
625 if (!foundDef && !foundUse) {
626 if (BlockDefs.count(Walker))
628 else if (BlockUses.count(Walker))
631 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
632 Uses, NewVNs, LiveOut, Phis,
633 IsTopLevel, IsIntraBlock);
636 unsigned StartIndex = LIs->getInstructionIndex(Walker);
637 StartIndex = foundDef ? LiveIntervals::getDefIndex(StartIndex) :
638 LiveIntervals::getUseIndex(StartIndex);
639 unsigned EndIndex = 0;
641 EndIndex = LIs->getInstructionIndex(UseI);
642 EndIndex = LiveIntervals::getUseIndex(EndIndex);
644 EndIndex = LIs->getMBBEndIdx(MBB);
647 RetVNI = NewVNs[Walker];
649 RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
650 NewVNs, LiveOut, Phis, false, true);
652 LI->addRange(LiveRange(StartIndex, EndIndex+1, RetVNI));
654 if (foundUse && LI->isKill(RetVNI, StartIndex))
655 LI->removeKill(RetVNI, StartIndex);
657 LI->addKill(RetVNI, EndIndex);
661 // Memoize results so we don't have to recompute them.
662 if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
664 if (!NewVNs.count(UseI))
665 NewVNs[UseI] = RetVNI;
666 Visited.insert(UseI);
672 /// PerformPHIConstructionFallBack - PerformPHIConstruction fall back path.
675 PreAllocSplitting::PerformPHIConstructionFallBack(MachineBasicBlock::iterator UseI,
676 MachineBasicBlock* MBB, LiveInterval* LI,
677 SmallPtrSet<MachineInstr*, 4>& Visited,
678 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
679 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
680 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
681 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
682 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
683 bool IsTopLevel, bool IsIntraBlock) {
684 // NOTE: Because this is the fallback case from other cases, we do NOT
685 // assume that we are not intrablock here.
686 if (Phis.count(MBB)) return Phis[MBB];
688 unsigned StartIndex = LIs->getMBBStartIdx(MBB);
689 VNInfo *RetVNI = Phis[MBB] = LI->getNextValue(~0U, /*FIXME*/ 0,
690 LIs->getVNInfoAllocator());
691 if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
693 // If there are no uses or defs between our starting point and the
694 // beginning of the block, then recursive perform phi construction
695 // on our predecessors.
696 DenseMap<MachineBasicBlock*, VNInfo*> IncomingVNs;
697 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
698 PE = MBB->pred_end(); PI != PE; ++PI) {
699 VNInfo* Incoming = PerformPHIConstruction((*PI)->end(), *PI, LI,
700 Visited, Defs, Uses, NewVNs,
701 LiveOut, Phis, false, false);
703 IncomingVNs[*PI] = Incoming;
706 if (MBB->pred_size() == 1 && !RetVNI->hasPHIKill) {
707 VNInfo* OldVN = RetVNI;
708 VNInfo* NewVN = IncomingVNs.begin()->second;
709 VNInfo* MergedVN = LI->MergeValueNumberInto(OldVN, NewVN);
710 if (MergedVN == OldVN) std::swap(OldVN, NewVN);
712 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator LOI = LiveOut.begin(),
713 LOE = LiveOut.end(); LOI != LOE; ++LOI)
714 if (LOI->second == OldVN)
715 LOI->second = MergedVN;
716 for (DenseMap<MachineInstr*, VNInfo*>::iterator NVI = NewVNs.begin(),
717 NVE = NewVNs.end(); NVI != NVE; ++NVI)
718 if (NVI->second == OldVN)
719 NVI->second = MergedVN;
720 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator PI = Phis.begin(),
721 PE = Phis.end(); PI != PE; ++PI)
722 if (PI->second == OldVN)
723 PI->second = MergedVN;
726 // Otherwise, merge the incoming VNInfos with a phi join. Create a new
727 // VNInfo to represent the joined value.
728 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator I =
729 IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) {
730 I->second->hasPHIKill = true;
731 unsigned KillIndex = LIs->getMBBEndIdx(I->first);
732 if (!LiveInterval::isKill(I->second, KillIndex))
733 LI->addKill(I->second, KillIndex);
737 unsigned EndIndex = 0;
739 EndIndex = LIs->getInstructionIndex(UseI);
740 EndIndex = LiveIntervals::getUseIndex(EndIndex);
742 EndIndex = LIs->getMBBEndIdx(MBB);
743 LI->addRange(LiveRange(StartIndex, EndIndex+1, RetVNI));
745 LI->addKill(RetVNI, EndIndex);
747 // Memoize results so we don't have to recompute them.
749 LiveOut[MBB] = RetVNI;
751 if (!NewVNs.count(UseI))
752 NewVNs[UseI] = RetVNI;
753 Visited.insert(UseI);
759 /// ReconstructLiveInterval - Recompute a live interval from scratch.
760 void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) {
761 BumpPtrAllocator& Alloc = LIs->getVNInfoAllocator();
763 // Clear the old ranges and valnos;
766 // Cache the uses and defs of the register
767 typedef DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> > RegMap;
770 // Keep track of the new VNs we're creating.
771 DenseMap<MachineInstr*, VNInfo*> NewVNs;
772 SmallPtrSet<VNInfo*, 2> PhiVNs;
774 // Cache defs, and create a new VNInfo for each def.
775 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
776 DE = MRI->def_end(); DI != DE; ++DI) {
777 Defs[(*DI).getParent()].insert(&*DI);
779 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
780 DefIdx = LiveIntervals::getDefIndex(DefIdx);
782 VNInfo* NewVN = LI->getNextValue(DefIdx, 0, Alloc);
784 // If the def is a move, set the copy field.
785 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
786 if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
787 if (DstReg == LI->reg)
790 NewVNs[&*DI] = NewVN;
793 // Cache uses as a separate pass from actually processing them.
794 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
795 UE = MRI->use_end(); UI != UE; ++UI)
796 Uses[(*UI).getParent()].insert(&*UI);
798 // Now, actually process every use and use a phi construction algorithm
799 // to walk from it to its reaching definitions, building VNInfos along
801 DenseMap<MachineBasicBlock*, VNInfo*> LiveOut;
802 DenseMap<MachineBasicBlock*, VNInfo*> Phis;
803 SmallPtrSet<MachineInstr*, 4> Visited;
804 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
805 UE = MRI->use_end(); UI != UE; ++UI) {
806 PerformPHIConstruction(&*UI, UI->getParent(), LI, Visited, Defs,
807 Uses, NewVNs, LiveOut, Phis, true, true);
810 // Add ranges for dead defs
811 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
812 DE = MRI->def_end(); DI != DE; ++DI) {
813 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
814 DefIdx = LiveIntervals::getDefIndex(DefIdx);
816 if (LI->liveAt(DefIdx)) continue;
818 VNInfo* DeadVN = NewVNs[&*DI];
819 LI->addRange(LiveRange(DefIdx, DefIdx+1, DeadVN));
820 LI->addKill(DeadVN, DefIdx);
824 /// RenumberValno - Split the given valno out into a new vreg, allowing it to
825 /// be allocated to a different register. This function creates a new vreg,
826 /// copies the valno and its live ranges over to the new vreg's interval,
827 /// removes them from the old interval, and rewrites all uses and defs of
828 /// the original reg to the new vreg within those ranges.
829 void PreAllocSplitting::RenumberValno(VNInfo* VN) {
830 SmallVector<VNInfo*, 4> Stack;
831 SmallVector<VNInfo*, 4> VNsToCopy;
834 // Walk through and copy the valno we care about, and any other valnos
835 // that are two-address redefinitions of the one we care about. These
836 // will need to be rewritten as well. We also check for safety of the
837 // renumbering here, by making sure that none of the valno involved has
839 while (!Stack.empty()) {
840 VNInfo* OldVN = Stack.back();
843 // Bail out if we ever encounter a valno that has a PHI kill. We can't
845 if (OldVN->hasPHIKill) return;
847 VNsToCopy.push_back(OldVN);
849 // Locate two-address redefinitions
850 for (SmallVector<unsigned, 4>::iterator KI = OldVN->kills.begin(),
851 KE = OldVN->kills.end(); KI != KE; ++KI) {
852 MachineInstr* MI = LIs->getInstructionFromIndex(*KI);
853 unsigned DefIdx = MI->findRegisterDefOperandIdx(CurrLI->reg);
854 if (DefIdx == ~0U) continue;
855 if (MI->isRegReDefinedByTwoAddr(DefIdx)) {
857 CurrLI->findDefinedVNInfo(LiveIntervals::getDefIndex(*KI));
858 if (NextVN == OldVN) continue;
859 Stack.push_back(NextVN);
864 // Create the new vreg
865 unsigned NewVReg = MRI->createVirtualRegister(MRI->getRegClass(CurrLI->reg));
867 // Create the new live interval
868 LiveInterval& NewLI = LIs->getOrCreateInterval(NewVReg);
870 for (SmallVector<VNInfo*, 4>::iterator OI = VNsToCopy.begin(), OE =
871 VNsToCopy.end(); OI != OE; ++OI) {
874 // Copy the valno over
875 VNInfo* NewVN = NewLI.getNextValue(OldVN->def, OldVN->copy,
876 LIs->getVNInfoAllocator());
877 NewLI.copyValNumInfo(NewVN, OldVN);
878 NewLI.MergeValueInAsValue(*CurrLI, OldVN, NewVN);
880 // Remove the valno from the old interval
881 CurrLI->removeValNo(OldVN);
884 // Rewrite defs and uses. This is done in two stages to avoid invalidating
886 SmallVector<std::pair<MachineInstr*, unsigned>, 8> OpsToChange;
888 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
889 E = MRI->reg_end(); I != E; ++I) {
890 MachineOperand& MO = I.getOperand();
891 unsigned InstrIdx = LIs->getInstructionIndex(&*I);
893 if ((MO.isUse() && NewLI.liveAt(LiveIntervals::getUseIndex(InstrIdx))) ||
894 (MO.isDef() && NewLI.liveAt(LiveIntervals::getDefIndex(InstrIdx))))
895 OpsToChange.push_back(std::make_pair(&*I, I.getOperandNo()));
898 for (SmallVector<std::pair<MachineInstr*, unsigned>, 8>::iterator I =
899 OpsToChange.begin(), E = OpsToChange.end(); I != E; ++I) {
900 MachineInstr* Inst = I->first;
901 unsigned OpIdx = I->second;
902 MachineOperand& MO = Inst->getOperand(OpIdx);
906 // The renumbered vreg shares a stack slot with the old register.
907 if (IntervalSSMap.count(CurrLI->reg))
908 IntervalSSMap[NewVReg] = IntervalSSMap[CurrLI->reg];
913 bool PreAllocSplitting::Rematerialize(unsigned vreg, VNInfo* ValNo,
915 MachineBasicBlock::iterator RestorePt,
917 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
918 MachineBasicBlock& MBB = *RestorePt->getParent();
920 MachineBasicBlock::iterator KillPt = BarrierMBB->end();
921 unsigned KillIdx = 0;
922 if (ValNo->def == ~0U || DefMI->getParent() == BarrierMBB)
923 KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, KillIdx);
925 KillPt = findNextEmptySlot(DefMI->getParent(), DefMI, KillIdx);
927 if (KillPt == DefMI->getParent()->end())
930 TII->reMaterialize(MBB, RestorePt, vreg, DefMI);
931 LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx);
933 ReconstructLiveInterval(CurrLI);
934 unsigned RematIdx = LIs->getInstructionIndex(prior(RestorePt));
935 RematIdx = LiveIntervals::getDefIndex(RematIdx);
936 RenumberValno(CurrLI->findDefinedVNInfo(RematIdx));
943 MachineInstr* PreAllocSplitting::FoldSpill(unsigned vreg,
944 const TargetRegisterClass* RC,
946 MachineInstr* Barrier,
947 MachineBasicBlock* MBB,
949 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
950 MachineBasicBlock::iterator Pt = MBB->begin();
952 // Go top down if RefsInMBB is empty.
953 if (RefsInMBB.empty())
956 MachineBasicBlock::iterator FoldPt = Barrier;
957 while (&*FoldPt != DefMI && FoldPt != MBB->begin() &&
958 !RefsInMBB.count(FoldPt))
961 int OpIdx = FoldPt->findRegisterDefOperandIdx(vreg, false);
965 SmallVector<unsigned, 1> Ops;
966 Ops.push_back(OpIdx);
968 if (!TII->canFoldMemoryOperand(FoldPt, Ops))
971 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(vreg);
972 if (I != IntervalSSMap.end()) {
975 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
979 MachineInstr* FMI = TII->foldMemoryOperand(*MBB->getParent(),
983 LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
984 FMI = MBB->insert(MBB->erase(FoldPt), FMI);
987 IntervalSSMap[vreg] = SS;
988 CurrSLI = &LSs->getOrCreateInterval(SS);
989 if (CurrSLI->hasAtLeastOneValue())
990 CurrSValNo = CurrSLI->getValNumInfo(0);
992 CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
998 /// SplitRegLiveInterval - Split (spill and restore) the given live interval
999 /// so it would not cross the barrier that's being processed. Shrink wrap
1000 /// (minimize) the live interval to the last uses.
1001 bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
1004 // Find live range where current interval cross the barrier.
1005 LiveInterval::iterator LR =
1006 CurrLI->FindLiveRangeContaining(LIs->getUseIndex(BarrierIdx));
1007 VNInfo *ValNo = LR->valno;
1009 if (ValNo->def == ~1U) {
1010 // Defined by a dead def? How can this be?
1011 assert(0 && "Val# is defined by a dead def?");
1015 MachineInstr *DefMI = (ValNo->def != ~0U)
1016 ? LIs->getInstructionFromIndex(ValNo->def) : NULL;
1018 // If this would create a new join point, do not split.
1019 if (DefMI && createsNewJoin(LR, DefMI->getParent(), Barrier->getParent()))
1022 // Find all references in the barrier mbb.
1023 SmallPtrSet<MachineInstr*, 4> RefsInMBB;
1024 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
1025 E = MRI->reg_end(); I != E; ++I) {
1026 MachineInstr *RefMI = &*I;
1027 if (RefMI->getParent() == BarrierMBB)
1028 RefsInMBB.insert(RefMI);
1031 // Find a point to restore the value after the barrier.
1032 unsigned RestoreIndex = 0;
1033 MachineBasicBlock::iterator RestorePt =
1034 findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB, RestoreIndex);
1035 if (RestorePt == BarrierMBB->end())
1038 if (DefMI && LIs->isReMaterializable(*LI, ValNo, DefMI))
1039 if (Rematerialize(LI->reg, ValNo, DefMI, RestorePt,
1040 RestoreIndex, RefsInMBB))
1043 // Add a spill either before the barrier or after the definition.
1044 MachineBasicBlock *DefMBB = DefMI ? DefMI->getParent() : NULL;
1045 const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg);
1046 unsigned SpillIndex = 0;
1047 MachineInstr *SpillMI = NULL;
1049 if (ValNo->def == ~0U) {
1050 // If it's defined by a phi, we must split just before the barrier.
1051 if ((SpillMI = FoldSpill(LI->reg, RC, 0, Barrier,
1052 BarrierMBB, SS, RefsInMBB))) {
1053 SpillIndex = LIs->getInstructionIndex(SpillMI);
1055 MachineBasicBlock::iterator SpillPt =
1056 findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, SpillIndex);
1057 if (SpillPt == BarrierMBB->begin())
1058 return false; // No gap to insert spill.
1061 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1062 TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
1063 SpillMI = prior(SpillPt);
1064 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1066 } else if (!IsAvailableInStack(DefMBB, CurrLI->reg, ValNo->def,
1067 RestoreIndex, SpillIndex, SS)) {
1068 // If it's already split, just restore the value. There is no need to spill
1071 return false; // Def is dead. Do nothing.
1073 if ((SpillMI = FoldSpill(LI->reg, RC, DefMI, Barrier,
1074 BarrierMBB, SS, RefsInMBB))) {
1075 SpillIndex = LIs->getInstructionIndex(SpillMI);
1077 // Check if it's possible to insert a spill after the def MI.
1078 MachineBasicBlock::iterator SpillPt;
1079 if (DefMBB == BarrierMBB) {
1080 // Add spill after the def and the last use before the barrier.
1081 SpillPt = findSpillPoint(BarrierMBB, Barrier, DefMI,
1082 RefsInMBB, SpillIndex);
1083 if (SpillPt == DefMBB->begin())
1084 return false; // No gap to insert spill.
1086 SpillPt = findNextEmptySlot(DefMBB, DefMI, SpillIndex);
1087 if (SpillPt == DefMBB->end())
1088 return false; // No gap to insert spill.
1090 // Add spill. The store instruction kills the register if def is before
1091 // the barrier in the barrier block.
1092 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1093 TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg,
1094 DefMBB == BarrierMBB, SS, RC);
1095 SpillMI = prior(SpillPt);
1096 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1100 // Remember def instruction index to spill index mapping.
1101 if (DefMI && SpillMI)
1102 Def2SpillMap[ValNo->def] = SpillIndex;
1105 TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
1106 MachineInstr *LoadMI = prior(RestorePt);
1107 LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex);
1109 // Update spill stack slot live interval.
1110 UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
1111 LIs->getDefIndex(RestoreIndex));
1113 ReconstructLiveInterval(CurrLI);
1114 unsigned RestoreIdx = LIs->getInstructionIndex(prior(RestorePt));
1115 RestoreIdx = LiveIntervals::getDefIndex(RestoreIdx);
1116 RenumberValno(CurrLI->findDefinedVNInfo(RestoreIdx));
1122 /// SplitRegLiveIntervals - Split all register live intervals that cross the
1123 /// barrier that's being processed.
1125 PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs,
1126 SmallPtrSet<LiveInterval*, 8>& Split) {
1127 // First find all the virtual registers whose live intervals are intercepted
1128 // by the current barrier.
1129 SmallVector<LiveInterval*, 8> Intervals;
1130 for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
1131 // FIXME: If it's not safe to move any instruction that defines the barrier
1132 // register class, then it means there are some special dependencies which
1133 // codegen is not modelling. Ignore these barriers for now.
1134 if (!TII->isSafeToMoveRegClassDefs(*RC))
1136 std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
1137 for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
1138 unsigned Reg = VRs[i];
1139 if (!LIs->hasInterval(Reg))
1141 LiveInterval *LI = &LIs->getInterval(Reg);
1142 if (LI->liveAt(BarrierIdx) && !Barrier->readsRegister(Reg))
1143 // Virtual register live interval is intercepted by the barrier. We
1144 // should split and shrink wrap its interval if possible.
1145 Intervals.push_back(LI);
1149 // Process the affected live intervals.
1150 bool Change = false;
1151 while (!Intervals.empty()) {
1152 if (PreSplitLimit != -1 && (int)NumSplits == PreSplitLimit)
1154 else if (NumSplits == 4)
1156 LiveInterval *LI = Intervals.back();
1157 Intervals.pop_back();
1158 bool result = SplitRegLiveInterval(LI);
1159 if (result) Split.insert(LI);
1166 unsigned PreAllocSplitting::getNumberOfNonSpills(
1167 SmallPtrSet<MachineInstr*, 4>& MIs,
1168 unsigned Reg, int FrameIndex,
1169 bool& FeedsTwoAddr) {
1170 unsigned NonSpills = 0;
1171 for (SmallPtrSet<MachineInstr*, 4>::iterator UI = MIs.begin(), UE = MIs.end();
1173 int StoreFrameIndex;
1174 unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1175 if (StoreVReg != Reg || StoreFrameIndex != FrameIndex)
1178 int DefIdx = (*UI)->findRegisterDefOperandIdx(Reg);
1179 if (DefIdx != -1 && (*UI)->isRegReDefinedByTwoAddr(DefIdx))
1180 FeedsTwoAddr = true;
1186 /// removeDeadSpills - After doing splitting, filter through all intervals we've
1187 /// split, and see if any of the spills are unnecessary. If so, remove them.
1188 bool PreAllocSplitting::removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split) {
1189 bool changed = false;
1191 // Walk over all of the live intervals that were touched by the splitter,
1192 // and see if we can do any DCE and/or folding.
1193 for (SmallPtrSet<LiveInterval*, 8>::iterator LI = split.begin(),
1194 LE = split.end(); LI != LE; ++LI) {
1195 DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> > VNUseCount;
1197 // First, collect all the uses of the vreg, and sort them by their
1198 // reaching definition (VNInfo).
1199 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin((*LI)->reg),
1200 UE = MRI->use_end(); UI != UE; ++UI) {
1201 unsigned index = LIs->getInstructionIndex(&*UI);
1202 index = LiveIntervals::getUseIndex(index);
1204 const LiveRange* LR = (*LI)->getLiveRangeContaining(index);
1205 VNUseCount[LR->valno].insert(&*UI);
1208 // Now, take the definitions (VNInfo's) one at a time and try to DCE
1209 // and/or fold them away.
1210 for (LiveInterval::vni_iterator VI = (*LI)->vni_begin(),
1211 VE = (*LI)->vni_end(); VI != VE; ++VI) {
1213 if (DeadSplitLimit != -1 && (int)NumDeadSpills == DeadSplitLimit)
1216 VNInfo* CurrVN = *VI;
1218 // We don't currently try to handle definitions with PHI kills, because
1219 // it would involve processing more than one VNInfo at once.
1220 if (CurrVN->hasPHIKill) continue;
1222 // We also don't try to handle the results of PHI joins, since there's
1223 // no defining instruction to analyze.
1224 unsigned DefIdx = CurrVN->def;
1225 if (DefIdx == ~0U || DefIdx == ~1U) continue;
1227 // We're only interested in eliminating cruft introduced by the splitter,
1228 // is of the form load-use or load-use-store. First, check that the
1229 // definition is a load, and remember what stack slot we loaded it from.
1230 MachineInstr* DefMI = LIs->getInstructionFromIndex(DefIdx);
1232 if (!TII->isLoadFromStackSlot(DefMI, FrameIndex)) continue;
1234 // If the definition has no uses at all, just DCE it.
1235 if (VNUseCount[CurrVN].size() == 0) {
1236 LIs->RemoveMachineInstrFromMaps(DefMI);
1237 (*LI)->removeValNo(CurrVN);
1238 DefMI->eraseFromParent();
1239 VNUseCount.erase(CurrVN);
1245 // Second, get the number of non-store uses of the definition, as well as
1246 // a flag indicating whether it feeds into a later two-address definition.
1247 bool FeedsTwoAddr = false;
1248 unsigned NonSpillCount = getNumberOfNonSpills(VNUseCount[CurrVN],
1249 (*LI)->reg, FrameIndex,
1252 // If there's one non-store use and it doesn't feed a two-addr, then
1253 // this is a load-use-store case that we can try to fold.
1254 if (NonSpillCount == 1 && !FeedsTwoAddr) {
1255 // Start by finding the non-store use MachineInstr.
1256 SmallPtrSet<MachineInstr*, 4>::iterator UI = VNUseCount[CurrVN].begin();
1257 int StoreFrameIndex;
1258 unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1259 while (UI != VNUseCount[CurrVN].end() &&
1260 (StoreVReg == (*LI)->reg && StoreFrameIndex == FrameIndex)) {
1262 if (UI != VNUseCount[CurrVN].end())
1263 StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1265 if (UI == VNUseCount[CurrVN].end()) continue;
1267 MachineInstr* use = *UI;
1269 // Attempt to fold it away!
1270 int OpIdx = use->findRegisterUseOperandIdx((*LI)->reg, false);
1271 if (OpIdx == -1) continue;
1272 SmallVector<unsigned, 1> Ops;
1273 Ops.push_back(OpIdx);
1274 if (!TII->canFoldMemoryOperand(use, Ops)) continue;
1276 MachineInstr* NewMI =
1277 TII->foldMemoryOperand(*use->getParent()->getParent(),
1278 use, Ops, FrameIndex);
1280 if (!NewMI) continue;
1282 // Update relevant analyses.
1283 LIs->RemoveMachineInstrFromMaps(DefMI);
1284 LIs->ReplaceMachineInstrInMaps(use, NewMI);
1285 (*LI)->removeValNo(CurrVN);
1287 DefMI->eraseFromParent();
1288 MachineBasicBlock* MBB = use->getParent();
1289 NewMI = MBB->insert(MBB->erase(use), NewMI);
1290 VNUseCount[CurrVN].erase(use);
1292 // Remove deleted instructions. Note that we need to remove them from
1293 // the VNInfo->use map as well, just to be safe.
1294 for (SmallPtrSet<MachineInstr*, 4>::iterator II =
1295 VNUseCount[CurrVN].begin(), IE = VNUseCount[CurrVN].end();
1297 for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
1298 VNI = VNUseCount.begin(), VNE = VNUseCount.end(); VNI != VNE;
1300 if (VNI->first != CurrVN)
1301 VNI->second.erase(*II);
1302 LIs->RemoveMachineInstrFromMaps(*II);
1303 (*II)->eraseFromParent();
1306 VNUseCount.erase(CurrVN);
1308 for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
1309 VI = VNUseCount.begin(), VE = VNUseCount.end(); VI != VE; ++VI)
1310 if (VI->second.erase(use))
1311 VI->second.insert(NewMI);
1318 // If there's more than one non-store instruction, we can't profitably
1319 // fold it, so bail.
1320 if (NonSpillCount) continue;
1322 // Otherwise, this is a load-store case, so DCE them.
1323 for (SmallPtrSet<MachineInstr*, 4>::iterator UI =
1324 VNUseCount[CurrVN].begin(), UE = VNUseCount[CurrVN].end();
1326 LIs->RemoveMachineInstrFromMaps(*UI);
1327 (*UI)->eraseFromParent();
1330 VNUseCount.erase(CurrVN);
1332 LIs->RemoveMachineInstrFromMaps(DefMI);
1333 (*LI)->removeValNo(CurrVN);
1334 DefMI->eraseFromParent();
1343 bool PreAllocSplitting::createsNewJoin(LiveRange* LR,
1344 MachineBasicBlock* DefMBB,
1345 MachineBasicBlock* BarrierMBB) {
1346 if (DefMBB == BarrierMBB)
1349 if (LR->valno->hasPHIKill)
1352 unsigned MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
1353 if (LR->end < MBBEnd)
1356 MachineLoopInfo& MLI = getAnalysis<MachineLoopInfo>();
1357 if (MLI.getLoopFor(DefMBB) != MLI.getLoopFor(BarrierMBB))
1360 MachineDominatorTree& MDT = getAnalysis<MachineDominatorTree>();
1361 SmallPtrSet<MachineBasicBlock*, 4> Visited;
1362 typedef std::pair<MachineBasicBlock*,
1363 MachineBasicBlock::succ_iterator> ItPair;
1364 SmallVector<ItPair, 4> Stack;
1365 Stack.push_back(std::make_pair(BarrierMBB, BarrierMBB->succ_begin()));
1367 while (!Stack.empty()) {
1368 ItPair P = Stack.back();
1371 MachineBasicBlock* PredMBB = P.first;
1372 MachineBasicBlock::succ_iterator S = P.second;
1374 if (S == PredMBB->succ_end())
1376 else if (Visited.count(*S)) {
1377 Stack.push_back(std::make_pair(PredMBB, ++S));
1380 Stack.push_back(std::make_pair(PredMBB, S+1));
1382 MachineBasicBlock* MBB = *S;
1383 Visited.insert(MBB);
1385 if (MBB == BarrierMBB)
1388 MachineDomTreeNode* DefMDTN = MDT.getNode(DefMBB);
1389 MachineDomTreeNode* BarrierMDTN = MDT.getNode(BarrierMBB);
1390 MachineDomTreeNode* MDTN = MDT.getNode(MBB)->getIDom();
1392 if (MDTN == DefMDTN)
1394 else if (MDTN == BarrierMDTN)
1396 MDTN = MDTN->getIDom();
1399 MBBEnd = LIs->getMBBEndIdx(MBB);
1400 if (LR->end > MBBEnd)
1401 Stack.push_back(std::make_pair(MBB, MBB->succ_begin()));
1408 bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
1410 TM = &MF.getTarget();
1411 TRI = TM->getRegisterInfo();
1412 TII = TM->getInstrInfo();
1413 MFI = MF.getFrameInfo();
1414 MRI = &MF.getRegInfo();
1415 LIs = &getAnalysis<LiveIntervals>();
1416 LSs = &getAnalysis<LiveStacks>();
1418 bool MadeChange = false;
1420 // Make sure blocks are numbered in order.
1421 MF.RenumberBlocks();
1423 MachineBasicBlock *Entry = MF.begin();
1424 SmallPtrSet<MachineBasicBlock*,16> Visited;
1426 SmallPtrSet<LiveInterval*, 8> Split;
1428 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
1429 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
1432 for (MachineBasicBlock::iterator I = BarrierMBB->begin(),
1433 E = BarrierMBB->end(); I != E; ++I) {
1435 const TargetRegisterClass **BarrierRCs =
1436 Barrier->getDesc().getRegClassBarriers();
1439 BarrierIdx = LIs->getInstructionIndex(Barrier);
1440 MadeChange |= SplitRegLiveIntervals(BarrierRCs, Split);
1444 MadeChange |= removeDeadSpills(Split);