1 //===---------------------- ProcessImplicitDefs.cpp -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "processimplicitdefs"
12 #include "llvm/CodeGen/ProcessImplicitDefs.h"
14 #include "llvm/ADT/DepthFirstIterator.h"
15 #include "llvm/ADT/SmallSet.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
28 char ProcessImplicitDefs::ID = 0;
29 static RegisterPass<ProcessImplicitDefs> X("processimpdefs",
30 "Process Implicit Definitions.");
32 void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
34 AU.addPreserved<AliasAnalysis>();
35 AU.addPreserved<LiveVariables>();
36 AU.addRequired<LiveVariables>();
37 AU.addPreservedID(MachineLoopInfoID);
38 AU.addPreservedID(MachineDominatorsID);
39 AU.addPreservedID(TwoAddressInstructionPassID);
40 AU.addPreservedID(PHIEliminationID);
41 MachineFunctionPass::getAnalysisUsage(AU);
44 bool ProcessImplicitDefs::CanTurnIntoImplicitDef(MachineInstr *MI,
45 unsigned Reg, unsigned OpIdx,
46 const TargetInstrInfo *tii_) {
47 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
48 if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
49 Reg == SrcReg && DstSubReg == 0)
53 case 1: return (MI->isExtractSubreg() || MI->isCopy()) &&
54 MI->getOperand(0).getSubReg() == 0;
55 case 2: return MI->isSubregToReg() && MI->getOperand(0).getSubReg() == 0;
56 default: return false;
60 /// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure
61 /// there is one implicit_def for each use. Add isUndef marker to
62 /// implicit_def defs and their uses.
63 bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
65 DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
66 << "********** Function: "
67 << ((Value*)fn.getFunction())->getName() << '\n');
71 const TargetInstrInfo *tii_ = fn.getTarget().getInstrInfo();
72 const TargetRegisterInfo *tri_ = fn.getTarget().getRegisterInfo();
73 MachineRegisterInfo *mri_ = &fn.getRegInfo();
75 LiveVariables *lv_ = &getAnalysis<LiveVariables>();
77 SmallSet<unsigned, 8> ImpDefRegs;
78 SmallVector<MachineInstr*, 8> ImpDefMIs;
79 SmallVector<MachineInstr*, 4> RUses;
80 SmallPtrSet<MachineBasicBlock*,16> Visited;
81 SmallPtrSet<MachineInstr*, 8> ModInsts;
83 MachineBasicBlock *Entry = fn.begin();
84 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
85 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
87 MachineBasicBlock *MBB = *DFI;
88 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
90 MachineInstr *MI = &*I;
92 if (MI->isImplicitDef()) {
93 if (MI->getOperand(0).getSubReg())
95 unsigned Reg = MI->getOperand(0).getReg();
96 ImpDefRegs.insert(Reg);
97 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
98 for (const unsigned *SS = tri_->getSubRegisters(Reg); *SS; ++SS)
99 ImpDefRegs.insert(*SS);
101 ImpDefMIs.push_back(MI);
105 if (MI->isInsertSubreg()) {
106 MachineOperand &MO = MI->getOperand(2);
107 if (ImpDefRegs.count(MO.getReg())) {
108 // %reg1032<def> = INSERT_SUBREG %reg1032, undef, 2
109 // This is an identity copy, eliminate it now.
111 LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
114 MI->eraseFromParent();
120 bool ChangedToImpDef = false;
121 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
122 MachineOperand& MO = MI->getOperand(i);
123 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
125 unsigned Reg = MO.getReg();
128 if (!ImpDefRegs.count(Reg))
130 // Use is a copy, just turn it into an implicit_def.
131 if (CanTurnIntoImplicitDef(MI, Reg, i, tii_)) {
132 bool isKill = MO.isKill();
133 MI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF));
134 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
135 MI->RemoveOperand(j);
137 ImpDefRegs.erase(Reg);
138 LiveVariables::VarInfo& vi = lv_->getVarInfo(Reg);
141 ChangedToImpDef = true;
148 if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
149 // Make sure other uses of
150 for (unsigned j = i+1; j != e; ++j) {
151 MachineOperand &MOJ = MI->getOperand(j);
152 if (MOJ.isReg() && MOJ.isUse() && MOJ.getReg() == Reg)
155 ImpDefRegs.erase(Reg);
159 if (ChangedToImpDef) {
160 // Backtrack to process this new implicit_def.
163 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
164 MachineOperand& MO = MI->getOperand(i);
165 if (!MO.isReg() || !MO.isDef())
167 ImpDefRegs.erase(MO.getReg());
172 // Any outstanding liveout implicit_def's?
173 for (unsigned i = 0, e = ImpDefMIs.size(); i != e; ++i) {
174 MachineInstr *MI = ImpDefMIs[i];
175 unsigned Reg = MI->getOperand(0).getReg();
176 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
177 !ImpDefRegs.count(Reg)) {
178 // Delete all "local" implicit_def's. That include those which define
179 // physical registers since they cannot be liveout.
180 MI->eraseFromParent();
185 // If there are multiple defs of the same register and at least one
186 // is not an implicit_def, do not insert implicit_def's before the
189 SmallVector<MachineInstr*, 4> DeadImpDefs;
190 for (MachineRegisterInfo::def_iterator DI = mri_->def_begin(Reg),
191 DE = mri_->def_end(); DI != DE; ++DI) {
192 MachineInstr *DeadImpDef = &*DI;
193 if (!DeadImpDef->isImplicitDef()) {
197 DeadImpDefs.push_back(DeadImpDef);
202 // The only implicit_def which we want to keep are those that are live
204 for (unsigned j = 0, ee = DeadImpDefs.size(); j != ee; ++j)
205 DeadImpDefs[j]->eraseFromParent();
208 // Process each use instruction once.
209 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
210 UE = mri_->use_end(); UI != UE; ++UI) {
211 if (UI.getOperand().isUndef())
213 MachineInstr *RMI = &*UI;
214 if (ModInsts.insert(RMI))
215 RUses.push_back(RMI);
218 for (unsigned i = 0, e = RUses.size(); i != e; ++i) {
219 MachineInstr *RMI = RUses[i];
221 // Turn a copy use into an implicit_def.
222 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
223 if ((RMI->isCopy() && RMI->getOperand(1).getReg() == Reg &&
224 RMI->getOperand(0).getSubReg() == 0) ||
225 (tii_->isMoveInstr(*RMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
226 Reg == SrcReg && DstSubReg == 0)) {
227 RMI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF));
230 SmallVector<unsigned, 4> Ops;
231 for (unsigned j = 0, ee = RMI->getNumOperands(); j != ee; ++j) {
232 MachineOperand &RRMO = RMI->getOperand(j);
233 if (RRMO.isReg() && RRMO.getReg() == Reg) {
239 // Leave the other operands along.
240 for (unsigned j = 0, ee = Ops.size(); j != ee; ++j) {
241 unsigned OpIdx = Ops[j];
242 RMI->RemoveOperand(OpIdx-j);
245 // Update LiveVariables varinfo if the instruction is a kill.
247 LiveVariables::VarInfo& vi = lv_->getVarInfo(Reg);
253 // Replace Reg with a new vreg that's marked implicit.
254 const TargetRegisterClass* RC = mri_->getRegClass(Reg);
255 unsigned NewVReg = mri_->createVirtualRegister(RC);
257 for (unsigned j = 0, ee = RMI->getNumOperands(); j != ee; ++j) {
258 MachineOperand &RRMO = RMI->getOperand(j);
259 if (RRMO.isReg() && RRMO.getReg() == Reg) {
260 RRMO.setReg(NewVReg);
263 // Only the first operand of NewVReg is marked kill.