1 //===---------------------------------------------------------------------===//
3 Common register allocation / spilling problem:
21 and then "merge" mul and mov:
29 It also increase the likelyhood the store may become dead.
31 //===---------------------------------------------------------------------===//
33 I think we should have a "hasSideEffects" flag (which is automatically set for
34 stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
35 to remat any instruction that has no side effects, if it can handle it and if
38 For now, I'd suggest having the remat stuff work like this:
40 1. I need to spill/reload this thing.
41 2. Check to see if it has side effects.
42 3. Check to see if it is simple enough: e.g. it only has one register
43 destination and no register input.
44 4. If so, clone the instruction, do the xform, etc.
46 Advantages of this are:
48 1. the .td file describes the behavior of the instructions, not the way the
49 algorithm should work.
50 2. as remat gets smarter in the future, we shouldn't have to be changing the .td
52 3. it is easier to explain what the flag means in the .td file, because you
53 don't have to pull in the explanation of how the current remat algo works.
55 Some potential added complexities:
57 1. Some instructions have to be glued to it's predecessor or successor. All of
58 the PC relative instructions and condition code setting instruction. We could
59 mark them as hasSideEffects, but that's not quite right. PC relative loads
60 from constantpools can be remat'ed, for example. But it requires more than
61 just cloning the instruction. Some instructions can be remat'ed but it
62 expands to more than one instruction. But allocator will have to make a
65 4. As stated in 3, not as simple as cloning in some cases. The target will have
66 to decide how to remat it. For example, an ARM 2-piece constant generation
67 instruction is remat'ed as a load from constantpool.
69 //===---------------------------------------------------------------------===//
73 %reg1037 = ADDri %reg1039, 1
74 %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
75 Successors according to CFG: 0x8b03bf0 (#5)
77 bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
78 Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
79 %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>
81 Note ADDri is not a two-address instruction. However, its result %reg1037 is an
82 operand of the PHI node in bb76 and its operand %reg1039 is the result of the
83 PHI node. We should treat it as a two-address code and make sure the ADDri is
84 scheduled after any node that reads %reg1039.
86 //===---------------------------------------------------------------------===//
88 Re-Materialize load from frame index.