1 //===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RegAllocBase class, which is the skeleton of a basic
11 // register allocation algorithm and interface for extending it. It provides the
12 // building blocks on which to construct other experimental allocators and test
13 // the validity of two principles:
15 // - If virtual and physical register liveness is modeled using intervals, then
16 // on-the-fly interference checking is cheap. Furthermore, interferences can be
17 // lazily cached and reused.
19 // - Register allocation complexity, and generated code performance is
20 // determined by the effectiveness of live range splitting rather than optimal
23 // Following the first principle, interfering checking revolves around the
24 // LiveIntervalUnion data structure.
26 // To fulfill the second principle, the basic allocator provides a driver for
27 // incremental splitting. It essentially punts on the problem of register
28 // coloring, instead driving the assignment of virtual to physical registers by
29 // the cost of splitting. The basic allocator allows for heuristic reassignment
30 // of registers, if a more sophisticated allocator chooses to do that.
32 // This framework provides a way to engineer the compile time vs. code
33 // quality trade-off without relying a particular theoretical solver.
35 //===----------------------------------------------------------------------===//
37 #ifndef LLVM_CODEGEN_REGALLOCBASE
38 #define LLVM_CODEGEN_REGALLOCBASE
40 #include "llvm/ADT/OwningPtr.h"
41 #include "LiveIntervalUnion.h"
46 template<typename T> class SmallVectorImpl;
47 class TargetRegisterInfo;
52 // Forward declare a priority queue of live virtual registers. If an
53 // implementation needs to prioritize by anything other than spill weight, then
54 // this will become an abstract base class with virtual calls to push/get.
55 class LiveVirtRegQueue;
57 /// RegAllocBase provides the register allocation driver and interface that can
58 /// be extended to add interesting heuristics.
60 /// Register allocators must override the selectOrSplit() method to implement
61 /// live range splitting. They may also override getPriority() which otherwise
62 /// defaults to the spill weight computed by CalculateSpillWeights.
64 LiveIntervalUnion::Allocator UnionAllocator;
66 // Array of LiveIntervalUnions indexed by physical register.
67 class LiveUnionArray {
69 LiveIntervalUnion *Array;
71 LiveUnionArray(): NumRegs(0), Array(0) {}
72 ~LiveUnionArray() { clear(); }
74 unsigned numRegs() const { return NumRegs; }
76 void init(LiveIntervalUnion::Allocator &, unsigned NRegs);
80 LiveIntervalUnion& operator[](unsigned PhysReg) {
81 assert(PhysReg < NumRegs && "physReg out of bounds");
82 return Array[PhysReg];
86 const TargetRegisterInfo *TRI;
87 MachineRegisterInfo *MRI;
90 LiveUnionArray PhysReg2LiveUnion;
92 // Current queries, one per physreg. They must be reinitialized each time we
93 // query on a new live virtual register.
94 OwningArrayPtr<LiveIntervalUnion::Query> Queries;
96 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0) {}
98 virtual ~RegAllocBase() {}
100 // A RegAlloc pass should call this before allocatePhysRegs.
101 void init(VirtRegMap &vrm, LiveIntervals &lis);
103 // Get an initialized query to check interferences between lvr and preg. Note
104 // that Query::init must be called at least once for each physical register
105 // before querying a new live virtual register. This ties Queries and
106 // PhysReg2LiveUnion together.
107 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) {
108 Queries[PhysReg].init(&VirtReg, &PhysReg2LiveUnion[PhysReg]);
109 return Queries[PhysReg];
112 // The top-level driver. The output is a VirtRegMap that us updated with
113 // physical register assignments.
115 // If an implementation wants to override the LiveInterval comparator, we
116 // should modify this interface to allow passing in an instance derived from
118 void allocatePhysRegs();
120 // Get a temporary reference to a Spiller instance.
121 virtual Spiller &spiller() = 0;
123 // getPriority - Calculate the allocation priority for VirtReg.
124 // Virtual registers with higher priorities are allocated first.
125 virtual float getPriority(LiveInterval *LI) = 0;
127 // A RegAlloc pass should override this to provide the allocation heuristics.
128 // Each call must guarantee forward progess by returning an available PhysReg
129 // or new set of split live virtual registers. It is up to the splitter to
130 // converge quickly toward fully spilled live ranges.
131 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
132 SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
134 // A RegAlloc pass should call this when PassManager releases its memory.
135 virtual void releaseMemory();
137 // Helper for checking interference between a live virtual register and a
138 // physical register, including all its register aliases. If an interference
139 // exists, return the interfering register, which may be preg or an alias.
140 unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg);
142 // Helper for spilling all live virtual registers currently unified under preg
143 // that interfere with the most recently queried lvr. Return true if spilling
144 // was successful, and append any new spilled/split intervals to splitLVRs.
145 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
146 SmallVectorImpl<LiveInterval*> &SplitVRegs);
148 /// addMBBLiveIns - Add physreg liveins to basic blocks.
149 void addMBBLiveIns(MachineFunction *);
152 // Verify each LiveIntervalUnion.
156 // Use this group name for NamedRegionTimer.
157 static const char *TimerGroupName;
160 /// VerifyEnabled - True when -verify-regalloc is given.
161 static bool VerifyEnabled;
164 void seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> >&);
166 void spillReg(LiveInterval &VirtReg, unsigned PhysReg,
167 SmallVectorImpl<LiveInterval*> &SplitVRegs);
170 } // end namespace llvm
172 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE)