1 //===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RegAllocBase class, which is the skeleton of a basic
11 // register allocation algorithm and interface for extending it. It provides the
12 // building blocks on which to construct other experimental allocators and test
13 // the validity of two principles:
15 // - If virtual and physical register liveness is modeled using intervals, then
16 // on-the-fly interference checking is cheap. Furthermore, interferences can be
17 // lazily cached and reused.
19 // - Register allocation complexity, and generated code performance is
20 // determined by the effectiveness of live range splitting rather than optimal
23 // Following the first principle, interfering checking revolves around the
24 // LiveIntervalUnion data structure.
26 // To fulfill the second principle, the basic allocator provides a driver for
27 // incremental splitting. It essentially punts on the problem of register
28 // coloring, instead driving the assignment of virtual to physical registers by
29 // the cost of splitting. The basic allocator allows for heuristic reassignment
30 // of registers, if a more sophisticated allocator chooses to do that.
32 // This framework provides a way to engineer the compile time vs. code
33 // quality trade-off without relying a particular theoretical solver.
35 //===----------------------------------------------------------------------===//
37 #ifndef LLVM_CODEGEN_REGALLOCBASE
38 #define LLVM_CODEGEN_REGALLOCBASE
40 #include "llvm/ADT/OwningPtr.h"
41 #include "LiveIntervalUnion.h"
45 template<typename T> class SmallVectorImpl;
46 class TargetRegisterInfo;
51 // Heuristic that determines the priority of assigning virtual to physical
52 // registers. The main impact of the heuristic is expected to be compile time.
53 // The default is to simply compare spill weights.
54 struct LessSpillWeightPriority
55 : public std::binary_function<LiveInterval,LiveInterval, bool> {
56 bool operator()(const LiveInterval *Left, const LiveInterval *Right) const {
57 return Left->weight < Right->weight;
61 // Forward declare a priority queue of live virtual registers. If an
62 // implementation needs to prioritize by anything other than spill weight, then
63 // this will become an abstract base class with virtual calls to push/get.
64 class LiveVirtRegQueue;
66 /// RegAllocBase provides the register allocation driver and interface that can
67 /// be extended to add interesting heuristics.
69 /// Register allocators must override the selectOrSplit() method to implement
70 /// live range splitting. LessSpillWeightPriority is provided as a standard
71 /// comparator, but we may add an interface to override it if necessary.
73 LiveIntervalUnion::Allocator UnionAllocator;
75 // Array of LiveIntervalUnions indexed by physical register.
76 class LiveUnionArray {
78 LiveIntervalUnion *Array;
80 LiveUnionArray(): NumRegs(0), Array(0) {}
81 ~LiveUnionArray() { clear(); }
83 unsigned numRegs() const { return NumRegs; }
85 void init(LiveIntervalUnion::Allocator &, unsigned NRegs);
89 LiveIntervalUnion& operator[](unsigned PhysReg) {
90 assert(PhysReg < NumRegs && "physReg out of bounds");
91 return Array[PhysReg];
95 const TargetRegisterInfo *TRI;
98 LiveUnionArray PhysReg2LiveUnion;
100 // Current queries, one per physreg. They must be reinitialized each time we
101 // query on a new live virtual register.
102 OwningArrayPtr<LiveIntervalUnion::Query> Queries;
104 RegAllocBase(): TRI(0), VRM(0), LIS(0) {}
106 virtual ~RegAllocBase() {}
108 // A RegAlloc pass should call this before allocatePhysRegs.
109 void init(const TargetRegisterInfo &tri, VirtRegMap &vrm, LiveIntervals &lis);
111 // Get an initialized query to check interferences between lvr and preg. Note
112 // that Query::init must be called at least once for each physical register
113 // before querying a new live virtual register. This ties Queries and
114 // PhysReg2LiveUnion together.
115 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) {
116 Queries[PhysReg].init(&VirtReg, &PhysReg2LiveUnion[PhysReg]);
117 return Queries[PhysReg];
120 // The top-level driver. The output is a VirtRegMap that us updated with
121 // physical register assignments.
123 // If an implementation wants to override the LiveInterval comparator, we
124 // should modify this interface to allow passing in an instance derived from
126 void allocatePhysRegs();
128 // Get a temporary reference to a Spiller instance.
129 virtual Spiller &spiller() = 0;
131 // A RegAlloc pass should override this to provide the allocation heuristics.
132 // Each call must guarantee forward progess by returning an available PhysReg
133 // or new set of split live virtual registers. It is up to the splitter to
134 // converge quickly toward fully spilled live ranges.
135 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
136 SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
138 // A RegAlloc pass should call this when PassManager releases its memory.
139 virtual void releaseMemory();
141 // Helper for checking interference between a live virtual register and a
142 // physical register, including all its register aliases. If an interference
143 // exists, return the interfering register, which may be preg or an alias.
144 unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg);
146 // Helper for spilling all live virtual registers currently unified under preg
147 // that interfere with the most recently queried lvr. Return true if spilling
148 // was successful, and append any new spilled/split intervals to splitLVRs.
149 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
150 SmallVectorImpl<LiveInterval*> &SplitVRegs);
153 // Verify each LiveIntervalUnion.
158 void seedLiveVirtRegs(LiveVirtRegQueue &VirtRegQ);
160 void spillReg(LiveInterval &VirtReg, unsigned PhysReg,
161 SmallVectorImpl<LiveInterval*> &SplitVRegs);
164 } // end namespace llvm
166 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE)