1 //===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RegAllocBase class, which is the skeleton of a basic
11 // register allocation algorithm and interface for extending it. It provides the
12 // building blocks on which to construct other experimental allocators and test
13 // the validity of two principles:
15 // - If virtual and physical register liveness is modeled using intervals, then
16 // on-the-fly interference checking is cheap. Furthermore, interferences can be
17 // lazily cached and reused.
19 // - Register allocation complexity, and generated code performance is
20 // determined by the effectiveness of live range splitting rather than optimal
23 // Following the first principle, interfering checking revolves around the
24 // LiveIntervalUnion data structure.
26 // To fulfill the second principle, the basic allocator provides a driver for
27 // incremental splitting. It essentially punts on the problem of register
28 // coloring, instead driving the assignment of virtual to physical registers by
29 // the cost of splitting. The basic allocator allows for heuristic reassignment
30 // of registers, if a more sophisticated allocator chooses to do that.
32 // This framework provides a way to engineer the compile time vs. code
33 // quality trade-off without relying on a particular theoretical solver.
35 //===----------------------------------------------------------------------===//
37 #ifndef LLVM_CODEGEN_REGALLOCBASE
38 #define LLVM_CODEGEN_REGALLOCBASE
40 #include "LiveIntervalUnion.h"
41 #include "llvm/CodeGen/RegisterClassInfo.h"
42 #include "llvm/ADT/OwningPtr.h"
46 template<typename T> class SmallVectorImpl;
47 class TargetRegisterInfo;
53 /// RegAllocBase provides the register allocation driver and interface that can
54 /// be extended to add interesting heuristics.
56 /// Register allocators must override the selectOrSplit() method to implement
57 /// live range splitting. They must also override enqueue/dequeue to provide an
60 LiveIntervalUnion::Allocator UnionAllocator;
62 // Cache tag for PhysReg2LiveUnion entries. Increment whenever virtual
63 // registers may have changed.
66 LiveIntervalUnion::Array PhysReg2LiveUnion;
68 // Current queries, one per physreg. They must be reinitialized each time we
69 // query on a new live virtual register.
70 OwningArrayPtr<LiveIntervalUnion::Query> Queries;
73 const TargetRegisterInfo *TRI;
74 MachineRegisterInfo *MRI;
77 LiveRegMatrix *Matrix;
78 RegisterClassInfo RegClassInfo;
80 RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
82 virtual ~RegAllocBase() {}
84 // A RegAlloc pass should call this before allocatePhysRegs.
85 void init(VirtRegMap &vrm, LiveIntervals &lis);
87 // Get an initialized query to check interferences between lvr and preg. Note
88 // that Query::init must be called at least once for each physical register
89 // before querying a new live virtual register. This ties Queries and
90 // PhysReg2LiveUnion together.
91 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) {
92 Queries[PhysReg].init(UserTag, &VirtReg, &PhysReg2LiveUnion[PhysReg]);
93 return Queries[PhysReg];
96 // Get direct access to the underlying LiveIntervalUnion for PhysReg.
97 LiveIntervalUnion &getLiveUnion(unsigned PhysReg) {
98 return PhysReg2LiveUnion[PhysReg];
101 // Invalidate all cached information about virtual registers - live ranges may
103 void invalidateVirtRegs() { ++UserTag; }
105 // The top-level driver. The output is a VirtRegMap that us updated with
106 // physical register assignments.
107 void allocatePhysRegs();
109 // Get a temporary reference to a Spiller instance.
110 virtual Spiller &spiller() = 0;
112 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
113 virtual void enqueue(LiveInterval *LI) = 0;
115 /// dequeue - Return the next unassigned register, or NULL.
116 virtual LiveInterval *dequeue() = 0;
118 // A RegAlloc pass should override this to provide the allocation heuristics.
119 // Each call must guarantee forward progess by returning an available PhysReg
120 // or new set of split live virtual registers. It is up to the splitter to
121 // converge quickly toward fully spilled live ranges.
122 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
123 SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
125 // A RegAlloc pass should call this when PassManager releases its memory.
126 virtual void releaseMemory();
128 // Helper for checking interference between a live virtual register and a
129 // physical register, including all its register aliases. If an interference
130 // exists, return the interfering register, which may be preg or an alias.
131 unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg);
133 /// assign - Assign VirtReg to PhysReg.
134 /// This should not be called from selectOrSplit for the current register.
135 void assign(LiveInterval &VirtReg, unsigned PhysReg);
137 /// unassign - Undo a previous assignment of VirtReg to PhysReg.
138 /// This can be invoked from selectOrSplit, but be careful to guarantee that
139 /// allocation is making progress.
140 void unassign(LiveInterval &VirtReg, unsigned PhysReg);
143 // Verify each LiveIntervalUnion.
147 // Use this group name for NamedRegionTimer.
148 static const char *TimerGroupName;
151 /// VerifyEnabled - True when -verify-regalloc is given.
152 static bool VerifyEnabled;
158 } // end namespace llvm
160 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE)