1 //===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RegAllocBase class, which is the skeleton of a basic
11 // register allocation algorithm and interface for extending it. It provides the
12 // building blocks on which to construct other experimental allocators and test
13 // the validity of two principles:
15 // - If virtual and physical register liveness is modeled using intervals, then
16 // on-the-fly interference checking is cheap. Furthermore, interferences can be
17 // lazily cached and reused.
19 // - Register allocation complexity, and generated code performance is
20 // determined by the effectiveness of live range splitting rather than optimal
23 // Following the first principle, interfering checking revolves around the
24 // LiveIntervalUnion data structure.
26 // To fulfill the second principle, the basic allocator provides a driver for
27 // incremental splitting. It essentially punts on the problem of register
28 // coloring, instead driving the assignment of virtual to physical registers by
29 // the cost of splitting. The basic allocator allows for heuristic reassignment
30 // of registers, if a more sophisticated allocator chooses to do that.
32 // This framework provides a way to engineer the compile time vs. code
33 // quality trade-off without relying on a particular theoretical solver.
35 //===----------------------------------------------------------------------===//
37 #ifndef LLVM_CODEGEN_REGALLOCBASE
38 #define LLVM_CODEGEN_REGALLOCBASE
40 #include "llvm/ADT/OwningPtr.h"
41 #include "LiveIntervalUnion.h"
42 #include "RegisterClassInfo.h"
46 template<typename T> class SmallVectorImpl;
47 class TargetRegisterInfo;
52 /// RegAllocBase provides the register allocation driver and interface that can
53 /// be extended to add interesting heuristics.
55 /// Register allocators must override the selectOrSplit() method to implement
56 /// live range splitting. They must also override enqueue/dequeue to provide an
59 LiveIntervalUnion::Allocator UnionAllocator;
61 // Cache tag for PhysReg2LiveUnion entries. Increment whenever virtual
62 // registers may have changed.
65 LiveIntervalUnion::Array PhysReg2LiveUnion;
67 // Current queries, one per physreg. They must be reinitialized each time we
68 // query on a new live virtual register.
69 OwningArrayPtr<LiveIntervalUnion::Query> Queries;
72 const TargetRegisterInfo *TRI;
73 MachineRegisterInfo *MRI;
76 RegisterClassInfo RegClassInfo;
78 RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0) {}
80 virtual ~RegAllocBase() {}
82 // A RegAlloc pass should call this before allocatePhysRegs.
83 void init(VirtRegMap &vrm, LiveIntervals &lis);
85 // Get an initialized query to check interferences between lvr and preg. Note
86 // that Query::init must be called at least once for each physical register
87 // before querying a new live virtual register. This ties Queries and
88 // PhysReg2LiveUnion together.
89 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) {
90 Queries[PhysReg].init(UserTag, &VirtReg, &PhysReg2LiveUnion[PhysReg]);
91 return Queries[PhysReg];
94 // Get direct access to the underlying LiveIntervalUnion for PhysReg.
95 LiveIntervalUnion &getLiveUnion(unsigned PhysReg) {
96 return PhysReg2LiveUnion[PhysReg];
99 // Invalidate all cached information about virtual registers - live ranges may
101 void invalidateVirtRegs() { ++UserTag; }
103 // The top-level driver. The output is a VirtRegMap that us updated with
104 // physical register assignments.
105 void allocatePhysRegs();
107 // Get a temporary reference to a Spiller instance.
108 virtual Spiller &spiller() = 0;
110 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
111 virtual void enqueue(LiveInterval *LI) = 0;
113 /// dequeue - Return the next unassigned register, or NULL.
114 virtual LiveInterval *dequeue() = 0;
116 // A RegAlloc pass should override this to provide the allocation heuristics.
117 // Each call must guarantee forward progess by returning an available PhysReg
118 // or new set of split live virtual registers. It is up to the splitter to
119 // converge quickly toward fully spilled live ranges.
120 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
121 SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
123 // A RegAlloc pass should call this when PassManager releases its memory.
124 virtual void releaseMemory();
126 // Helper for checking interference between a live virtual register and a
127 // physical register, including all its register aliases. If an interference
128 // exists, return the interfering register, which may be preg or an alias.
129 unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg);
131 /// assign - Assign VirtReg to PhysReg.
132 /// This should not be called from selectOrSplit for the current register.
133 void assign(LiveInterval &VirtReg, unsigned PhysReg);
135 /// unassign - Undo a previous assignment of VirtReg to PhysReg.
136 /// This can be invoked from selectOrSplit, but be careful to guarantee that
137 /// allocation is making progress.
138 void unassign(LiveInterval &VirtReg, unsigned PhysReg);
140 /// addMBBLiveIns - Add physreg liveins to basic blocks.
141 void addMBBLiveIns(MachineFunction *);
144 // Verify each LiveIntervalUnion.
148 // Use this group name for NamedRegionTimer.
149 static const char *TimerGroupName;
152 /// VerifyEnabled - True when -verify-regalloc is given.
153 static bool VerifyEnabled;
159 } // end namespace llvm
161 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE)