1 //===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RegAllocBase class, which is the skeleton of a basic
11 // register allocation algorithm and interface for extending it. It provides the
12 // building blocks on which to construct other experimental allocators and test
13 // the validity of two principles:
15 // - If virtual and physical register liveness is modeled using intervals, then
16 // on-the-fly interference checking is cheap. Furthermore, interferences can be
17 // lazily cached and reused.
19 // - Register allocation complexity, and generated code performance is
20 // determined by the effectiveness of live range splitting rather than optimal
23 // Following the first principle, interfering checking revolves around the
24 // LiveIntervalUnion data structure.
26 // To fulfill the second principle, the basic allocator provides a driver for
27 // incremental splitting. It essentially punts on the problem of register
28 // coloring, instead driving the assignment of virtual to physical registers by
29 // the cost of splitting. The basic allocator allows for heuristic reassignment
30 // of registers, if a more sophisticated allocator chooses to do that.
32 // This framework provides a way to engineer the compile time vs. code
33 // quality trade-off without relying a particular theoretical solver.
35 //===----------------------------------------------------------------------===//
37 #ifndef LLVM_CODEGEN_REGALLOCBASE
38 #define LLVM_CODEGEN_REGALLOCBASE
40 #include "llvm/ADT/OwningPtr.h"
44 template<typename T> class SmallVectorImpl;
45 class TargetRegisterInfo;
49 // Heuristic that determines the priority of assigning virtual to physical
50 // registers. The main impact of the heuristic is expected to be compile time.
51 // The default is to simply compare spill weights.
52 struct LessSpillWeightPriority
53 : public std::binary_function<LiveInterval,LiveInterval, bool> {
54 bool operator()(const LiveInterval *left, const LiveInterval *right) const {
55 return left->weight < right->weight;
59 // Forward declare a priority queue of live virtual registers. If an
60 // implementation needs to prioritize by anything other than spill weight, then
61 // this will become an abstract base class with virtual calls to push/get.
62 class LiveVirtRegQueue;
64 /// RegAllocBase provides the register allocation driver and interface that can
65 /// be extended to add interesting heuristics.
67 /// More sophisticated allocators must override the selectOrSplit() method to
68 /// implement live range splitting and must specify a comparator to determine
69 /// register assignment priority. LessSpillWeightPriority is provided as a
70 /// standard comparator.
73 // Array of LiveIntervalUnions indexed by physical register.
76 OwningArrayPtr<LiveIntervalUnion> array_;
78 LIUArray(): nRegs_(0) {}
80 unsigned numRegs() const { return nRegs_; }
82 void init(unsigned nRegs);
86 LiveIntervalUnion& operator[](unsigned physReg) {
87 assert(physReg < nRegs_ && "physReg out of bounds");
88 return array_[physReg];
92 const TargetRegisterInfo *tri_;
95 LIUArray physReg2liu_;
97 // Current queries, one per physreg. They must be reinitialized each time we
98 // query on a new live virtual register.
99 OwningArrayPtr<LiveIntervalUnion::Query> queries_;
101 RegAllocBase(): tri_(0), vrm_(0), lis_(0) {}
103 virtual ~RegAllocBase() {}
105 // A RegAlloc pass should call this before allocatePhysRegs.
106 void init(const TargetRegisterInfo &tri, VirtRegMap &vrm, LiveIntervals &lis);
108 // The top-level driver. The output is a VirtRegMap that us updated with
109 // physical register assignments.
111 // If an implementation wants to override the LiveInterval comparator, we
112 // should modify this interface to allow passing in an instance derived from
114 void allocatePhysRegs();
116 // A RegAlloc pass should override this to provide the allocation heuristics.
117 // Each call must guarantee forward progess by returning an available PhysReg
118 // or new set of split live virtual registers. It is up to the splitter to
119 // converge quickly toward fully spilled live ranges.
120 virtual unsigned selectOrSplit(LiveInterval &lvr,
121 SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
123 // A RegAlloc pass should call this when PassManager releases its memory.
124 virtual void releaseMemory();
126 // Helper for checking interference between a live virtual register and a
127 // physical register, including all its register aliases. If an interference
128 // exists, return the interfering register, which may be preg or an alias.
129 unsigned checkPhysRegInterference(LiveInterval& lvr, unsigned preg);
131 // Helper that spills all live virtual registers currently unified under preg
132 // that interfere with the most recently queried lvr.
133 void spillInterferences(unsigned preg,
134 SmallVectorImpl<LiveInterval*> &splitLVRs);
137 void seedLiveVirtRegs(LiveVirtRegQueue &lvrQ);
140 } // end namespace llvm
142 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE)