1 //===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "RegAllocBase.h"
17 #include "RenderMachineFunction.h"
19 #include "VirtRegRewriter.h"
20 #include "llvm/Function.h"
21 #include "llvm/PassAnalysisSupport.h"
22 #include "llvm/CodeGen/CalcSpillWeights.h"
23 #include "llvm/CodeGen/LiveStackAnalysis.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineLoopInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/RegAllocRegistry.h"
30 #include "llvm/CodeGen/RegisterCoalescer.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/raw_ostream.h"
38 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
39 createBasicRegisterAllocator);
43 /// RABasic provides a minimal implementation of the basic register allocation
44 /// algorithm. It prioritizes live virtual registers by spill weight and spills
45 /// whenever a register is unavailable. This is not practical in production but
46 /// provides a useful baseline both for measuring other allocators and comparing
47 /// the speed of the basic algorithm against other styles of allocators.
48 class RABasic : public MachineFunctionPass, public RegAllocBase
52 const TargetMachine *tm_;
53 MachineRegisterInfo *mri_;
57 RenderMachineFunction *rmf_;
60 std::auto_ptr<Spiller> spiller_;
65 /// Return the pass name.
66 virtual const char* getPassName() const {
67 return "Basic Register Allocator";
70 /// RABasic analysis usage.
71 virtual void getAnalysisUsage(AnalysisUsage &au) const;
73 virtual void releaseMemory();
75 virtual unsigned selectOrSplit(LiveInterval &lvr, LiveVirtRegs &splitLVRs);
77 /// Perform register allocation.
78 virtual bool runOnMachineFunction(MachineFunction &mf);
85 } // end anonymous namespace
87 // We should not need to publish the initializer as long as no other passes
89 #if 0 // disable INITIALIZE_PASS
90 INITIALIZE_PASS_BEGIN(RABasic, "basic-regalloc",
91 "Basic Register Allocator", false, false)
92 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
93 INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
94 INITIALIZE_AG_DEPENDENCY(RegisterCoalescer)
95 INITIALIZE_PASS_DEPENDENCY(CalculateSpillWeights)
96 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
97 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
98 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
100 INITIALIZE_PASS_DEPENDENCY(RenderMachineFunction)
102 INITIALIZE_PASS_END(RABasic, "basic-regalloc",
103 "Basic Register Allocator", false, false)
104 #endif // INITIALIZE_PASS
106 RABasic::RABasic(): MachineFunctionPass(ID) {
107 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
108 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
109 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
110 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
111 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
112 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
113 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
114 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
115 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
118 void RABasic::getAnalysisUsage(AnalysisUsage &au) const {
119 au.setPreservesCFG();
120 au.addRequired<LiveIntervals>();
121 au.addPreserved<SlotIndexes>();
123 au.addRequiredID(StrongPHIEliminationID);
124 au.addRequiredTransitive<RegisterCoalescer>();
125 au.addRequired<CalculateSpillWeights>();
126 au.addRequired<LiveStacks>();
127 au.addPreserved<LiveStacks>();
128 au.addRequired<MachineLoopInfo>();
129 au.addPreserved<MachineLoopInfo>();
130 au.addRequired<VirtRegMap>();
131 au.addPreserved<VirtRegMap>();
132 DEBUG(au.addRequired<RenderMachineFunction>());
133 MachineFunctionPass::getAnalysisUsage(au);
136 void RABasic::releaseMemory() {
138 RegAllocBase::releaseMemory();
141 //===----------------------------------------------------------------------===//
142 // RegAllocBase Implementation
143 //===----------------------------------------------------------------------===//
145 // Instantiate a LiveIntervalUnion for each physical register.
146 void RegAllocBase::LIUArray::init(unsigned nRegs) {
147 array_.reset(new LiveIntervalUnion[nRegs]);
149 for (unsigned pr = 0; pr < nRegs; ++pr) {
154 void RegAllocBase::init(const TargetRegisterInfo &tri, VirtRegMap &vrm,
155 LiveIntervals &lis) {
159 physReg2liu_.init(tri_->getNumRegs());
162 void RegAllocBase::LIUArray::clear() {
167 void RegAllocBase::releaseMemory() {
168 physReg2liu_.clear();
171 // Check if this live virtual reg interferes with a physical register. If not,
172 // then check for interference on each register that aliases with the physical
174 bool RegAllocBase::checkPhysRegInterference(LiveIntervalUnion::Query &query,
176 if (query.checkInterference())
178 for (const unsigned *asI = tri_->getAliasSet(preg); *asI; ++asI) {
179 // We assume it's very unlikely for a register in the alias set to also be
180 // in the original register class. So we don't bother caching the
182 LiveIntervalUnion::Query subQuery(query.lvr(), physReg2liu_[*asI] );
183 if (subQuery.checkInterference())
189 //===----------------------------------------------------------------------===//
190 // RABasic Implementation
191 //===----------------------------------------------------------------------===//
193 // Driver for the register assignment and splitting heuristics.
194 // Manages iteration over the LiveIntervalUnions.
196 // Minimal implementation of register assignment and splitting--spills whenever
197 // we run out of registers.
199 // selectOrSplit can only be called once per live virtual register. We then do a
200 // single interference test for each register the correct class until we find an
201 // available register. So, the number of interference tests in the worst case is
202 // |vregs| * |machineregs|. And since the number of interference tests is
203 // minimal, there is no value in caching them.
204 unsigned RABasic::selectOrSplit(LiveInterval &lvr, LiveVirtRegs &splitLVRs) {
205 // Check for an available reg in this class.
206 const TargetRegisterClass *trc = mri_->getRegClass(lvr.reg);
207 for (TargetRegisterClass::iterator trcI = trc->allocation_order_begin(*mf_),
208 trcEnd = trc->allocation_order_end(*mf_);
209 trcI != trcEnd; ++trcI) {
210 unsigned preg = *trcI;
211 LiveIntervalUnion::Query query(lvr, physReg2liu_[preg]);
212 if (!checkPhysRegInterference(query, preg)) {
213 DEBUG(dbgs() << "\tallocating: " << tri_->getName(preg) << lvr << '\n');
217 DEBUG(dbgs() << "\tspilling: " << lvr << '\n');
218 SmallVector<LiveInterval*, 1> spillIs; // ignored
219 spiller_->spill(&lvr, splitLVRs, spillIs);
221 // FIXME: update LiveStacks
225 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
226 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
227 << "********** Function: "
228 << ((Value*)mf.getFunction())->getName() << '\n');
231 tm_ = &mf.getTarget();
232 mri_ = &mf.getRegInfo();
234 DEBUG(rmf_ = &getAnalysis<RenderMachineFunction>());
236 RegAllocBase::init(*tm_->getRegisterInfo(), getAnalysis<VirtRegMap>(),
237 getAnalysis<LiveIntervals>());
239 spiller_.reset(createSpiller(*this, *mf_, *vrm_));
241 allocatePhysRegs(LessSpillWeightPriority());
243 // Diagnostic output before rewriting
244 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm_ << "\n");
246 // optional HTML output
247 DEBUG(rmf_->renderMachineFunction("After basic register allocation.", vrm_));
250 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
251 rewriter->runOnMachineFunction(*mf_, *vrm_, lis_);
256 FunctionPass* llvm::createBasicRegisterAllocator()
258 return new RABasic();