1 //===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "LiveIntervalUnion.h"
17 #include "RegAllocBase.h"
18 #include "RenderMachineFunction.h"
20 #include "VirtRegMap.h"
21 #include "VirtRegRewriter.h"
22 #include "llvm/ADT/OwningPtr.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/Function.h"
25 #include "llvm/PassAnalysisSupport.h"
26 #include "llvm/CodeGen/CalcSpillWeights.h"
27 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
28 #include "llvm/CodeGen/LiveStackAnalysis.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineLoopInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/RegAllocRegistry.h"
35 #include "llvm/CodeGen/RegisterCoalescer.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/ADT/SparseBitVector.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/raw_ostream.h"
50 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
51 createBasicRegisterAllocator);
53 // Temporary verification option until we can put verification inside
56 VerifyRegAlloc("verify-regalloc",
57 cl::desc("Verify live intervals before renaming"));
61 class PhysicalRegisterDescription : public AbstractRegisterDescription {
62 const TargetRegisterInfo *TRI;
64 PhysicalRegisterDescription(const TargetRegisterInfo *T): TRI(T) {}
65 virtual const char *getName(unsigned Reg) const { return TRI->getName(Reg); }
68 /// RABasic provides a minimal implementation of the basic register allocation
69 /// algorithm. It prioritizes live virtual registers by spill weight and spills
70 /// whenever a register is unavailable. This is not practical in production but
71 /// provides a useful baseline both for measuring other allocators and comparing
72 /// the speed of the basic algorithm against other styles of allocators.
73 class RABasic : public MachineFunctionPass, public RegAllocBase
77 const TargetMachine *TM;
78 MachineRegisterInfo *MRI;
80 BitVector ReservedRegs;
84 RenderMachineFunction *RMF;
87 std::auto_ptr<Spiller> SpillerInstance;
92 /// Return the pass name.
93 virtual const char* getPassName() const {
94 return "Basic Register Allocator";
97 /// RABasic analysis usage.
98 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
100 virtual void releaseMemory();
102 virtual Spiller &spiller() { return *SpillerInstance; }
104 virtual float getPriority(LiveInterval *LI) { return LI->weight; }
106 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
107 SmallVectorImpl<LiveInterval*> &SplitVRegs);
109 /// Perform register allocation.
110 virtual bool runOnMachineFunction(MachineFunction &mf);
115 char RABasic::ID = 0;
117 } // end anonymous namespace
119 RABasic::RABasic(): MachineFunctionPass(ID) {
120 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
121 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
122 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
123 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
124 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
125 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
126 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
127 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
128 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
129 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
132 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
133 AU.setPreservesCFG();
134 AU.addRequired<AliasAnalysis>();
135 AU.addPreserved<AliasAnalysis>();
136 AU.addRequired<LiveIntervals>();
137 AU.addPreserved<SlotIndexes>();
139 AU.addRequiredID(StrongPHIEliminationID);
140 AU.addRequiredTransitive<RegisterCoalescer>();
141 AU.addRequired<CalculateSpillWeights>();
142 AU.addRequired<LiveStacks>();
143 AU.addPreserved<LiveStacks>();
144 AU.addRequiredID(MachineDominatorsID);
145 AU.addPreservedID(MachineDominatorsID);
146 AU.addRequired<MachineLoopInfo>();
147 AU.addPreserved<MachineLoopInfo>();
148 AU.addRequired<VirtRegMap>();
149 AU.addPreserved<VirtRegMap>();
150 DEBUG(AU.addRequired<RenderMachineFunction>());
151 MachineFunctionPass::getAnalysisUsage(AU);
154 void RABasic::releaseMemory() {
155 SpillerInstance.reset(0);
156 RegAllocBase::releaseMemory();
160 // Verify each LiveIntervalUnion.
161 void RegAllocBase::verify() {
162 LiveVirtRegBitSet VisitedVRegs;
163 OwningArrayPtr<LiveVirtRegBitSet>
164 unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
166 // Verify disjoint unions.
167 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
168 DEBUG(PhysicalRegisterDescription PRD(TRI);
169 PhysReg2LiveUnion[PhysReg].dump(&PRD));
170 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
171 PhysReg2LiveUnion[PhysReg].verify(VRegs);
172 // Union + intersection test could be done efficiently in one pass, but
173 // don't add a method to SparseBitVector unless we really need it.
174 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
175 VisitedVRegs |= VRegs;
178 // Verify vreg coverage.
179 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
180 liItr != liEnd; ++liItr) {
181 unsigned reg = liItr->first;
182 if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
183 if (!VRM->hasPhys(reg)) continue; // spilled?
184 unsigned PhysReg = VRM->getPhys(reg);
185 if (!unionVRegs[PhysReg].test(reg)) {
186 dbgs() << "LiveVirtReg " << reg << " not in union " <<
187 TRI->getName(PhysReg) << "\n";
188 llvm_unreachable("unallocated live vreg");
191 // FIXME: I'm not sure how to verify spilled intervals.
195 //===----------------------------------------------------------------------===//
196 // RegAllocBase Implementation
197 //===----------------------------------------------------------------------===//
199 // Instantiate a LiveIntervalUnion for each physical register.
200 void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
204 static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
205 for (unsigned r = 0; r != NRegs; ++r)
206 new(Array + r) LiveIntervalUnion(r, allocator);
209 void RegAllocBase::init(const TargetRegisterInfo &tri, VirtRegMap &vrm,
210 LiveIntervals &lis) {
214 PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
215 // Cache an interferece query for each physical reg
216 Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
219 void RegAllocBase::LiveUnionArray::clear() {
222 for (unsigned r = 0; r != NumRegs; ++r)
223 Array[r].~LiveIntervalUnion();
229 void RegAllocBase::releaseMemory() {
230 PhysReg2LiveUnion.clear();
233 // Visit all the live virtual registers. If they are already assigned to a
234 // physical register, unify them with the corresponding LiveIntervalUnion,
235 // otherwise push them on the priority queue for later assignment.
237 seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> > &VirtRegQ) {
238 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
239 unsigned RegNum = I->first;
240 LiveInterval &VirtReg = *I->second;
241 if (TargetRegisterInfo::isPhysicalRegister(RegNum))
242 PhysReg2LiveUnion[RegNum].unify(VirtReg);
244 VirtRegQ.push(std::make_pair(getPriority(&VirtReg), RegNum));
248 // Top-level driver to manage the queue of unassigned VirtRegs and call the
249 // selectOrSplit implementation.
250 void RegAllocBase::allocatePhysRegs() {
252 // Push each vreg onto a queue or "precolor" by adding it to a physreg union.
253 std::priority_queue<std::pair<float, unsigned> > VirtRegQ;
254 seedLiveVirtRegs(VirtRegQ);
256 // Continue assigning vregs one at a time to available physical registers.
257 while (!VirtRegQ.empty()) {
258 // Pop the highest priority vreg.
259 LiveInterval &VirtReg = LIS->getInterval(VirtRegQ.top().second);
262 // selectOrSplit requests the allocator to return an available physical
263 // register if possible and populate a list of new live intervals that
264 // result from splitting.
265 typedef SmallVector<LiveInterval*, 4> VirtRegVec;
266 VirtRegVec SplitVRegs;
267 unsigned AvailablePhysReg = selectOrSplit(VirtReg, SplitVRegs);
269 if (AvailablePhysReg) {
270 DEBUG(dbgs() << "allocating: " << TRI->getName(AvailablePhysReg) <<
271 " " << VirtReg << '\n');
272 assert(!VRM->hasPhys(VirtReg.reg) && "duplicate vreg in union");
273 VRM->assignVirt2Phys(VirtReg.reg, AvailablePhysReg);
274 PhysReg2LiveUnion[AvailablePhysReg].unify(VirtReg);
276 for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
278 LiveInterval* SplitVirtReg = *I;
279 if (SplitVirtReg->empty()) continue;
280 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
281 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
282 "expect split value in virtual register");
283 VirtRegQ.push(std::make_pair(getPriority(SplitVirtReg),
289 // Check if this live virtual register interferes with a physical register. If
290 // not, then check for interference on each register that aliases with the
291 // physical register. Return the interfering register.
292 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
294 if (query(VirtReg, PhysReg).checkInterference())
296 for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) {
297 if (query(VirtReg, *AliasI).checkInterference())
303 // Helper for spillInteferences() that spills all interfering vregs currently
304 // assigned to this physical register.
305 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
306 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
307 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
308 assert(Q.seenAllInterferences() && "need collectInterferences()");
309 const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
311 for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
312 E = PendingSpills.end(); I != E; ++I) {
313 LiveInterval &SpilledVReg = **I;
314 DEBUG(dbgs() << "extracting from " <<
315 TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
317 // Deallocate the interfering vreg by removing it from the union.
318 // A LiveInterval instance may not be in a union during modification!
319 PhysReg2LiveUnion[PhysReg].extract(SpilledVReg);
321 // Clear the vreg assignment.
322 VRM->clearVirt(SpilledVReg.reg);
324 // Spill the extracted interval.
325 spiller().spill(&SpilledVReg, SplitVRegs, PendingSpills);
327 // After extracting segments, the query's results are invalid. But keep the
328 // contents valid until we're done accessing pendingSpills.
332 // Spill or split all live virtual registers currently unified under PhysReg
333 // that interfere with VirtReg. The newly spilled or split live intervals are
334 // returned by appending them to SplitVRegs.
336 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
337 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
338 // Record each interference and determine if all are spillable before mutating
339 // either the union or live intervals.
341 // Collect interferences assigned to the requested physical register.
342 LiveIntervalUnion::Query &QPreg = query(VirtReg, PhysReg);
343 unsigned NumInterferences = QPreg.collectInterferingVRegs();
344 if (QPreg.seenUnspillableVReg()) {
347 // Collect interferences assigned to any alias of the physical register.
348 for (const unsigned *asI = TRI->getAliasSet(PhysReg); *asI; ++asI) {
349 LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
350 NumInterferences += QAlias.collectInterferingVRegs();
351 if (QAlias.seenUnspillableVReg()) {
355 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
356 " interferences with " << VirtReg << "\n");
357 assert(NumInterferences > 0 && "expect interference");
359 // Spill each interfering vreg allocated to PhysReg or an alias.
360 spillReg(VirtReg, PhysReg, SplitVRegs);
361 for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI)
362 spillReg(VirtReg, *AliasI, SplitVRegs);
366 // Add newly allocated physical registers to the MBB live in sets.
367 void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
368 typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
370 MachineBasicBlock &entryMBB = *MF->begin();
372 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
373 LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
374 if (LiveUnion.empty())
376 for (LiveIntervalUnion::SegmentIter SI = LiveUnion.begin(); SI.valid();
379 // Find the set of basic blocks which this range is live into...
381 if (!LIS->findLiveInMBBs(SI.start(), SI.stop(), liveInMBBs)) continue;
383 // And add the physreg for this interval to their live-in sets.
384 for (MBBVec::iterator I = liveInMBBs.begin(), E = liveInMBBs.end();
386 MachineBasicBlock *MBB = *I;
387 if (MBB == &entryMBB) continue;
388 if (MBB->isLiveIn(PhysReg)) continue;
389 MBB->addLiveIn(PhysReg);
396 //===----------------------------------------------------------------------===//
397 // RABasic Implementation
398 //===----------------------------------------------------------------------===//
400 // Driver for the register assignment and splitting heuristics.
401 // Manages iteration over the LiveIntervalUnions.
403 // This is a minimal implementation of register assignment and splitting that
404 // spills whenever we run out of registers.
406 // selectOrSplit can only be called once per live virtual register. We then do a
407 // single interference test for each register the correct class until we find an
408 // available register. So, the number of interference tests in the worst case is
409 // |vregs| * |machineregs|. And since the number of interference tests is
410 // minimal, there is no value in caching them outside the scope of
412 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
413 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
414 // Populate a list of physical register spill candidates.
415 SmallVector<unsigned, 8> PhysRegSpillCands;
417 // Check for an available register in this class.
418 const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
419 DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
421 for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
422 E = TRC->allocation_order_end(*MF);
425 unsigned PhysReg = *I;
426 if (ReservedRegs.test(PhysReg)) continue;
428 // Check interference and as a side effect, intialize queries for this
429 // VirtReg and its aliases.
430 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
431 if (interfReg == 0) {
432 // Found an available register.
435 LiveInterval *interferingVirtReg =
436 Queries[interfReg].firstInterference().liveUnionPos().value();
438 // The current VirtReg must either be spillable, or one of its interferences
439 // must have less spill weight.
440 if (interferingVirtReg->weight < VirtReg.weight ) {
441 PhysRegSpillCands.push_back(PhysReg);
444 // Try to spill another interfering reg with less spill weight.
445 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
446 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
448 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
450 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
451 "Interference after spill.");
452 // Tell the caller to allocate to this newly freed physical register.
455 // No other spill candidates were found, so spill the current VirtReg.
456 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
457 SmallVector<LiveInterval*, 1> pendingSpills;
459 spiller().spill(&VirtReg, SplitVRegs, pendingSpills);
461 // The live virtual register requesting allocation was spilled, so tell
462 // the caller not to allocate anything during this round.
466 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
467 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
468 << "********** Function: "
469 << ((Value*)mf.getFunction())->getName() << '\n');
472 TM = &mf.getTarget();
473 MRI = &mf.getRegInfo();
475 DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
477 const TargetRegisterInfo *TRI = TM->getRegisterInfo();
478 RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(),
479 getAnalysis<LiveIntervals>());
481 ReservedRegs = TRI->getReservedRegs(*MF);
483 SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
489 // Diagnostic output before rewriting
490 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
492 // optional HTML output
493 DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
495 // FIXME: Verification currently must run before VirtRegRewriter. We should
496 // make the rewriter a separate pass and override verifyAnalysis instead. When
497 // that happens, verification naturally falls under VerifyMachineCode.
499 if (VerifyRegAlloc) {
500 // Verify accuracy of LiveIntervals. The standard machine code verifier
501 // ensures that each LiveIntervals covers all uses of the virtual reg.
503 // FIXME: MachineVerifier is badly broken when using the standard
504 // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
505 // inline spiller, some tests fail to verify because the coalescer does not
506 // always generate verifiable code.
509 // Verify that LiveIntervals are partitioned into unions and disjoint within
516 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
517 rewriter->runOnMachineFunction(*MF, *VRM, LIS);
519 // The pass output is in VirtRegMap. Release all the transient data.
525 FunctionPass* llvm::createBasicRegisterAllocator()
527 return new RABasic();