1 //===- RegAllocBigBlock.cpp - A register allocator for large basic blocks -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the RABigBlock class
12 //===----------------------------------------------------------------------===//
14 // This register allocator is derived from RegAllocLocal.cpp. Like it, this
15 // allocator works on one basic block at a time, oblivious to others.
16 // However, the algorithm used here is suited for long blocks of
17 // instructions - registers are spilled by greedily choosing those holding
18 // values that will not be needed for the longest amount of time. This works
19 // particularly well for blocks with 10 or more times as many instructions
20 // as machine registers, but can be used for general code.
22 //===----------------------------------------------------------------------===//
24 // TODO: - automagically invoke linearscan for (groups of) small BBs?
25 // - break ties when picking regs? (probably not worth it in a
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "regalloc"
31 #include "llvm/BasicBlock.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineInstr.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/LiveVariables.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/Compiler.h"
44 #include "llvm/ADT/IndexedMap.h"
45 #include "llvm/ADT/DenseMap.h"
46 #include "llvm/ADT/SmallVector.h"
47 #include "llvm/ADT/SmallPtrSet.h"
48 #include "llvm/ADT/Statistic.h"
52 STATISTIC(NumStores, "Number of stores added");
53 STATISTIC(NumLoads , "Number of loads added");
54 STATISTIC(NumFolded, "Number of loads/stores folded into instructions");
57 static RegisterRegAlloc
58 bigBlockRegAlloc("bigblock", " Big-block register allocator",
59 createBigBlockRegisterAllocator);
61 /// VRegKeyInfo - Defines magic values required to use VirtRegs as DenseMap
64 static inline unsigned getEmptyKey() { return -1U; }
65 static inline unsigned getTombstoneKey() { return -2U; }
66 static bool isEqual(unsigned LHS, unsigned RHS) { return LHS == RHS; }
67 static unsigned getHashValue(const unsigned &Key) { return Key; }
71 /// This register allocator is derived from RegAllocLocal.cpp. Like it, this
72 /// allocator works on one basic block at a time, oblivious to others.
73 /// However, the algorithm used here is suited for long blocks of
74 /// instructions - registers are spilled by greedily choosing those holding
75 /// values that will not be needed for the longest amount of time. This works
76 /// particularly well for blocks with 10 or more times as many instructions
77 /// as machine registers, but can be used for general code.
79 /// TODO: - automagically invoke linearscan for (groups of) small BBs?
80 /// - break ties when picking regs? (probably not worth it in a
83 class VISIBILITY_HIDDEN RABigBlock : public MachineFunctionPass {
86 RABigBlock() : MachineFunctionPass((intptr_t)&ID) {}
88 /// TM - For getting at TargetMachine info
90 const TargetMachine *TM;
92 /// MF - Our generic MachineFunction pointer
96 /// RegInfo - For dealing with machine register info (aliases, folds
98 const MRegisterInfo *RegInfo;
100 typedef SmallVector<unsigned, 2> VRegTimes;
102 /// VRegReadTable - maps VRegs in a BB to the set of times they are read
104 DenseMap<unsigned, VRegTimes*, VRegKeyInfo> VRegReadTable;
106 /// VRegReadIdx - keeps track of the "current time" in terms of
107 /// positions in VRegReadTable
108 DenseMap<unsigned, unsigned , VRegKeyInfo> VRegReadIdx;
110 /// StackSlotForVirtReg - Maps virtual regs to the frame index where these
111 /// values are spilled.
112 IndexedMap<unsigned, VirtReg2IndexFunctor> StackSlotForVirtReg;
114 /// Virt2PhysRegMap - This map contains entries for each virtual register
115 /// that is currently available in a physical register.
116 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
118 /// PhysRegsUsed - This array is effectively a map, containing entries for
119 /// each physical register that currently has a value (ie, it is in
120 /// Virt2PhysRegMap). The value mapped to is the virtual register
121 /// corresponding to the physical register (the inverse of the
122 /// Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
123 /// because it is used by a future instruction, and to -2 if it is not
124 /// allocatable. If the entry for a physical register is -1, then the
125 /// physical register is "not in the map".
127 std::vector<int> PhysRegsUsed;
129 /// VirtRegModified - This bitset contains information about which virtual
130 /// registers need to be spilled back to memory when their registers are
131 /// scavenged. If a virtual register has simply been rematerialized, there
132 /// is no reason to spill it to memory when we need the register back.
134 std::vector<int> VirtRegModified;
136 /// MBBLastInsnTime - the number of the the last instruction in MBB
140 /// MBBCurTime - the number of the the instruction being currently processed
144 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
145 return Virt2PhysRegMap[VirtReg];
148 unsigned &getVirt2StackSlot(unsigned VirtReg) {
149 return StackSlotForVirtReg[VirtReg];
152 /// markVirtRegModified - Lets us flip bits in the VirtRegModified bitset
154 void markVirtRegModified(unsigned Reg, bool Val = true) {
155 assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
156 Reg -= MRegisterInfo::FirstVirtualRegister;
157 if (VirtRegModified.size() <= Reg)
158 VirtRegModified.resize(Reg+1);
159 VirtRegModified[Reg] = Val;
162 /// isVirtRegModified - Lets us query the VirtRegModified bitset
164 bool isVirtRegModified(unsigned Reg) const {
165 assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
166 assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
167 && "Illegal virtual register!");
168 return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister];
172 /// getPassName - returns the BigBlock allocator's name
174 virtual const char *getPassName() const {
175 return "BigBlock Register Allocator";
178 /// getAnalaysisUsage - declares the required analyses
180 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
181 AU.addRequiredID(PHIEliminationID);
182 AU.addRequiredID(TwoAddressInstructionPassID);
183 MachineFunctionPass::getAnalysisUsage(AU);
187 /// runOnMachineFunction - Register allocate the whole function
189 bool runOnMachineFunction(MachineFunction &Fn);
191 /// AllocateBasicBlock - Register allocate the specified basic block.
193 void AllocateBasicBlock(MachineBasicBlock &MBB);
195 /// FillVRegReadTable - Fill out the table of vreg read times given a BB
197 void FillVRegReadTable(MachineBasicBlock &MBB);
199 /// areRegsEqual - This method returns true if the specified registers are
200 /// related to each other. To do this, it checks to see if they are equal
201 /// or if the first register is in the alias set of the second register.
203 bool areRegsEqual(unsigned R1, unsigned R2) const {
204 if (R1 == R2) return true;
205 for (const unsigned *AliasSet = RegInfo->getAliasSet(R2);
206 *AliasSet; ++AliasSet) {
207 if (*AliasSet == R1) return true;
212 /// getStackSpaceFor - This returns the frame index of the specified virtual
213 /// register on the stack, allocating space if necessary.
214 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
216 /// removePhysReg - This method marks the specified physical register as no
217 /// longer being in use.
219 void removePhysReg(unsigned PhysReg);
221 /// spillVirtReg - This method spills the value specified by PhysReg into
222 /// the virtual register slot specified by VirtReg. It then updates the RA
223 /// data structures to indicate the fact that PhysReg is now available.
225 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
226 unsigned VirtReg, unsigned PhysReg);
228 /// spillPhysReg - This method spills the specified physical register into
229 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
230 /// true, then the request is ignored if the physical register does not
231 /// contain a virtual register.
233 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
234 unsigned PhysReg, bool OnlyVirtRegs = false);
236 /// assignVirtToPhysReg - This method updates local state so that we know
237 /// that PhysReg is the proper container for VirtReg now. The physical
238 /// register must not be used for anything else when this is called.
240 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
242 /// isPhysRegAvailable - Return true if the specified physical register is
243 /// free and available for use. This also includes checking to see if
244 /// aliased registers are all free...
246 bool isPhysRegAvailable(unsigned PhysReg) const;
248 /// getFreeReg - Look to see if there is a free register available in the
249 /// specified register class. If not, return 0.
251 unsigned getFreeReg(const TargetRegisterClass *RC);
253 /// chooseReg - Pick a physical register to hold the specified
254 /// virtual register by choosing the one which will be read furthest
257 unsigned chooseReg(MachineBasicBlock &MBB, MachineInstr *MI,
260 /// reloadVirtReg - This method transforms the specified specified virtual
261 /// register use to refer to a physical register. This method may do this
262 /// in one of several ways: if the register is available in a physical
263 /// register already, it uses that physical register. If the value is not
264 /// in a physical register, and if there are physical registers available,
265 /// it loads it into a register. If register pressure is high, and it is
266 /// possible, it tries to fold the load of the virtual register into the
267 /// instruction itself. It avoids doing this if register pressure is low to
268 /// improve the chance that subsequent instructions can use the reloaded
269 /// value. This method returns the modified instruction.
271 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
275 char RABigBlock::ID = 0;
278 /// getStackSpaceFor - This allocates space for the specified virtual register
279 /// to be held on the stack.
280 int RABigBlock::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
281 // Find the location Reg would belong...
282 int FrameIdx = getVirt2StackSlot(VirtReg);
285 return FrameIdx - 1; // Already has space allocated?
287 // Allocate a new stack object for this spill location...
288 FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
291 // Assign the slot...
292 getVirt2StackSlot(VirtReg) = FrameIdx + 1;
297 /// removePhysReg - This method marks the specified physical register as no
298 /// longer being in use.
300 void RABigBlock::removePhysReg(unsigned PhysReg) {
301 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
305 /// spillVirtReg - This method spills the value specified by PhysReg into the
306 /// virtual register slot specified by VirtReg. It then updates the RA data
307 /// structures to indicate the fact that PhysReg is now available.
309 void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
310 MachineBasicBlock::iterator I,
311 unsigned VirtReg, unsigned PhysReg) {
312 assert(VirtReg && "Spilling a physical register is illegal!"
313 " Must not have appropriate kill for the register or use exists beyond"
314 " the intended one.");
315 DOUT << " Spilling register " << RegInfo->getName(PhysReg)
316 << " containing %reg" << VirtReg;
318 const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
320 if (!isVirtRegModified(VirtReg))
321 DOUT << " which has not been modified, so no store necessary!";
323 // Otherwise, there is a virtual register corresponding to this physical
324 // register. We only need to spill it into its stack slot if it has been
326 if (isVirtRegModified(VirtReg)) {
327 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
328 int FrameIndex = getStackSpaceFor(VirtReg, RC);
329 DOUT << " to stack slot #" << FrameIndex;
330 TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
331 ++NumStores; // Update statistics
334 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
337 removePhysReg(PhysReg);
341 /// spillPhysReg - This method spills the specified physical register into the
342 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
343 /// then the request is ignored if the physical register does not contain a
344 /// virtual register.
346 void RABigBlock::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
347 unsigned PhysReg, bool OnlyVirtRegs) {
348 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
349 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
350 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
351 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
353 // If the selected register aliases any other registers, we must make
354 // sure that one of the aliases isn't alive.
355 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
356 *AliasSet; ++AliasSet)
357 if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
358 PhysRegsUsed[*AliasSet] != -2) // If allocatable.
359 if (PhysRegsUsed[*AliasSet])
360 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
365 /// assignVirtToPhysReg - This method updates local state so that we know
366 /// that PhysReg is the proper container for VirtReg now. The physical
367 /// register must not be used for anything else when this is called.
369 void RABigBlock::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
370 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
371 // Update information to note the fact that this register was just used, and
373 PhysRegsUsed[PhysReg] = VirtReg;
374 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
378 /// isPhysRegAvailable - Return true if the specified physical register is free
379 /// and available for use. This also includes checking to see if aliased
380 /// registers are all free...
382 bool RABigBlock::isPhysRegAvailable(unsigned PhysReg) const {
383 if (PhysRegsUsed[PhysReg] != -1) return false;
385 // If the selected register aliases any other allocated registers, it is
387 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
388 *AliasSet; ++AliasSet)
389 if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use?
390 return false; // Can't use this reg then.
395 /// getFreeReg - Look to see if there is a free register available in the
396 /// specified register class. If not, return 0.
398 unsigned RABigBlock::getFreeReg(const TargetRegisterClass *RC) {
399 // Get iterators defining the range of registers that are valid to allocate in
400 // this class, which also specifies the preferred allocation order.
401 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
402 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
404 for (; RI != RE; ++RI)
405 if (isPhysRegAvailable(*RI)) { // Is reg unused?
406 assert(*RI != 0 && "Cannot use register!");
407 return *RI; // Found an unused register!
413 /// chooseReg - Pick a physical register to hold the specified
414 /// virtual register by choosing the one whose value will be read
415 /// furthest in the future.
417 unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I,
419 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
420 // First check to see if we have a free register of the requested type...
421 unsigned PhysReg = getFreeReg(RC);
423 // If we didn't find an unused register, find the one which will be
424 // read at the most distant point in time.
426 unsigned delay=0, longest_delay=0;
427 VRegTimes* ReadTimes;
429 unsigned curTime = MBBCurTime;
431 // for all physical regs in the RC,
432 for(TargetRegisterClass::iterator pReg = RC->begin();
433 pReg != RC->end(); ++pReg) {
434 // how long until they're read?
435 if(PhysRegsUsed[*pReg]>0) { // ignore non-allocatable regs
436 ReadTimes = VRegReadTable[PhysRegsUsed[*pReg]];
437 if(ReadTimes && !ReadTimes->empty()) {
438 unsigned& pt = VRegReadIdx[PhysRegsUsed[*pReg]];
439 while(pt < ReadTimes->size() && (*ReadTimes)[pt] < curTime) {
443 if(pt < ReadTimes->size())
444 delay = (*ReadTimes)[pt] - curTime;
446 delay = MBBLastInsnTime + 1 - curTime;
448 // This register is only defined, but never
449 // read in this MBB. Therefore the next read
450 // happens after the end of this MBB
451 delay = MBBLastInsnTime + 1 - curTime;
455 if(delay > longest_delay) {
456 longest_delay = delay;
462 if(PhysReg == 0) { // ok, now we're desperate. We couldn't choose
463 // a register to spill by looking through the
464 // read timetable, so now we just spill the
465 // first allocatable register we find.
467 // for all physical regs in the RC,
468 for(TargetRegisterClass::iterator pReg = RC->begin();
469 pReg != RC->end(); ++pReg) {
470 // if we find a register we can spill
471 if(PhysRegsUsed[*pReg]>=-1)
472 PhysReg = *pReg; // choose it to be spilled
476 assert(PhysReg && "couldn't choose a register to spill :( ");
477 // TODO: assert that RC->contains(PhysReg) / handle aliased registers?
479 // since we needed to look in the table we need to spill this register.
480 spillPhysReg(MBB, I, PhysReg);
483 // assign the vreg to our chosen physical register
484 assignVirtToPhysReg(VirtReg, PhysReg);
485 return PhysReg; // and return it
489 /// reloadVirtReg - This method transforms an instruction with a virtual
490 /// register use to one that references a physical register. It does this as
493 /// 1) If the register is already in a physical register, it uses it.
494 /// 2) Otherwise, if there is a free physical register, it uses that.
495 /// 3) Otherwise, it calls chooseReg() to get the physical register
496 /// holding the most distantly needed value, generating a spill in
499 /// This method returns the modified instruction.
500 MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
502 unsigned VirtReg = MI->getOperand(OpNum).getReg();
503 const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
505 // If the virtual register is already available in a physical register,
506 // just update the instruction and return.
507 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
508 MI->getOperand(OpNum).setReg(PR);
512 // Otherwise, if we have free physical registers available to hold the
514 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
515 unsigned PhysReg = getFreeReg(RC);
516 int FrameIndex = getStackSpaceFor(VirtReg, RC);
518 if (PhysReg) { // we have a free register, so use it.
519 assignVirtToPhysReg(VirtReg, PhysReg);
520 } else { // no free registers available.
521 // try to fold the spill into the instruction
522 SmallVector<unsigned, 2> Ops;
523 Ops.push_back(OpNum);
524 if(MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) {
526 FMI->copyKillDeadInfo(MI);
527 return MBB.insert(MBB.erase(MI), FMI);
530 // determine which of the physical registers we'll kill off, since we
532 PhysReg = chooseReg(MBB, MI, VirtReg);
535 // this virtual register is now unmodified (since we just reloaded it)
536 markVirtRegModified(VirtReg, false);
538 DOUT << " Reloading %reg" << VirtReg << " into "
539 << RegInfo->getName(PhysReg) << "\n";
541 // Add move instruction(s)
542 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
543 ++NumLoads; // Update statistics
545 MF->getRegInfo().setPhysRegUsed(PhysReg);
546 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
550 /// Fill out the vreg read timetable. Since ReadTime increases
551 /// monotonically, the individual readtime sets will be sorted
552 /// in ascending order.
553 void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) {
554 // loop over each instruction
555 MachineBasicBlock::iterator MII;
558 for(ReadTime=0, MII = MBB.begin(); MII != MBB.end(); ++ReadTime, ++MII) {
559 MachineInstr *MI = MII;
561 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
562 MachineOperand& MO = MI->getOperand(i);
563 // look for vreg reads..
564 if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
565 MRegisterInfo::isVirtualRegister(MO.getReg())) {
566 // ..and add them to the read table.
567 VRegTimes* &Times = VRegReadTable[MO.getReg()];
568 if(!VRegReadTable[MO.getReg()]) {
569 Times = new VRegTimes;
570 VRegReadIdx[MO.getReg()] = 0;
572 Times->push_back(ReadTime);
578 MBBLastInsnTime = ReadTime;
580 for(DenseMap<unsigned, VRegTimes*, VRegKeyInfo>::iterator Reads = VRegReadTable.begin();
581 Reads != VRegReadTable.end(); ++Reads) {
583 DOUT << "Reads[" << Reads->first << "]=" << Reads->second->size() << "\n";
588 /// isReadModWriteImplicitKill - True if this is an implicit kill for a
589 /// read/mod/write register, i.e. update partial register.
590 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
591 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
592 MachineOperand& MO = MI->getOperand(i);
593 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
594 MO.isDef() && !MO.isDead())
600 /// isReadModWriteImplicitDef - True if this is an implicit def for a
601 /// read/mod/write register, i.e. update partial register.
602 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
603 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
604 MachineOperand& MO = MI->getOperand(i);
605 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
606 !MO.isDef() && MO.isKill())
613 void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
614 // loop over each instruction
615 MachineBasicBlock::iterator MII = MBB.begin();
616 const TargetInstrInfo &TII = *TM->getInstrInfo();
618 DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
619 if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName());
621 // If this is the first basic block in the machine function, add live-in
622 // registers as active.
623 if (&MBB == &*MF->begin()) {
624 for (MachineRegisterInfo::livein_iterator
625 I = MF->getRegInfo().livein_begin(),
626 E = MF->getRegInfo().livein_end(); I != E; ++I) {
627 unsigned Reg = I->first;
628 MF->getRegInfo().setPhysRegUsed(Reg);
629 PhysRegsUsed[Reg] = 0; // It is free and reserved now
630 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
631 *AliasSet; ++AliasSet) {
632 if (PhysRegsUsed[*AliasSet] != -2) {
633 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
634 MF->getRegInfo().setPhysRegUsed(*AliasSet);
640 // Otherwise, sequentially allocate each instruction in the MBB.
642 while (MII != MBB.end()) {
643 MachineInstr *MI = MII++;
645 const TargetInstrDesc &TID = MI->getDesc();
646 DEBUG(DOUT << "\nTime=" << MBBCurTime << " Starting RegAlloc of: " << *MI;
647 DOUT << " Regs have values: ";
648 for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
649 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
650 DOUT << "[" << RegInfo->getName(i)
651 << ",%reg" << PhysRegsUsed[i] << "] ";
654 SmallVector<unsigned, 8> Kills;
655 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
656 MachineOperand& MO = MI->getOperand(i);
657 if (MO.isRegister() && MO.isKill()) {
658 if (!MO.isImplicit())
659 Kills.push_back(MO.getReg());
660 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
661 // These are extra physical register kills when a sub-register
662 // is defined (def of a sub-register is a read/mod/write of the
663 // larger registers). Ignore.
664 Kills.push_back(MO.getReg());
668 // Get the used operands into registers. This has the potential to spill
669 // incoming values if we are out of registers. Note that we completely
670 // ignore physical register uses here. We assume that if an explicit
671 // physical register is referenced by the instruction, that it is guaranteed
672 // to be live-in, or the input is badly hosed.
674 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
675 MachineOperand& MO = MI->getOperand(i);
676 // here we are looking for only used operands (never def&use)
677 if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
678 MRegisterInfo::isVirtualRegister(MO.getReg()))
679 MI = reloadVirtReg(MBB, MI, i);
682 // If this instruction is the last user of this register, kill the
683 // value, freeing the register being used, so it doesn't need to be
684 // spilled to memory.
686 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
687 unsigned VirtReg = Kills[i];
688 unsigned PhysReg = VirtReg;
689 if (MRegisterInfo::isVirtualRegister(VirtReg)) {
690 // If the virtual register was never materialized into a register, it
691 // might not be in the map, but it won't hurt to zero it out anyway.
692 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
693 PhysReg = PhysRegSlot;
695 } else if (PhysRegsUsed[PhysReg] == -2) {
696 // Unallocatable register dead, ignore.
699 assert(!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1 &&
700 "Silently clearing a virtual register?");
704 DOUT << " Last use of " << RegInfo->getName(PhysReg)
705 << "[%reg" << VirtReg <<"], removing it from live set\n";
706 removePhysReg(PhysReg);
707 for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg);
708 *AliasSet; ++AliasSet) {
709 if (PhysRegsUsed[*AliasSet] != -2) {
710 DOUT << " Last use of "
711 << RegInfo->getName(*AliasSet)
712 << "[%reg" << VirtReg <<"], removing it from live set\n";
713 removePhysReg(*AliasSet);
719 // Loop over all of the operands of the instruction, spilling registers that
720 // are defined, and marking explicit destinations in the PhysRegsUsed map.
721 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
722 MachineOperand& MO = MI->getOperand(i);
723 if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
724 MRegisterInfo::isPhysicalRegister(MO.getReg())) {
725 unsigned Reg = MO.getReg();
726 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
727 // These are extra physical register defs when a sub-register
728 // is defined (def of a sub-register is a read/mod/write of the
729 // larger registers). Ignore.
730 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
732 MF->getRegInfo().setPhysRegUsed(Reg);
733 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
734 PhysRegsUsed[Reg] = 0; // It is free and reserved now
735 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
736 *AliasSet; ++AliasSet) {
737 if (PhysRegsUsed[*AliasSet] != -2) {
738 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
739 MF->getRegInfo().setPhysRegUsed(*AliasSet);
745 // Loop over the implicit defs, spilling them as well.
746 if (TID.getImplicitDefs()) {
747 for (const unsigned *ImplicitDefs = TID.getImplicitDefs();
748 *ImplicitDefs; ++ImplicitDefs) {
749 unsigned Reg = *ImplicitDefs;
750 if (PhysRegsUsed[Reg] != -2) {
751 spillPhysReg(MBB, MI, Reg, true);
752 PhysRegsUsed[Reg] = 0; // It is free and reserved now
754 MF->getRegInfo().setPhysRegUsed(Reg);
755 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
756 *AliasSet; ++AliasSet) {
757 if (PhysRegsUsed[*AliasSet] != -2) {
758 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
759 MF->getRegInfo().setPhysRegUsed(*AliasSet);
765 SmallVector<unsigned, 8> DeadDefs;
766 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
767 MachineOperand& MO = MI->getOperand(i);
768 if (MO.isRegister() && MO.isDead())
769 DeadDefs.push_back(MO.getReg());
772 // Okay, we have allocated all of the source operands and spilled any values
773 // that would be destroyed by defs of this instruction. Loop over the
774 // explicit defs and assign them to a register, spilling incoming values if
775 // we need to scavenge a register.
777 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
778 MachineOperand& MO = MI->getOperand(i);
779 if (MO.isRegister() && MO.isDef() && MO.getReg() &&
780 MRegisterInfo::isVirtualRegister(MO.getReg())) {
781 unsigned DestVirtReg = MO.getReg();
782 unsigned DestPhysReg;
784 // If DestVirtReg already has a value, use it.
785 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
786 DestPhysReg = chooseReg(MBB, MI, DestVirtReg);
787 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
788 markVirtRegModified(DestVirtReg);
789 MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
793 // If this instruction defines any registers that are immediately dead,
796 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
797 unsigned VirtReg = DeadDefs[i];
798 unsigned PhysReg = VirtReg;
799 if (MRegisterInfo::isVirtualRegister(VirtReg)) {
800 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
801 PhysReg = PhysRegSlot;
802 assert(PhysReg != 0);
804 } else if (PhysRegsUsed[PhysReg] == -2) {
805 // Unallocatable register dead, ignore.
810 DOUT << " Register " << RegInfo->getName(PhysReg)
811 << " [%reg" << VirtReg
812 << "] is never used, removing it frame live list\n";
813 removePhysReg(PhysReg);
814 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
815 *AliasSet; ++AliasSet) {
816 if (PhysRegsUsed[*AliasSet] != -2) {
817 DOUT << " Register " << RegInfo->getName(*AliasSet)
818 << " [%reg" << *AliasSet
819 << "] is never used, removing it frame live list\n";
820 removePhysReg(*AliasSet);
826 // Finally, if this is a noop copy instruction, zap it.
827 unsigned SrcReg, DstReg;
828 if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
832 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
834 // Spill all physical registers holding virtual registers now.
835 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
836 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
837 if (unsigned VirtReg = PhysRegsUsed[i])
838 spillVirtReg(MBB, MI, VirtReg, i);
843 /// runOnMachineFunction - Register allocate the whole function
845 bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) {
846 DOUT << "Machine Function " << "\n";
848 TM = &Fn.getTarget();
849 RegInfo = TM->getRegisterInfo();
851 PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
853 // At various places we want to efficiently check to see whether a register
854 // is allocatable. To handle this, we mark all unallocatable registers as
855 // being pinned down, permanently.
857 BitVector Allocable = RegInfo->getAllocatableSet(Fn);
858 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
860 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
863 // initialize the virtual->physical register map to have a 'null'
864 // mapping for all virtual registers
865 Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg());
866 StackSlotForVirtReg.grow(MF->getRegInfo().getLastVirtReg());
867 VirtRegModified.resize(MF->getRegInfo().getLastVirtReg() -
868 MRegisterInfo::FirstVirtualRegister + 1, 0);
870 // Loop over all of the basic blocks, eliminating virtual register references
871 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
872 MBB != MBBe; ++MBB) {
873 // fill out the read timetable
874 FillVRegReadTable(*MBB);
875 // use it to allocate the BB
876 AllocateBasicBlock(*MBB);
878 VRegReadTable.clear();
881 StackSlotForVirtReg.clear();
882 PhysRegsUsed.clear();
883 VirtRegModified.clear();
884 Virt2PhysRegMap.clear();
888 FunctionPass *llvm::createBigBlockRegisterAllocator() {
889 return new RABigBlock();