1 //===- RegAllocBigBlock.cpp - A register allocator for large basic blocks -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the RABigBlock class
12 //===----------------------------------------------------------------------===//
14 // This register allocator is derived from RegAllocLocal.cpp. Like it, this
15 // allocator works on one basic block at a time, oblivious to others.
16 // However, the algorithm used here is suited for long blocks of
17 // instructions - registers are spilled by greedily choosing those holding
18 // values that will not be needed for the longest amount of time. This works
19 // particularly well for blocks with 10 or more times as many instructions
20 // as machine registers, but can be used for general code.
22 //===----------------------------------------------------------------------===//
24 // TODO: - automagically invoke linearscan for (groups of) small BBs?
25 // - break ties when picking regs? (probably not worth it in a
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "regalloc"
31 #include "llvm/BasicBlock.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineInstr.h"
35 #include "llvm/CodeGen/SSARegMap.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/LiveVariables.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/Compiler.h"
44 #include "llvm/ADT/IndexedMap.h"
45 #include "llvm/ADT/DenseMap.h"
46 #include "llvm/ADT/SmallVector.h"
47 #include "llvm/ADT/SmallPtrSet.h"
48 #include "llvm/ADT/Statistic.h"
52 STATISTIC(NumStores, "Number of stores added");
53 STATISTIC(NumLoads , "Number of loads added");
54 STATISTIC(NumFolded, "Number of loads/stores folded into instructions");
57 static RegisterRegAlloc
58 bigBlockRegAlloc("bigblock", " Big-block register allocator",
59 createBigBlockRegisterAllocator);
61 /// VRegKeyInfo - Defines magic values required to use VirtRegs as DenseMap
64 static inline unsigned getEmptyKey() { return -1U; }
65 static inline unsigned getTombstoneKey() { return -2U; }
66 static unsigned getHashValue(const unsigned &Key) { return Key; }
70 /// This register allocator is derived from RegAllocLocal.cpp. Like it, this
71 /// allocator works on one basic block at a time, oblivious to others.
72 /// However, the algorithm used here is suited for long blocks of
73 /// instructions - registers are spilled by greedily choosing those holding
74 /// values that will not be needed for the longest amount of time. This works
75 /// particularly well for blocks with 10 or more times as many instructions
76 /// as machine registers, but can be used for general code.
78 /// TODO: - automagically invoke linearscan for (groups of) small BBs?
79 /// - break ties when picking regs? (probably not worth it in a
82 class VISIBILITY_HIDDEN RABigBlock : public MachineFunctionPass {
85 RABigBlock() : MachineFunctionPass((intptr_t)&ID) {}
87 /// TM - For getting at TargetMachine info
89 const TargetMachine *TM;
91 /// MF - Our generic MachineFunction pointer
95 /// RegInfo - For dealing with machine register info (aliases, folds
97 const MRegisterInfo *RegInfo;
99 /// LV - Our generic LiveVariables pointer
103 typedef SmallVector<unsigned, 2> VRegTimes;
105 /// VRegReadTable - maps VRegs in a BB to the set of times they are read
107 DenseMap<unsigned, VRegTimes*, VRegKeyInfo> VRegReadTable;
109 /// VRegReadIdx - keeps track of the "current time" in terms of
110 /// positions in VRegReadTable
111 DenseMap<unsigned, unsigned , VRegKeyInfo> VRegReadIdx;
113 /// StackSlotForVirtReg - Maps virtual regs to the frame index where these
114 /// values are spilled.
115 IndexedMap<unsigned, VirtReg2IndexFunctor> StackSlotForVirtReg;
117 /// Virt2PhysRegMap - This map contains entries for each virtual register
118 /// that is currently available in a physical register.
119 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
121 /// PhysRegsUsed - This array is effectively a map, containing entries for
122 /// each physical register that currently has a value (ie, it is in
123 /// Virt2PhysRegMap). The value mapped to is the virtual register
124 /// corresponding to the physical register (the inverse of the
125 /// Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
126 /// because it is used by a future instruction, and to -2 if it is not
127 /// allocatable. If the entry for a physical register is -1, then the
128 /// physical register is "not in the map".
130 std::vector<int> PhysRegsUsed;
132 /// VirtRegModified - This bitset contains information about which virtual
133 /// registers need to be spilled back to memory when their registers are
134 /// scavenged. If a virtual register has simply been rematerialized, there
135 /// is no reason to spill it to memory when we need the register back.
137 std::vector<int> VirtRegModified;
139 /// MBBLastInsnTime - the number of the the last instruction in MBB
143 /// MBBCurTime - the number of the the instruction being currently processed
147 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
148 return Virt2PhysRegMap[VirtReg];
151 unsigned &getVirt2StackSlot(unsigned VirtReg) {
152 return StackSlotForVirtReg[VirtReg];
155 /// markVirtRegModified - Lets us flip bits in the VirtRegModified bitset
157 void markVirtRegModified(unsigned Reg, bool Val = true) {
158 assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
159 Reg -= MRegisterInfo::FirstVirtualRegister;
160 if (VirtRegModified.size() <= Reg)
161 VirtRegModified.resize(Reg+1);
162 VirtRegModified[Reg] = Val;
165 /// isVirtRegModified - Lets us query the VirtRegModified bitset
167 bool isVirtRegModified(unsigned Reg) const {
168 assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
169 assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
170 && "Illegal virtual register!");
171 return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister];
175 /// getPassName - returns the BigBlock allocator's name
177 virtual const char *getPassName() const {
178 return "BigBlock Register Allocator";
181 /// getAnalaysisUsage - declares the required analyses
183 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
184 AU.addRequired<LiveVariables>();
185 AU.addRequiredID(PHIEliminationID);
186 AU.addRequiredID(TwoAddressInstructionPassID);
187 MachineFunctionPass::getAnalysisUsage(AU);
191 /// runOnMachineFunction - Register allocate the whole function
193 bool runOnMachineFunction(MachineFunction &Fn);
195 /// AllocateBasicBlock - Register allocate the specified basic block.
197 void AllocateBasicBlock(MachineBasicBlock &MBB);
199 /// FillVRegReadTable - Fill out the table of vreg read times given a BB
201 void FillVRegReadTable(MachineBasicBlock &MBB);
203 /// areRegsEqual - This method returns true if the specified registers are
204 /// related to each other. To do this, it checks to see if they are equal
205 /// or if the first register is in the alias set of the second register.
207 bool areRegsEqual(unsigned R1, unsigned R2) const {
208 if (R1 == R2) return true;
209 for (const unsigned *AliasSet = RegInfo->getAliasSet(R2);
210 *AliasSet; ++AliasSet) {
211 if (*AliasSet == R1) return true;
216 /// getStackSpaceFor - This returns the frame index of the specified virtual
217 /// register on the stack, allocating space if necessary.
218 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
220 /// removePhysReg - This method marks the specified physical register as no
221 /// longer being in use.
223 void removePhysReg(unsigned PhysReg);
225 /// spillVirtReg - This method spills the value specified by PhysReg into
226 /// the virtual register slot specified by VirtReg. It then updates the RA
227 /// data structures to indicate the fact that PhysReg is now available.
229 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
230 unsigned VirtReg, unsigned PhysReg);
232 /// spillPhysReg - This method spills the specified physical register into
233 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
234 /// true, then the request is ignored if the physical register does not
235 /// contain a virtual register.
237 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
238 unsigned PhysReg, bool OnlyVirtRegs = false);
240 /// assignVirtToPhysReg - This method updates local state so that we know
241 /// that PhysReg is the proper container for VirtReg now. The physical
242 /// register must not be used for anything else when this is called.
244 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
246 /// isPhysRegAvailable - Return true if the specified physical register is
247 /// free and available for use. This also includes checking to see if
248 /// aliased registers are all free...
250 bool isPhysRegAvailable(unsigned PhysReg) const;
252 /// getFreeReg - Look to see if there is a free register available in the
253 /// specified register class. If not, return 0.
255 unsigned getFreeReg(const TargetRegisterClass *RC);
257 /// chooseReg - Pick a physical register to hold the specified
258 /// virtual register by choosing the one which will be read furthest
261 unsigned chooseReg(MachineBasicBlock &MBB, MachineInstr *MI,
264 /// reloadVirtReg - This method transforms the specified specified virtual
265 /// register use to refer to a physical register. This method may do this
266 /// in one of several ways: if the register is available in a physical
267 /// register already, it uses that physical register. If the value is not
268 /// in a physical register, and if there are physical registers available,
269 /// it loads it into a register. If register pressure is high, and it is
270 /// possible, it tries to fold the load of the virtual register into the
271 /// instruction itself. It avoids doing this if register pressure is low to
272 /// improve the chance that subsequent instructions can use the reloaded
273 /// value. This method returns the modified instruction.
275 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
279 char RABigBlock::ID = 0;
282 /// getStackSpaceFor - This allocates space for the specified virtual register
283 /// to be held on the stack.
284 int RABigBlock::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
285 // Find the location Reg would belong...
286 int FrameIdx = getVirt2StackSlot(VirtReg);
289 return FrameIdx - 1; // Already has space allocated?
291 // Allocate a new stack object for this spill location...
292 FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
295 // Assign the slot...
296 getVirt2StackSlot(VirtReg) = FrameIdx + 1;
301 /// removePhysReg - This method marks the specified physical register as no
302 /// longer being in use.
304 void RABigBlock::removePhysReg(unsigned PhysReg) {
305 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
309 /// spillVirtReg - This method spills the value specified by PhysReg into the
310 /// virtual register slot specified by VirtReg. It then updates the RA data
311 /// structures to indicate the fact that PhysReg is now available.
313 void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
314 MachineBasicBlock::iterator I,
315 unsigned VirtReg, unsigned PhysReg) {
316 assert(VirtReg && "Spilling a physical register is illegal!"
317 " Must not have appropriate kill for the register or use exists beyond"
318 " the intended one.");
319 DOUT << " Spilling register " << RegInfo->getName(PhysReg)
320 << " containing %reg" << VirtReg;
321 if (!isVirtRegModified(VirtReg))
322 DOUT << " which has not been modified, so no store necessary!";
324 // Otherwise, there is a virtual register corresponding to this physical
325 // register. We only need to spill it into its stack slot if it has been
327 if (isVirtRegModified(VirtReg)) {
328 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
329 int FrameIndex = getStackSpaceFor(VirtReg, RC);
330 DOUT << " to stack slot #" << FrameIndex;
331 RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
332 ++NumStores; // Update statistics
335 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
338 removePhysReg(PhysReg);
342 /// spillPhysReg - This method spills the specified physical register into the
343 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
344 /// then the request is ignored if the physical register does not contain a
345 /// virtual register.
347 void RABigBlock::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
348 unsigned PhysReg, bool OnlyVirtRegs) {
349 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
350 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
351 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
352 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
354 // If the selected register aliases any other registers, we must make
355 // sure that one of the aliases isn't alive.
356 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
357 *AliasSet; ++AliasSet)
358 if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
359 PhysRegsUsed[*AliasSet] != -2) // If allocatable.
360 if (PhysRegsUsed[*AliasSet])
361 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
366 /// assignVirtToPhysReg - This method updates local state so that we know
367 /// that PhysReg is the proper container for VirtReg now. The physical
368 /// register must not be used for anything else when this is called.
370 void RABigBlock::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
371 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
372 // Update information to note the fact that this register was just used, and
374 PhysRegsUsed[PhysReg] = VirtReg;
375 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
379 /// isPhysRegAvailable - Return true if the specified physical register is free
380 /// and available for use. This also includes checking to see if aliased
381 /// registers are all free...
383 bool RABigBlock::isPhysRegAvailable(unsigned PhysReg) const {
384 if (PhysRegsUsed[PhysReg] != -1) return false;
386 // If the selected register aliases any other allocated registers, it is
388 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
389 *AliasSet; ++AliasSet)
390 if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use?
391 return false; // Can't use this reg then.
396 /// getFreeReg - Look to see if there is a free register available in the
397 /// specified register class. If not, return 0.
399 unsigned RABigBlock::getFreeReg(const TargetRegisterClass *RC) {
400 // Get iterators defining the range of registers that are valid to allocate in
401 // this class, which also specifies the preferred allocation order.
402 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
403 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
405 for (; RI != RE; ++RI)
406 if (isPhysRegAvailable(*RI)) { // Is reg unused?
407 assert(*RI != 0 && "Cannot use register!");
408 return *RI; // Found an unused register!
414 /// chooseReg - Pick a physical register to hold the specified
415 /// virtual register by choosing the one whose value will be read
416 /// furthest in the future.
418 unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I,
420 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
421 // First check to see if we have a free register of the requested type...
422 unsigned PhysReg = getFreeReg(RC);
424 // If we didn't find an unused register, find the one which will be
425 // read at the most distant point in time.
427 unsigned delay=0, longest_delay=0;
428 VRegTimes* ReadTimes;
430 unsigned curTime = MBBCurTime;
432 // for all physical regs in the RC,
433 for(TargetRegisterClass::iterator pReg = RC->begin();
434 pReg != RC->end(); ++pReg) {
435 // how long until they're read?
436 if(PhysRegsUsed[*pReg]>0) { // ignore non-allocatable regs
437 ReadTimes = VRegReadTable[PhysRegsUsed[*pReg]];
438 if(ReadTimes && !ReadTimes->empty()) {
439 unsigned& pt = VRegReadIdx[PhysRegsUsed[*pReg]];
440 while(pt < ReadTimes->size() && (*ReadTimes)[pt] < curTime) {
444 if(pt < ReadTimes->size())
445 delay = (*ReadTimes)[pt] - curTime;
447 delay = MBBLastInsnTime + 1 - curTime;
449 // This register is only defined, but never
450 // read in this MBB. Therefore the next read
451 // happens after the end of this MBB
452 delay = MBBLastInsnTime + 1 - curTime;
456 if(delay > longest_delay) {
457 longest_delay = delay;
463 if(PhysReg == 0) { // ok, now we're desperate. We couldn't choose
464 // a register to spill by looking through the
465 // read timetable, so now we just spill the
466 // first allocatable register we find.
468 // for all physical regs in the RC,
469 for(TargetRegisterClass::iterator pReg = RC->begin();
470 pReg != RC->end(); ++pReg) {
471 // if we find a register we can spill
472 if(PhysRegsUsed[*pReg]>=-1)
473 PhysReg = *pReg; // choose it to be spilled
477 assert(PhysReg && "couldn't choose a register to spill :( ");
478 // TODO: assert that RC->contains(PhysReg) / handle aliased registers?
480 // since we needed to look in the table we need to spill this register.
481 spillPhysReg(MBB, I, PhysReg);
484 // assign the vreg to our chosen physical register
485 assignVirtToPhysReg(VirtReg, PhysReg);
486 return PhysReg; // and return it
490 /// reloadVirtReg - This method transforms an instruction with a virtual
491 /// register use to one that references a physical register. It does this as
494 /// 1) If the register is already in a physical register, it uses it.
495 /// 2) Otherwise, if there is a free physical register, it uses that.
496 /// 3) Otherwise, it calls chooseReg() to get the physical register
497 /// holding the most distantly needed value, generating a spill in
500 /// This method returns the modified instruction.
501 MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
503 unsigned VirtReg = MI->getOperand(OpNum).getReg();
505 // If the virtual register is already available in a physical register,
506 // just update the instruction and return.
507 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
508 MI->getOperand(OpNum).setReg(PR);
512 // Otherwise, if we have free physical registers available to hold the
514 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
515 unsigned PhysReg = getFreeReg(RC);
516 int FrameIndex = getStackSpaceFor(VirtReg, RC);
518 if (PhysReg) { // we have a free register, so use it.
519 assignVirtToPhysReg(VirtReg, PhysReg);
520 } else { // no free registers available.
521 // try to fold the spill into the instruction
522 if(MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, OpNum, FrameIndex)) {
524 // Since we changed the address of MI, make sure to update live variables
525 // to know that the new instruction has the properties of the old one.
526 LV->instructionChanged(MI, FMI);
527 return MBB.insert(MBB.erase(MI), FMI);
530 // determine which of the physical registers we'll kill off, since we
532 PhysReg = chooseReg(MBB, MI, VirtReg);
535 // this virtual register is now unmodified (since we just reloaded it)
536 markVirtRegModified(VirtReg, false);
538 DOUT << " Reloading %reg" << VirtReg << " into "
539 << RegInfo->getName(PhysReg) << "\n";
541 // Add move instruction(s)
542 RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
543 ++NumLoads; // Update statistics
545 MF->setPhysRegUsed(PhysReg);
546 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
550 /// Fill out the vreg read timetable. Since ReadTime increases
551 /// monotonically, the individual readtime sets will be sorted
552 /// in ascending order.
553 void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) {
554 // loop over each instruction
555 MachineBasicBlock::iterator MII;
558 for(ReadTime=0, MII = MBB.begin(); MII != MBB.end(); ++ReadTime, ++MII) {
559 MachineInstr *MI = MII;
561 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
562 MachineOperand& MO = MI->getOperand(i);
563 // look for vreg reads..
564 if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
565 MRegisterInfo::isVirtualRegister(MO.getReg())) {
566 // ..and add them to the read table.
567 VRegTimes* &Times = VRegReadTable[MO.getReg()];
568 if(!VRegReadTable[MO.getReg()]) {
569 Times = new VRegTimes;
570 VRegReadIdx[MO.getReg()] = 0;
572 Times->push_back(ReadTime);
578 MBBLastInsnTime = ReadTime;
580 for(DenseMap<unsigned, VRegTimes*, VRegKeyInfo>::iterator Reads = VRegReadTable.begin();
581 Reads != VRegReadTable.end(); ++Reads) {
583 DOUT << "Reads[" << Reads->first << "]=" << Reads->second->size() << "\n";
588 /// isReadModWriteImplicitKill - True if this is an implicit kill for a
589 /// read/mod/write register, i.e. update partial register.
590 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
591 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
592 MachineOperand& MO = MI->getOperand(i);
593 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
594 MO.isDef() && !MO.isDead())
600 /// isReadModWriteImplicitDef - True if this is an implicit def for a
601 /// read/mod/write register, i.e. update partial register.
602 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
603 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
604 MachineOperand& MO = MI->getOperand(i);
605 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
606 !MO.isDef() && MO.isKill())
613 void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
614 // loop over each instruction
615 MachineBasicBlock::iterator MII = MBB.begin();
616 const TargetInstrInfo &TII = *TM->getInstrInfo();
618 DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
619 if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName());
621 // If this is the first basic block in the machine function, add live-in
622 // registers as active.
623 if (&MBB == &*MF->begin()) {
624 for (MachineFunction::livein_iterator I = MF->livein_begin(),
625 E = MF->livein_end(); I != E; ++I) {
626 unsigned Reg = I->first;
627 MF->setPhysRegUsed(Reg);
628 PhysRegsUsed[Reg] = 0; // It is free and reserved now
629 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
630 *AliasSet; ++AliasSet) {
631 if (PhysRegsUsed[*AliasSet] != -2) {
632 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
633 MF->setPhysRegUsed(*AliasSet);
639 // Otherwise, sequentially allocate each instruction in the MBB.
641 while (MII != MBB.end()) {
642 MachineInstr *MI = MII++;
644 const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
645 DEBUG(DOUT << "\nTime=" << MBBCurTime << " Starting RegAlloc of: " << *MI;
646 DOUT << " Regs have values: ";
647 for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
648 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
649 DOUT << "[" << RegInfo->getName(i)
650 << ",%reg" << PhysRegsUsed[i] << "] ";
653 SmallVector<unsigned, 8> Kills;
654 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
655 MachineOperand& MO = MI->getOperand(i);
656 if (MO.isRegister() && MO.isKill()) {
657 if (!MO.isImplicit())
658 Kills.push_back(MO.getReg());
659 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
660 // These are extra physical register kills when a sub-register
661 // is defined (def of a sub-register is a read/mod/write of the
662 // larger registers). Ignore.
663 Kills.push_back(MO.getReg());
667 // Get the used operands into registers. This has the potential to spill
668 // incoming values if we are out of registers. Note that we completely
669 // ignore physical register uses here. We assume that if an explicit
670 // physical register is referenced by the instruction, that it is guaranteed
671 // to be live-in, or the input is badly hosed.
673 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
674 MachineOperand& MO = MI->getOperand(i);
675 // here we are looking for only used operands (never def&use)
676 if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
677 MRegisterInfo::isVirtualRegister(MO.getReg()))
678 MI = reloadVirtReg(MBB, MI, i);
681 // If this instruction is the last user of this register, kill the
682 // value, freeing the register being used, so it doesn't need to be
683 // spilled to memory.
685 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
686 unsigned VirtReg = Kills[i];
687 unsigned PhysReg = VirtReg;
688 if (MRegisterInfo::isVirtualRegister(VirtReg)) {
689 // If the virtual register was never materialized into a register, it
690 // might not be in the map, but it won't hurt to zero it out anyway.
691 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
692 PhysReg = PhysRegSlot;
694 } else if (PhysRegsUsed[PhysReg] == -2) {
695 // Unallocatable register dead, ignore.
698 assert(!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1 &&
699 "Silently clearing a virtual register?");
703 DOUT << " Last use of " << RegInfo->getName(PhysReg)
704 << "[%reg" << VirtReg <<"], removing it from live set\n";
705 removePhysReg(PhysReg);
706 for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg);
707 *AliasSet; ++AliasSet) {
708 if (PhysRegsUsed[*AliasSet] != -2) {
709 DOUT << " Last use of "
710 << RegInfo->getName(*AliasSet)
711 << "[%reg" << VirtReg <<"], removing it from live set\n";
712 removePhysReg(*AliasSet);
718 // Loop over all of the operands of the instruction, spilling registers that
719 // are defined, and marking explicit destinations in the PhysRegsUsed map.
720 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
721 MachineOperand& MO = MI->getOperand(i);
722 if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
723 MRegisterInfo::isPhysicalRegister(MO.getReg())) {
724 unsigned Reg = MO.getReg();
725 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
726 // These are extra physical register defs when a sub-register
727 // is defined (def of a sub-register is a read/mod/write of the
728 // larger registers). Ignore.
729 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
731 MF->setPhysRegUsed(Reg);
732 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
733 PhysRegsUsed[Reg] = 0; // It is free and reserved now
734 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
735 *AliasSet; ++AliasSet) {
736 if (PhysRegsUsed[*AliasSet] != -2) {
737 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
738 MF->setPhysRegUsed(*AliasSet);
744 // Loop over the implicit defs, spilling them as well.
745 if (TID.ImplicitDefs) {
746 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
747 *ImplicitDefs; ++ImplicitDefs) {
748 unsigned Reg = *ImplicitDefs;
749 if (PhysRegsUsed[Reg] != -2) {
750 spillPhysReg(MBB, MI, Reg, true);
751 PhysRegsUsed[Reg] = 0; // It is free and reserved now
753 MF->setPhysRegUsed(Reg);
754 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
755 *AliasSet; ++AliasSet) {
756 if (PhysRegsUsed[*AliasSet] != -2) {
757 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
758 MF->setPhysRegUsed(*AliasSet);
764 SmallVector<unsigned, 8> DeadDefs;
765 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
766 MachineOperand& MO = MI->getOperand(i);
767 if (MO.isRegister() && MO.isDead())
768 DeadDefs.push_back(MO.getReg());
771 // Okay, we have allocated all of the source operands and spilled any values
772 // that would be destroyed by defs of this instruction. Loop over the
773 // explicit defs and assign them to a register, spilling incoming values if
774 // we need to scavenge a register.
776 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
777 MachineOperand& MO = MI->getOperand(i);
778 if (MO.isRegister() && MO.isDef() && MO.getReg() &&
779 MRegisterInfo::isVirtualRegister(MO.getReg())) {
780 unsigned DestVirtReg = MO.getReg();
781 unsigned DestPhysReg;
783 // If DestVirtReg already has a value, use it.
784 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
785 DestPhysReg = chooseReg(MBB, MI, DestVirtReg);
786 MF->setPhysRegUsed(DestPhysReg);
787 markVirtRegModified(DestVirtReg);
788 MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
792 // If this instruction defines any registers that are immediately dead,
795 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
796 unsigned VirtReg = DeadDefs[i];
797 unsigned PhysReg = VirtReg;
798 if (MRegisterInfo::isVirtualRegister(VirtReg)) {
799 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
800 PhysReg = PhysRegSlot;
801 assert(PhysReg != 0);
803 } else if (PhysRegsUsed[PhysReg] == -2) {
804 // Unallocatable register dead, ignore.
809 DOUT << " Register " << RegInfo->getName(PhysReg)
810 << " [%reg" << VirtReg
811 << "] is never used, removing it frame live list\n";
812 removePhysReg(PhysReg);
813 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
814 *AliasSet; ++AliasSet) {
815 if (PhysRegsUsed[*AliasSet] != -2) {
816 DOUT << " Register " << RegInfo->getName(*AliasSet)
817 << " [%reg" << *AliasSet
818 << "] is never used, removing it frame live list\n";
819 removePhysReg(*AliasSet);
825 // Finally, if this is a noop copy instruction, zap it.
826 unsigned SrcReg, DstReg;
827 if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) {
828 LV->removeVirtualRegistersKilled(MI);
829 LV->removeVirtualRegistersDead(MI);
834 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
836 // Spill all physical registers holding virtual registers now.
837 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
838 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
839 if (unsigned VirtReg = PhysRegsUsed[i])
840 spillVirtReg(MBB, MI, VirtReg, i);
845 /// runOnMachineFunction - Register allocate the whole function
847 bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) {
848 DOUT << "Machine Function " << "\n";
850 TM = &Fn.getTarget();
851 RegInfo = TM->getRegisterInfo();
852 LV = &getAnalysis<LiveVariables>();
854 PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
856 // At various places we want to efficiently check to see whether a register
857 // is allocatable. To handle this, we mark all unallocatable registers as
858 // being pinned down, permanently.
860 BitVector Allocable = RegInfo->getAllocatableSet(Fn);
861 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
863 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
866 // initialize the virtual->physical register map to have a 'null'
867 // mapping for all virtual registers
868 Virt2PhysRegMap.grow(MF->getSSARegMap()->getLastVirtReg());
869 StackSlotForVirtReg.grow(MF->getSSARegMap()->getLastVirtReg());
870 VirtRegModified.resize(MF->getSSARegMap()->getLastVirtReg() - MRegisterInfo::FirstVirtualRegister + 1,0);
872 // Loop over all of the basic blocks, eliminating virtual register references
873 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
874 MBB != MBBe; ++MBB) {
875 // fill out the read timetable
876 FillVRegReadTable(*MBB);
877 // use it to allocate the BB
878 AllocateBasicBlock(*MBB);
880 VRegReadTable.clear();
883 StackSlotForVirtReg.clear();
884 PhysRegsUsed.clear();
885 VirtRegModified.clear();
886 Virt2PhysRegMap.clear();
890 FunctionPass *llvm::createBigBlockRegisterAllocator() {
891 return new RABigBlock();