1 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/IndexedMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
38 static cl::opt<bool> VerifyFastRegalloc("verify-fast-regalloc", cl::Hidden,
39 cl::desc("Verify machine code before fast regalloc"));
41 STATISTIC(NumStores, "Number of stores added");
42 STATISTIC(NumLoads , "Number of loads added");
43 STATISTIC(NumCopies, "Number of copies coalesced");
45 static RegisterRegAlloc
46 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
49 class RAFast : public MachineFunctionPass {
52 RAFast() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1),
53 isBulkSpilling(false) {}
55 const TargetMachine *TM;
57 MachineRegisterInfo *MRI;
58 const TargetRegisterInfo *TRI;
59 const TargetInstrInfo *TII;
61 // Basic block currently being allocated.
62 MachineBasicBlock *MBB;
64 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
65 // values are spilled.
66 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
68 // Everything we know about a live virtual register.
70 MachineInstr *LastUse; // Last instr to use reg.
71 unsigned PhysReg; // Currently held here.
72 unsigned short LastOpNum; // OpNum on LastUse.
73 bool Dirty; // Register needs spill.
75 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
79 typedef DenseMap<unsigned, LiveReg> LiveRegMap;
80 typedef LiveRegMap::value_type LiveRegEntry;
82 // LiveVirtRegs - This map contains entries for each virtual register
83 // that is currently available in a physical register.
84 LiveRegMap LiveVirtRegs;
86 // RegState - Track the state of a physical register.
88 // A disabled register is not available for allocation, but an alias may
89 // be in use. A register can only be moved out of the disabled state if
90 // all aliases are disabled.
93 // A free register is not currently in use and can be allocated
94 // immediately without checking aliases.
97 // A reserved register has been assigned expolicitly (e.g., setting up a
98 // call parameter), and it remains reserved until it is used.
101 // A register state may also be a virtual register number, indication that
102 // the physical register is currently allocated to a virtual register. In
103 // that case, LiveVirtRegs contains the inverse mapping.
106 // PhysRegState - One of the RegState enums, or a virtreg.
107 std::vector<unsigned> PhysRegState;
109 // UsedInInstr - BitVector of physregs that are used in the current
110 // instruction, and so cannot be allocated.
111 BitVector UsedInInstr;
113 // Allocatable - vector of allocatable physical registers.
114 BitVector Allocatable;
116 // isBulkSpilling - This flag is set when LiveRegMap will be cleared
117 // completely after spilling all live registers. LiveRegMap entries should
122 virtual const char *getPassName() const {
123 return "Fast Register Allocator";
126 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
127 AU.setPreservesCFG();
128 AU.addRequiredID(PHIEliminationID);
129 AU.addRequiredID(TwoAddressInstructionPassID);
130 MachineFunctionPass::getAnalysisUsage(AU);
134 bool runOnMachineFunction(MachineFunction &Fn);
135 void AllocateBasicBlock();
136 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
137 bool isLastUseOfLocalReg(MachineOperand&);
139 void addKillFlag(const LiveReg&);
140 void killVirtReg(LiveRegMap::iterator);
141 void killVirtReg(unsigned VirtReg);
142 void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
143 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
145 void usePhysReg(MachineOperand&);
146 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
147 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
148 void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
149 unsigned defineVirtReg(MachineInstr *MI, unsigned OpNum,
150 unsigned VirtReg, unsigned Hint);
151 unsigned reloadVirtReg(MachineInstr *MI, unsigned OpNum,
152 unsigned VirtReg, unsigned Hint);
153 void spillAll(MachineInstr *MI);
154 void setPhysReg(MachineOperand &MO, unsigned PhysReg);
159 /// getStackSpaceFor - This allocates space for the specified virtual register
160 /// to be held on the stack.
161 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
162 // Find the location Reg would belong...
163 int SS = StackSlotForVirtReg[VirtReg];
165 return SS; // Already has space allocated?
167 // Allocate a new stack object for this spill location...
168 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
172 StackSlotForVirtReg[VirtReg] = FrameIdx;
176 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
177 /// its virtual register, and it is guaranteed to be a block-local register.
179 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
180 // Check for non-debug uses or defs following MO.
181 // This is the most likely way to fail - fast path it.
182 MachineOperand *Next = &MO;
183 while ((Next = Next->getNextOperandForReg()))
184 if (!Next->isDebug())
187 // If the register has ever been spilled or reloaded, we conservatively assume
188 // it is a global register used in multiple blocks.
189 if (StackSlotForVirtReg[MO.getReg()] != -1)
192 // Check that the use/def chain has exactly one operand - MO.
193 return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO;
196 /// addKillFlag - Set kill flags on last use of a virtual register.
197 void RAFast::addKillFlag(const LiveReg &LR) {
198 if (!LR.LastUse) return;
199 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
202 else if (!LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum))
206 /// killVirtReg - Mark virtreg as no longer available.
207 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
208 addKillFlag(LRI->second);
209 const LiveReg &LR = LRI->second;
210 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
211 PhysRegState[LR.PhysReg] = regFree;
212 // Erase from LiveVirtRegs unless we're spilling in bulk.
214 LiveVirtRegs.erase(LRI);
217 /// killVirtReg - Mark virtreg as no longer available.
218 void RAFast::killVirtReg(unsigned VirtReg) {
219 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
220 "killVirtReg needs a virtual register");
221 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
222 if (LRI != LiveVirtRegs.end())
226 /// spillVirtReg - This method spills the value specified by VirtReg into the
227 /// corresponding stack slot if needed. If isKill is set, the register is also
229 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
230 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
231 "Spilling a physical register is illegal!");
232 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
233 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
234 spillVirtReg(MI, LRI);
237 /// spillVirtReg - Do the actual work of spilling.
238 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
239 LiveRegMap::iterator LRI) {
240 LiveReg &LR = LRI->second;
241 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
244 // If this physreg is used by the instruction, we want to kill it on the
245 // instruction, not on the spill.
246 bool SpillKill = LR.LastUse != MI;
248 DEBUG(dbgs() << "Spilling %reg" << LRI->first
249 << " in " << TRI->getName(LR.PhysReg));
250 const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
251 int FI = getStackSpaceFor(LRI->first, RC);
252 DEBUG(dbgs() << " to stack slot #" << FI << "\n");
253 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
254 ++NumStores; // Update statistics
257 LR.LastUse = 0; // Don't kill register again
262 /// spillAll - Spill all dirty virtregs without killing them.
263 void RAFast::spillAll(MachineInstr *MI) {
264 isBulkSpilling = true;
265 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
266 e = LiveVirtRegs.end(); i != e; ++i)
268 LiveVirtRegs.clear();
269 isBulkSpilling = false;
272 /// usePhysReg - Handle the direct use of a physical register.
273 /// Check that the register is not used by a virtreg.
274 /// Kill the physreg, marking it free.
275 /// This may add implicit kills to MO->getParent() and invalidate MO.
276 void RAFast::usePhysReg(MachineOperand &MO) {
277 unsigned PhysReg = MO.getReg();
278 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
279 "Bad usePhysReg operand");
281 switch (PhysRegState[PhysReg]) {
285 PhysRegState[PhysReg] = regFree;
288 UsedInInstr.set(PhysReg);
292 // The physreg was allocated to a virtual register. That means to value we
293 // wanted has been clobbered.
294 llvm_unreachable("Instruction uses an allocated register");
297 // Maybe a superregister is reserved?
298 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
299 unsigned Alias = *AS; ++AS) {
300 switch (PhysRegState[Alias]) {
304 assert(TRI->isSuperRegister(PhysReg, Alias) &&
305 "Instruction is not using a subregister of a reserved register");
306 // Leave the superregister in the working set.
307 PhysRegState[Alias] = regFree;
308 UsedInInstr.set(Alias);
309 MO.getParent()->addRegisterKilled(Alias, TRI, true);
312 if (TRI->isSuperRegister(PhysReg, Alias)) {
313 // Leave the superregister in the working set.
314 UsedInInstr.set(Alias);
315 MO.getParent()->addRegisterKilled(Alias, TRI, true);
318 // Some other alias was in the working set - clear it.
319 PhysRegState[Alias] = regDisabled;
322 llvm_unreachable("Instruction uses an alias of an allocated register");
326 // All aliases are disabled, bring register into working set.
327 PhysRegState[PhysReg] = regFree;
328 UsedInInstr.set(PhysReg);
332 /// definePhysReg - Mark PhysReg as reserved or free after spilling any
333 /// virtregs. This is very similar to defineVirtReg except the physreg is
334 /// reserved instead of allocated.
335 void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
337 UsedInInstr.set(PhysReg);
338 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
342 spillVirtReg(MI, VirtReg);
346 PhysRegState[PhysReg] = NewState;
350 // This is a disabled register, disable all aliases.
351 PhysRegState[PhysReg] = NewState;
352 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
353 unsigned Alias = *AS; ++AS) {
354 UsedInInstr.set(Alias);
355 switch (unsigned VirtReg = PhysRegState[Alias]) {
359 spillVirtReg(MI, VirtReg);
363 PhysRegState[Alias] = regDisabled;
364 if (TRI->isSuperRegister(PhysReg, Alias))
372 /// assignVirtToPhysReg - This method updates local state so that we know
373 /// that PhysReg is the proper container for VirtReg now. The physical
374 /// register must not be used for anything else when this is called.
376 void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) {
377 DEBUG(dbgs() << "Assigning %reg" << LRE.first << " to "
378 << TRI->getName(PhysReg) << "\n");
379 PhysRegState[PhysReg] = LRE.first;
380 assert(!LRE.second.PhysReg && "Already assigned a physreg");
381 LRE.second.PhysReg = PhysReg;
384 /// allocVirtReg - Allocate a physical register for VirtReg.
385 void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
386 const unsigned SpillCost = 100;
387 const unsigned VirtReg = LRE.first;
389 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
390 "Can only allocate virtual registers");
392 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
393 TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
394 TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
396 // Ignore invalid hints.
397 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
398 !RC->contains(Hint) || UsedInInstr.test(Hint) ||
399 !Allocatable.test(Hint)))
402 // If there is no hint, peek at the first use of this register.
403 if (!Hint && !MRI->use_nodbg_empty(VirtReg)) {
404 MachineInstr &MI = *MRI->use_nodbg_begin(VirtReg);
405 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
406 // Copy to physreg -> use physreg as hint.
407 if (TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
408 SrcReg == VirtReg && TargetRegisterInfo::isPhysicalRegister(DstReg) &&
409 RC->contains(DstReg) && !UsedInInstr.test(DstReg) &&
410 Allocatable.test(DstReg)) {
412 DEBUG(dbgs() << "%reg" << VirtReg << " gets hint from " << MI);
416 // Take hint when possible.
418 assert(RC->contains(Hint) && !UsedInInstr.test(Hint) &&
419 Allocatable.test(Hint) && "Invalid hint should have been cleared");
420 switch(PhysRegState[Hint]) {
425 spillVirtReg(MI, PhysRegState[Hint]);
428 return assignVirtToPhysReg(LRE, Hint);
432 // First try to find a completely free register.
433 unsigned BestCost = 0, BestReg = 0;
434 bool hasDisabled = false;
435 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
436 unsigned PhysReg = *I;
437 switch(PhysRegState[PhysReg]) {
443 if (!UsedInInstr.test(PhysReg))
444 return assignVirtToPhysReg(LRE, PhysReg);
447 // Grab the first spillable register we meet.
448 if (!BestReg && !UsedInInstr.test(PhysReg))
449 BestReg = PhysReg, BestCost = SpillCost;
454 DEBUG(dbgs() << "Allocating %reg" << VirtReg << " from " << RC->getName()
455 << " candidate=" << TRI->getName(BestReg) << "\n");
457 // Try to extend the working set for RC if there were any disabled registers.
458 if (hasDisabled && (!BestReg || BestCost >= SpillCost)) {
459 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
460 unsigned PhysReg = *I;
461 if (PhysRegState[PhysReg] != regDisabled || UsedInInstr.test(PhysReg))
464 // Calculate the cost of bringing PhysReg into the working set.
466 bool Impossible = false;
467 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
468 unsigned Alias = *AS; ++AS) {
469 if (UsedInInstr.test(Alias)) {
473 switch (PhysRegState[Alias]) {
487 if (Impossible) continue;
488 DEBUG(dbgs() << "- candidate " << TRI->getName(PhysReg)
489 << " cost=" << Cost << "\n");
490 if (!BestReg || Cost < BestCost) {
493 if (Cost < SpillCost) break;
499 // BestCost is 0 when all aliases are already disabled.
501 if (PhysRegState[BestReg] != regDisabled)
502 spillVirtReg(MI, PhysRegState[BestReg]);
504 // Make sure all aliases are disabled.
505 for (const unsigned *AS = TRI->getAliasSet(BestReg);
506 unsigned Alias = *AS; ++AS) {
507 switch (PhysRegState[Alias]) {
511 PhysRegState[Alias] = regDisabled;
514 spillVirtReg(MI, PhysRegState[Alias]);
515 PhysRegState[Alias] = regDisabled;
521 return assignVirtToPhysReg(LRE, BestReg);
524 // Nothing we can do.
526 raw_string_ostream Msg(msg);
527 Msg << "Ran out of registers during register allocation!";
528 if (MI->isInlineAsm()) {
529 Msg << "\nPlease check your inline asm statement for "
530 << "invalid constraints:\n";
533 report_fatal_error(Msg.str());
536 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
537 unsigned RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
538 unsigned VirtReg, unsigned Hint) {
539 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
540 "Not a virtual register");
541 LiveRegMap::iterator LRI;
543 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
544 LiveReg &LR = LRI->second;
546 allocVirtReg(MI, *LRI, Hint);
548 addKillFlag(LR); // Kill before redefine.
549 assert(LR.PhysReg && "Register not assigned");
551 LR.LastOpNum = OpNum;
553 UsedInInstr.set(LR.PhysReg);
557 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
558 unsigned RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
559 unsigned VirtReg, unsigned Hint) {
560 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
561 "Not a virtual register");
562 LiveRegMap::iterator LRI;
564 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
565 LiveReg &LR = LRI->second;
567 allocVirtReg(MI, *LRI, Hint);
568 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
569 int FrameIndex = getStackSpaceFor(VirtReg, RC);
570 DEBUG(dbgs() << "Reloading %reg" << VirtReg << " into "
571 << TRI->getName(LR.PhysReg) << "\n");
572 TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI);
574 } else if (LR.Dirty) {
575 MachineOperand &MO = MI->getOperand(OpNum);
576 if (isLastUseOfLocalReg(MO)) {
577 DEBUG(dbgs() << "Killing last use: " << MO << "\n");
579 } else if (MO.isKill()) {
580 DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
584 assert(LR.PhysReg && "Register not assigned");
586 LR.LastOpNum = OpNum;
587 UsedInInstr.set(LR.PhysReg);
591 // setPhysReg - Change MO the refer the PhysReg, considering subregs.
592 void RAFast::setPhysReg(MachineOperand &MO, unsigned PhysReg) {
593 if (unsigned Idx = MO.getSubReg()) {
594 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, Idx) : 0);
600 void RAFast::AllocateBasicBlock() {
601 DEBUG(dbgs() << "\nAllocating " << *MBB);
603 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
604 assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
606 MachineBasicBlock::iterator MII = MBB->begin();
608 // Add live-in registers as live.
609 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
610 E = MBB->livein_end(); I != E; ++I)
611 definePhysReg(MII, *I, regReserved);
613 SmallVector<unsigned, 8> VirtKills, PhysDefs;
614 SmallVector<MachineInstr*, 32> Coalesced;
616 // Otherwise, sequentially allocate each instruction in the MBB.
617 while (MII != MBB->end()) {
618 MachineInstr *MI = MII++;
619 const TargetInstrDesc &TID = MI->getDesc();
621 dbgs() << "\n>> " << *MI << "Regs:";
622 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
623 if (PhysRegState[Reg] == regDisabled) continue;
624 dbgs() << " " << TRI->getName(Reg);
625 switch(PhysRegState[Reg]) {
632 dbgs() << "=%reg" << PhysRegState[Reg];
633 if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
635 assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
641 // Check that LiveVirtRegs is the inverse.
642 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
643 e = LiveVirtRegs.end(); i != e; ++i) {
644 assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
646 assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
648 assert(PhysRegState[i->second.PhysReg] == i->first &&
653 // Debug values are not allowed to change codegen in any way.
654 if (MI->isDebugValue()) {
655 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
656 MachineOperand &MO = MI->getOperand(i);
657 if (!MO.isReg()) continue;
658 unsigned Reg = MO.getReg();
659 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
660 LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
661 if (LRI != LiveVirtRegs.end())
662 setPhysReg(MO, LRI->second.PhysReg);
664 MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
670 // If this is a copy, we may be able to coalesce.
671 unsigned CopySrc, CopyDst, CopySrcSub, CopyDstSub;
672 if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
673 CopySrc = CopyDst = 0;
675 // Track registers used by instruction.
680 // Mark physreg uses and early clobbers as used.
681 // Find the end of the virtreg operands
682 unsigned VirtOpEnd = 0;
683 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
684 MachineOperand &MO = MI->getOperand(i);
685 if (!MO.isReg()) continue;
686 unsigned Reg = MO.getReg();
688 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
692 if (!Allocatable.test(Reg)) continue;
695 } else if (MO.isEarlyClobber()) {
696 definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
697 PhysDefs.push_back(Reg);
702 // Allocate virtreg uses and early clobbers.
704 for (unsigned i = 0; i != VirtOpEnd; ++i) {
705 MachineOperand &MO = MI->getOperand(i);
706 if (!MO.isReg()) continue;
707 unsigned Reg = MO.getReg();
708 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
710 unsigned PhysReg = reloadVirtReg(MI, i, Reg, CopyDst);
711 CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
712 setPhysReg(MO, PhysReg);
714 VirtKills.push_back(Reg);
715 } else if (MO.isEarlyClobber()) {
716 unsigned PhysReg = defineVirtReg(MI, i, Reg, 0);
717 setPhysReg(MO, PhysReg);
718 PhysDefs.push_back(PhysReg);
722 // Process virtreg kills
723 for (unsigned i = 0, e = VirtKills.size(); i != e; ++i)
724 killVirtReg(VirtKills[i]);
727 MRI->addPhysRegsUsed(UsedInInstr);
729 // Track registers defined by instruction - early clobbers at this point.
731 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
732 unsigned PhysReg = PhysDefs[i];
733 UsedInInstr.set(PhysReg);
734 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
735 unsigned Alias = *AS; ++AS)
736 UsedInInstr.set(Alias);
740 // Allocate defs and collect dead defs.
741 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
742 MachineOperand &MO = MI->getOperand(i);
743 if (!MO.isReg() || !MO.isDef() || !MO.getReg()) continue;
744 unsigned Reg = MO.getReg();
746 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
747 if (!Allocatable.test(Reg)) continue;
748 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
749 regFree : regReserved);
752 unsigned PhysReg = defineVirtReg(MI, i, Reg, CopySrc);
754 VirtKills.push_back(Reg);
755 CopyDst = 0; // cancel coalescing;
757 CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
758 setPhysReg(MO, PhysReg);
761 // Spill all dirty virtregs before a call, in case of an exception.
763 DEBUG(dbgs() << " Spilling remaining registers before call.\n");
767 // Process virtreg deads.
768 for (unsigned i = 0, e = VirtKills.size(); i != e; ++i)
769 killVirtReg(VirtKills[i]);
772 MRI->addPhysRegsUsed(UsedInInstr);
774 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
775 DEBUG(dbgs() << "-- coalescing: " << *MI);
776 Coalesced.push_back(MI);
778 DEBUG(dbgs() << "<< " << *MI);
782 // Spill all physical registers holding virtual registers now.
783 DEBUG(dbgs() << "Spilling live registers at end of block.\n");
784 spillAll(MBB->getFirstTerminator());
786 // Erase all the coalesced copies. We are delaying it until now because
787 // LiveVirtRegs might refer to the instrs.
788 for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
789 MBB->erase(Coalesced[i]);
790 NumCopies += Coalesced.size();
795 /// runOnMachineFunction - Register allocate the whole function
797 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
798 DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
799 << "********** Function: "
800 << ((Value*)Fn.getFunction())->getName() << '\n');
801 if (VerifyFastRegalloc)
802 Fn.verify(this, true);
804 MRI = &MF->getRegInfo();
805 TM = &Fn.getTarget();
806 TRI = TM->getRegisterInfo();
807 TII = TM->getInstrInfo();
809 UsedInInstr.resize(TRI->getNumRegs());
810 Allocatable = TRI->getAllocatableSet(*MF);
812 // initialize the virtual->physical register map to have a 'null'
813 // mapping for all virtual registers
814 unsigned LastVirtReg = MRI->getLastVirtReg();
815 StackSlotForVirtReg.grow(LastVirtReg);
817 // Loop over all of the basic blocks, eliminating virtual register references
818 for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
819 MBBi != MBBe; ++MBBi) {
821 AllocateBasicBlock();
824 // Make sure the set of used physregs is closed under subreg operations.
825 MRI->closePhysRegsUsed(*TRI);
827 StackSlotForVirtReg.clear();
831 FunctionPass *llvm::createFastRegisterAllocator() {