1 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/IndexedMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(NumStores, "Number of stores added");
39 STATISTIC(NumLoads , "Number of loads added");
41 static RegisterRegAlloc
42 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
45 class RAFast : public MachineFunctionPass {
48 RAFast() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {}
50 const TargetMachine *TM;
52 MachineRegisterInfo *MRI;
53 const TargetRegisterInfo *TRI;
54 const TargetInstrInfo *TII;
56 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
57 // values are spilled.
58 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
60 // Everything we know about a live virtual register.
62 MachineInstr *LastUse; // Last instr to use reg.
63 unsigned PhysReg; // Currently held here.
64 unsigned short LastOpNum; // OpNum on LastUse.
65 bool Dirty; // Register needs spill.
67 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
69 assert(p && "Don't create LiveRegs without a PhysReg");
73 typedef DenseMap<unsigned, LiveReg> LiveRegMap;
75 // LiveVirtRegs - This map contains entries for each virtual register
76 // that is currently available in a physical register.
77 LiveRegMap LiveVirtRegs;
79 // RegState - Track the state of a physical register.
81 // A disabled register is not available for allocation, but an alias may
82 // be in use. A register can only be moved out of the disabled state if
83 // all aliases are disabled.
86 // A free register is not currently in use and can be allocated
87 // immediately without checking aliases.
90 // A reserved register has been assigned expolicitly (e.g., setting up a
91 // call parameter), and it remains reserved until it is used.
94 // A register state may also be a virtual register number, indication that
95 // the physical register is currently allocated to a virtual register. In
96 // that case, LiveVirtRegs contains the inverse mapping.
99 // PhysRegState - One of the RegState enums, or a virtreg.
100 std::vector<unsigned> PhysRegState;
102 // UsedInInstr - BitVector of physregs that are used in the current
103 // instruction, and so cannot be allocated.
104 BitVector UsedInInstr;
106 // ReservedRegs - vector of reserved physical registers.
107 BitVector ReservedRegs;
110 virtual const char *getPassName() const {
111 return "Fast Register Allocator";
114 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
115 AU.setPreservesCFG();
116 AU.addRequiredID(PHIEliminationID);
117 AU.addRequiredID(TwoAddressInstructionPassID);
118 MachineFunctionPass::getAnalysisUsage(AU);
122 bool runOnMachineFunction(MachineFunction &Fn);
123 void AllocateBasicBlock(MachineBasicBlock &MBB);
124 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
125 void addKillFlag(LiveRegMap::iterator i);
126 void killVirtReg(LiveRegMap::iterator i);
127 void killVirtReg(unsigned VirtReg);
128 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
129 unsigned VirtReg, bool isKill);
130 void killPhysReg(unsigned PhysReg);
131 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
132 unsigned PhysReg, bool isKill);
133 LiveRegMap::iterator assignVirtToPhysReg(unsigned VirtReg,
135 LiveRegMap::iterator allocVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
136 unsigned VirtReg, unsigned Hint);
137 unsigned defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
138 unsigned OpNum, unsigned VirtReg, unsigned Hint);
139 unsigned reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
140 unsigned OpNum, unsigned VirtReg, unsigned Hint);
141 void reservePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
143 void spillAll(MachineBasicBlock &MBB, MachineInstr *MI);
144 void setPhysReg(MachineOperand &MO, unsigned PhysReg);
149 /// getStackSpaceFor - This allocates space for the specified virtual register
150 /// to be held on the stack.
151 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
152 // Find the location Reg would belong...
153 int SS = StackSlotForVirtReg[VirtReg];
155 return SS; // Already has space allocated?
157 // Allocate a new stack object for this spill location...
158 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
162 StackSlotForVirtReg[VirtReg] = FrameIdx;
166 /// addKillFlag - Set kill flags on last use of a virtual register.
167 void RAFast::addKillFlag(LiveRegMap::iterator lri) {
168 assert(lri != LiveVirtRegs.end() && "Killing unmapped virtual register");
169 const LiveReg &LR = lri->second;
171 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
174 else if (!LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum))
179 /// killVirtReg - Mark virtreg as no longer available.
180 void RAFast::killVirtReg(LiveRegMap::iterator lri) {
182 const LiveReg &LR = lri->second;
183 assert(PhysRegState[LR.PhysReg] == lri->first && "Broken RegState mapping");
184 PhysRegState[LR.PhysReg] = regFree;
185 LiveVirtRegs.erase(lri);
188 /// killVirtReg - Mark virtreg as no longer available.
189 void RAFast::killVirtReg(unsigned VirtReg) {
190 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
191 "killVirtReg needs a virtual register");
192 LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
193 if (lri != LiveVirtRegs.end())
197 /// spillVirtReg - This method spills the value specified by VirtReg into the
198 /// corresponding stack slot if needed. If isKill is set, the register is also
200 void RAFast::spillVirtReg(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator MI,
202 unsigned VirtReg, bool isKill) {
203 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
204 "Spilling a physical register is illegal!");
205 LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
206 assert(lri != LiveVirtRegs.end() && "Spilling unmapped virtual register");
207 LiveReg &LR = lri->second;
208 assert(PhysRegState[LR.PhysReg] == VirtReg && "Broken RegState mapping");
210 // If this physreg is used by the instruction, we want to kill it on the
211 // instruction, not on the spill.
212 bool spillKill = isKill && LR.LastUse != MI;
216 DEBUG(dbgs() << "Spilling register " << TRI->getName(LR.PhysReg)
217 << " containing %reg" << VirtReg);
218 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
219 int FrameIndex = getStackSpaceFor(VirtReg, RC);
220 DEBUG(dbgs() << " to stack slot #" << FrameIndex << "\n");
221 TII->storeRegToStackSlot(MBB, MI, LR.PhysReg, spillKill,
222 FrameIndex, RC, TRI);
223 ++NumStores; // Update statistics
226 LR.LastUse = 0; // Don't kill register again
228 MachineInstr *Spill = llvm::prior(MI);
230 LR.LastOpNum = Spill->findRegisterUseOperandIdx(LR.PhysReg);
238 /// spillAll - Spill all dirty virtregs without killing them.
239 void RAFast::spillAll(MachineBasicBlock &MBB, MachineInstr *MI) {
240 SmallVector<unsigned, 16> Dirty;
241 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
242 e = LiveVirtRegs.end(); i != e; ++i)
244 Dirty.push_back(i->first);
245 for (unsigned i = 0, e = Dirty.size(); i != e; ++i)
246 spillVirtReg(MBB, MI, Dirty[i], false);
249 /// killPhysReg - Kill any virtual register aliased by PhysReg.
250 void RAFast::killPhysReg(unsigned PhysReg) {
251 // Fast path for the normal case.
252 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
258 PhysRegState[PhysReg] = regFree;
261 killVirtReg(VirtReg);
265 // This is a disabled register, we have to check aliases.
266 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
267 unsigned Alias = *AS; ++AS) {
268 switch (unsigned VirtReg = PhysRegState[Alias]) {
273 PhysRegState[Alias] = regFree;
276 killVirtReg(VirtReg);
282 /// spillPhysReg - Spill any dirty virtual registers that aliases PhysReg. If
283 /// isKill is set, they are also killed.
284 void RAFast::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
285 unsigned PhysReg, bool isKill) {
286 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
293 PhysRegState[PhysReg] = regFree;
296 spillVirtReg(MBB, MI, VirtReg, isKill);
300 // This is a disabled register, we have to check aliases.
301 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
302 unsigned Alias = *AS; ++AS) {
303 switch (unsigned VirtReg = PhysRegState[Alias]) {
309 PhysRegState[Alias] = regFree;
312 spillVirtReg(MBB, MI, VirtReg, isKill);
318 /// assignVirtToPhysReg - This method updates local state so that we know
319 /// that PhysReg is the proper container for VirtReg now. The physical
320 /// register must not be used for anything else when this is called.
322 RAFast::LiveRegMap::iterator
323 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
324 DEBUG(dbgs() << "Assigning %reg" << VirtReg << " to "
325 << TRI->getName(PhysReg) << "\n");
326 PhysRegState[PhysReg] = VirtReg;
327 return LiveVirtRegs.insert(std::make_pair(VirtReg, PhysReg)).first;
330 /// allocVirtReg - Allocate a physical register for VirtReg.
331 RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
335 const unsigned spillCost = 100;
336 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
337 "Can only allocate virtual registers");
339 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
340 TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
341 TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
343 // Ignore invalid hints.
344 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
345 !RC->contains(Hint) || UsedInInstr.test(Hint)))
348 // If there is no hint, peek at the first use of this register.
349 if (!Hint && !MRI->use_nodbg_empty(VirtReg)) {
350 MachineInstr &MI = *MRI->use_nodbg_begin(VirtReg);
351 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
352 // Copy to physreg -> use physreg as hint.
353 if (TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
354 SrcReg == VirtReg && TargetRegisterInfo::isPhysicalRegister(DstReg) &&
355 RC->contains(DstReg) && !UsedInInstr.test(DstReg)) {
357 DEBUG(dbgs() << "%reg" << VirtReg << " gets hint from " << MI);
361 // Take hint when possible.
363 assert(RC->contains(Hint) && !UsedInInstr.test(Hint) &&
364 "Invalid hint should have been cleared");
365 switch(PhysRegState[Hint]) {
370 spillVirtReg(MBB, MI, PhysRegState[Hint], true);
373 return assignVirtToPhysReg(VirtReg, Hint);
377 // First try to find a completely free register.
378 unsigned BestCost = 0, BestReg = 0;
379 bool hasDisabled = false;
380 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
381 unsigned PhysReg = *I;
382 switch(PhysRegState[PhysReg]) {
388 if (!UsedInInstr.test(PhysReg))
389 return assignVirtToPhysReg(VirtReg, PhysReg);
392 // Grab the first spillable register we meet.
393 if (!BestReg && !UsedInInstr.test(PhysReg))
394 BestReg = PhysReg, BestCost = spillCost;
399 DEBUG(dbgs() << "Allocating %reg" << VirtReg << " from " << RC->getName()
400 << " candidate=" << TRI->getName(BestReg) << "\n");
402 // Try to extend the working set for RC if there were any disabled registers.
403 if (hasDisabled && (!BestReg || BestCost >= spillCost)) {
404 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
405 unsigned PhysReg = *I;
406 if (PhysRegState[PhysReg] != regDisabled || UsedInInstr.test(PhysReg))
409 // Calculate the cost of bringing PhysReg into the working set.
411 bool Impossible = false;
412 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
413 unsigned Alias = *AS; ++AS) {
414 if (UsedInInstr.test(Alias)) {
418 switch (PhysRegState[Alias]) {
432 if (Impossible) continue;
433 DEBUG(dbgs() << "- candidate " << TRI->getName(PhysReg)
434 << " cost=" << Cost << "\n");
435 if (!BestReg || Cost < BestCost) {
438 if (Cost < spillCost) break;
444 // BestCost is 0 when all aliases are already disabled.
446 if (PhysRegState[BestReg] != regDisabled)
447 spillVirtReg(MBB, MI, PhysRegState[BestReg], true);
449 // Make sure all aliases are disabled.
450 for (const unsigned *AS = TRI->getAliasSet(BestReg);
451 unsigned Alias = *AS; ++AS) {
452 switch (PhysRegState[Alias]) {
456 PhysRegState[Alias] = regDisabled;
459 spillVirtReg(MBB, MI, PhysRegState[Alias], true);
460 PhysRegState[Alias] = regDisabled;
466 return assignVirtToPhysReg(VirtReg, BestReg);
469 // Nothing we can do.
471 raw_string_ostream Msg(msg);
472 Msg << "Ran out of registers during register allocation!";
473 if (MI->isInlineAsm()) {
474 Msg << "\nPlease check your inline asm statement for "
475 << "invalid constraints:\n";
478 report_fatal_error(Msg.str());
479 return LiveVirtRegs.end();
482 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
483 unsigned RAFast::defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
484 unsigned OpNum, unsigned VirtReg, unsigned Hint) {
485 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
486 "Not a virtual register");
487 LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
488 if (lri == LiveVirtRegs.end())
489 lri = allocVirtReg(MBB, MI, VirtReg, Hint);
491 addKillFlag(lri); // Kill before redefine.
492 LiveReg &LR = lri->second;
494 LR.LastOpNum = OpNum;
496 UsedInInstr.set(LR.PhysReg);
500 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
501 unsigned RAFast::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
502 unsigned OpNum, unsigned VirtReg, unsigned Hint) {
503 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
504 "Not a virtual register");
505 LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
506 if (lri == LiveVirtRegs.end()) {
507 lri = allocVirtReg(MBB, MI, VirtReg, Hint);
508 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
509 int FrameIndex = getStackSpaceFor(VirtReg, RC);
510 DEBUG(dbgs() << "Reloading %reg" << VirtReg << " into "
511 << TRI->getName(lri->second.PhysReg) << "\n");
512 TII->loadRegFromStackSlot(MBB, MI, lri->second.PhysReg, FrameIndex, RC,
516 LiveReg &LR = lri->second;
518 LR.LastOpNum = OpNum;
519 UsedInInstr.set(LR.PhysReg);
523 /// reservePhysReg - Mark PhysReg as reserved. This is very similar to
524 /// defineVirtReg except the physreg is reserved instead of allocated.
525 void RAFast::reservePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
527 UsedInInstr.set(PhysReg);
528 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
532 PhysRegState[PhysReg] = regReserved;
537 spillVirtReg(MBB, MI, VirtReg, true);
538 PhysRegState[PhysReg] = regReserved;
542 // This is a disabled register, disable all aliases.
543 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
544 unsigned Alias = *AS; ++AS) {
545 UsedInInstr.set(Alias);
546 switch (unsigned VirtReg = PhysRegState[Alias]) {
551 // is a super register already reserved?
552 if (TRI->isSuperRegister(PhysReg, Alias))
556 spillVirtReg(MBB, MI, VirtReg, true);
559 PhysRegState[Alias] = regDisabled;
561 PhysRegState[PhysReg] = regReserved;
564 // setPhysReg - Change MO the refer the PhysReg, considering subregs.
565 void RAFast::setPhysReg(MachineOperand &MO, unsigned PhysReg) {
566 if (unsigned Idx = MO.getSubReg()) {
567 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, Idx) : 0);
573 void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
574 DEBUG(dbgs() << "\nAllocating " << MBB);
576 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
577 assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
579 MachineBasicBlock::iterator MII = MBB.begin();
581 // Add live-in registers as live.
582 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
583 E = MBB.livein_end(); I != E; ++I)
584 reservePhysReg(MBB, MII, *I);
586 SmallVector<unsigned, 8> VirtKills, PhysKills, PhysDefs;
588 // Otherwise, sequentially allocate each instruction in the MBB.
589 while (MII != MBB.end()) {
590 MachineInstr *MI = MII++;
591 const TargetInstrDesc &TID = MI->getDesc();
593 dbgs() << "\n>> " << *MI << "Regs:";
594 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
595 if (PhysRegState[Reg] == regDisabled) continue;
596 dbgs() << " " << TRI->getName(Reg);
597 switch(PhysRegState[Reg]) {
604 dbgs() << "=%reg" << PhysRegState[Reg];
605 if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
607 assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
613 // Check that LiveVirtRegs is the inverse.
614 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
615 e = LiveVirtRegs.end(); i != e; ++i) {
616 assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
618 assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
620 assert(PhysRegState[i->second.PhysReg] == i->first &&
625 // Debug values are not allowed to change codegen in any way.
626 if (MI->isDebugValue()) {
627 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
628 MachineOperand &MO = MI->getOperand(i);
629 if (!MO.isReg()) continue;
630 unsigned Reg = MO.getReg();
631 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
632 LiveRegMap::iterator lri = LiveVirtRegs.find(Reg);
633 if (lri != LiveVirtRegs.end())
634 setPhysReg(MO, lri->second.PhysReg);
636 MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
642 // If this is a copy, we may be able to coalesce.
643 unsigned CopySrc, CopyDst, CopySrcSub, CopyDstSub;
644 if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
645 CopySrc = CopyDst = 0;
647 // Track registers used by instruction.
652 // Mark physreg uses and early clobbers as used.
653 // Collect PhysKills.
654 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
655 MachineOperand &MO = MI->getOperand(i);
656 if (!MO.isReg()) continue;
658 // FIXME: For now, don't trust kill flags
659 if (MO.isUse()) MO.setIsKill(false);
661 unsigned Reg = MO.getReg();
662 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg) ||
663 ReservedRegs.test(Reg)) continue;
666 // We are using a physreg directly. It had better not be clobbered by a
668 assert(PhysRegState[Reg] <= regReserved && "Using clobbered physreg");
669 if (PhysRegState[Reg] == regDisabled)
670 for (const unsigned *AS = TRI->getAliasSet(Reg);
671 unsigned Alias = *AS; ++AS)
672 assert(PhysRegState[Alias] <= regReserved &&
673 "Physreg alias was clobbered");
675 PhysKills.push_back(Reg); // Any clean physreg use is a kill.
676 UsedInInstr.set(Reg);
677 } else if (MO.isEarlyClobber()) {
678 spillPhysReg(MBB, MI, Reg, true);
679 UsedInInstr.set(Reg);
680 PhysDefs.push_back(Reg);
685 // Allocate virtreg uses and early clobbers.
687 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
688 MachineOperand &MO = MI->getOperand(i);
689 if (!MO.isReg()) continue;
690 unsigned Reg = MO.getReg();
691 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
693 unsigned PhysReg = reloadVirtReg(MBB, MI, i, Reg, CopyDst);
696 setPhysReg(MO, PhysReg);
698 VirtKills.push_back(Reg);
699 } else if (MO.isEarlyClobber()) {
700 unsigned PhysReg = defineVirtReg(MBB, MI, i, Reg, 0);
701 setPhysReg(MO, PhysReg);
702 PhysDefs.push_back(PhysReg);
706 // Process virtreg kills
707 for (unsigned i = 0, e = VirtKills.size(); i != e; ++i)
708 killVirtReg(VirtKills[i]);
711 // Process physreg kills
712 for (unsigned i = 0, e = PhysKills.size(); i != e; ++i)
713 killPhysReg(PhysKills[i]);
716 MRI->addPhysRegsUsed(UsedInInstr);
718 // Track registers defined by instruction - early clobbers at this point.
720 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
721 unsigned PhysReg = PhysDefs[i];
722 UsedInInstr.set(PhysReg);
723 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
724 unsigned Alias = *AS; ++AS)
725 UsedInInstr.set(Alias);
729 // Allocate defs and collect dead defs.
730 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
731 MachineOperand &MO = MI->getOperand(i);
732 if (!MO.isReg() || !MO.isDef() || !MO.getReg()) continue;
733 unsigned Reg = MO.getReg();
735 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
736 if (ReservedRegs.test(Reg)) continue;
738 spillPhysReg(MBB, MI, Reg, true);
740 reservePhysReg(MBB, MI, Reg);
742 PhysKills.push_back(Reg);
746 VirtKills.push_back(Reg);
747 unsigned PhysReg = defineVirtReg(MBB, MI, i, Reg, CopySrc);
750 setPhysReg(MO, PhysReg);
753 // Spill all dirty virtregs before a call, in case of an exception.
755 DEBUG(dbgs() << " Spilling remaining registers before call.\n");
759 // Process virtreg deads.
760 for (unsigned i = 0, e = VirtKills.size(); i != e; ++i)
761 killVirtReg(VirtKills[i]);
764 // Process physreg deads.
765 for (unsigned i = 0, e = PhysKills.size(); i != e; ++i)
766 killPhysReg(PhysKills[i]);
769 MRI->addPhysRegsUsed(UsedInInstr);
771 DEBUG(dbgs() << "<< " << *MI);
774 // Spill all physical registers holding virtual registers now.
775 DEBUG(dbgs() << "Killing live registers at end of block.\n");
776 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
777 while (!LiveVirtRegs.empty())
778 spillVirtReg(MBB, MI, LiveVirtRegs.begin()->first, true);
783 /// runOnMachineFunction - Register allocate the whole function
785 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
786 DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
787 << "********** Function: "
788 << ((Value*)Fn.getFunction())->getName() << '\n');
790 MRI = &MF->getRegInfo();
791 TM = &Fn.getTarget();
792 TRI = TM->getRegisterInfo();
793 TII = TM->getInstrInfo();
795 UsedInInstr.resize(TRI->getNumRegs());
796 ReservedRegs = TRI->getReservedRegs(*MF);
798 // initialize the virtual->physical register map to have a 'null'
799 // mapping for all virtual registers
800 unsigned LastVirtReg = MRI->getLastVirtReg();
801 StackSlotForVirtReg.grow(LastVirtReg);
803 // Loop over all of the basic blocks, eliminating virtual register references
804 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
806 AllocateBasicBlock(*MBB);
808 // Make sure the set of used physregs is closed under subreg operations.
809 MRI->closePhysRegsUsed(*TRI);
811 StackSlotForVirtReg.clear();
815 FunctionPass *llvm::createFastRegisterAllocator() {