1 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "RegisterClassInfo.h"
17 #include "llvm/BasicBlock.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/CodeGen/RegAllocRegistry.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/IndexedMap.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
40 STATISTIC(NumStores, "Number of stores added");
41 STATISTIC(NumLoads , "Number of loads added");
42 STATISTIC(NumCopies, "Number of copies coalesced");
44 static RegisterRegAlloc
45 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
48 class RAFast : public MachineFunctionPass {
51 RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
52 isBulkSpilling(false) {
53 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
54 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
57 const TargetMachine *TM;
59 MachineRegisterInfo *MRI;
60 const TargetRegisterInfo *TRI;
61 const TargetInstrInfo *TII;
62 RegisterClassInfo RegClassInfo;
64 // Basic block currently being allocated.
65 MachineBasicBlock *MBB;
67 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
68 // values are spilled.
69 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
71 // Everything we know about a live virtual register.
73 MachineInstr *LastUse; // Last instr to use reg.
74 unsigned PhysReg; // Currently held here.
75 unsigned short LastOpNum; // OpNum on LastUse.
76 bool Dirty; // Register needs spill.
78 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
82 typedef DenseMap<unsigned, LiveReg> LiveRegMap;
83 typedef LiveRegMap::value_type LiveRegEntry;
85 // LiveVirtRegs - This map contains entries for each virtual register
86 // that is currently available in a physical register.
87 LiveRegMap LiveVirtRegs;
89 DenseMap<unsigned, SmallVector<MachineInstr *, 4> > LiveDbgValueMap;
91 // RegState - Track the state of a physical register.
93 // A disabled register is not available for allocation, but an alias may
94 // be in use. A register can only be moved out of the disabled state if
95 // all aliases are disabled.
98 // A free register is not currently in use and can be allocated
99 // immediately without checking aliases.
102 // A reserved register has been assigned explicitly (e.g., setting up a
103 // call parameter), and it remains reserved until it is used.
106 // A register state may also be a virtual register number, indication that
107 // the physical register is currently allocated to a virtual register. In
108 // that case, LiveVirtRegs contains the inverse mapping.
111 // PhysRegState - One of the RegState enums, or a virtreg.
112 std::vector<unsigned> PhysRegState;
114 // UsedInInstr - BitVector of physregs that are used in the current
115 // instruction, and so cannot be allocated.
116 BitVector UsedInInstr;
118 // SkippedInstrs - Descriptors of instructions whose clobber list was
119 // ignored because all registers were spilled. It is still necessary to
120 // mark all the clobbered registers as used by the function.
121 SmallPtrSet<const TargetInstrDesc*, 4> SkippedInstrs;
123 // isBulkSpilling - This flag is set when LiveRegMap will be cleared
124 // completely after spilling all live registers. LiveRegMap entries should
131 spillImpossible = ~0u
134 virtual const char *getPassName() const {
135 return "Fast Register Allocator";
138 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
139 AU.setPreservesCFG();
140 AU.addRequiredID(PHIEliminationID);
141 AU.addRequiredID(TwoAddressInstructionPassID);
142 MachineFunctionPass::getAnalysisUsage(AU);
146 bool runOnMachineFunction(MachineFunction &Fn);
147 void AllocateBasicBlock();
148 void handleThroughOperands(MachineInstr *MI,
149 SmallVectorImpl<unsigned> &VirtDead);
150 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
151 bool isLastUseOfLocalReg(MachineOperand&);
153 void addKillFlag(const LiveReg&);
154 void killVirtReg(LiveRegMap::iterator);
155 void killVirtReg(unsigned VirtReg);
156 void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
157 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
159 void usePhysReg(MachineOperand&);
160 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
161 unsigned calcSpillCost(unsigned PhysReg) const;
162 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
163 void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
164 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
165 unsigned VirtReg, unsigned Hint);
166 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
167 unsigned VirtReg, unsigned Hint);
168 void spillAll(MachineInstr *MI);
169 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
174 /// getStackSpaceFor - This allocates space for the specified virtual register
175 /// to be held on the stack.
176 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
177 // Find the location Reg would belong...
178 int SS = StackSlotForVirtReg[VirtReg];
180 return SS; // Already has space allocated?
182 // Allocate a new stack object for this spill location...
183 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
187 StackSlotForVirtReg[VirtReg] = FrameIdx;
191 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
192 /// its virtual register, and it is guaranteed to be a block-local register.
194 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
195 // Check for non-debug uses or defs following MO.
196 // This is the most likely way to fail - fast path it.
197 MachineOperand *Next = &MO;
198 while ((Next = Next->getNextOperandForReg()))
199 if (!Next->isDebug())
202 // If the register has ever been spilled or reloaded, we conservatively assume
203 // it is a global register used in multiple blocks.
204 if (StackSlotForVirtReg[MO.getReg()] != -1)
207 // Check that the use/def chain has exactly one operand - MO.
208 return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO;
211 /// addKillFlag - Set kill flags on last use of a virtual register.
212 void RAFast::addKillFlag(const LiveReg &LR) {
213 if (!LR.LastUse) return;
214 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
215 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
216 if (MO.getReg() == LR.PhysReg)
219 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
223 /// killVirtReg - Mark virtreg as no longer available.
224 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
225 addKillFlag(LRI->second);
226 const LiveReg &LR = LRI->second;
227 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
228 PhysRegState[LR.PhysReg] = regFree;
229 // Erase from LiveVirtRegs unless we're spilling in bulk.
231 LiveVirtRegs.erase(LRI);
234 /// killVirtReg - Mark virtreg as no longer available.
235 void RAFast::killVirtReg(unsigned VirtReg) {
236 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
237 "killVirtReg needs a virtual register");
238 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
239 if (LRI != LiveVirtRegs.end())
243 /// spillVirtReg - This method spills the value specified by VirtReg into the
244 /// corresponding stack slot if needed.
245 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
246 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
247 "Spilling a physical register is illegal!");
248 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
249 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
250 spillVirtReg(MI, LRI);
253 /// spillVirtReg - Do the actual work of spilling.
254 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
255 LiveRegMap::iterator LRI) {
256 LiveReg &LR = LRI->second;
257 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
260 // If this physreg is used by the instruction, we want to kill it on the
261 // instruction, not on the spill.
262 bool SpillKill = LR.LastUse != MI;
264 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->first, TRI)
265 << " in " << PrintReg(LR.PhysReg, TRI));
266 const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
267 int FI = getStackSpaceFor(LRI->first, RC);
268 DEBUG(dbgs() << " to stack slot #" << FI << "\n");
269 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
270 ++NumStores; // Update statistics
272 // If this register is used by DBG_VALUE then insert new DBG_VALUE to
273 // identify spilled location as the place to find corresponding variable's
275 SmallVector<MachineInstr *, 4> &LRIDbgValues = LiveDbgValueMap[LRI->first];
276 for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {
277 MachineInstr *DBG = LRIDbgValues[li];
278 const MDNode *MDPtr =
279 DBG->getOperand(DBG->getNumOperands()-1).getMetadata();
281 if (DBG->getOperand(1).isImm())
282 Offset = DBG->getOperand(1).getImm();
284 if (MI == MBB->end()) {
285 // If MI is at basic block end then use last instruction's location.
286 MachineBasicBlock::iterator EI = MI;
287 DL = (--EI)->getDebugLoc();
290 DL = MI->getDebugLoc();
291 if (MachineInstr *NewDV =
292 TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) {
293 MachineBasicBlock *MBB = DBG->getParent();
294 MBB->insert(MI, NewDV);
295 DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
298 // Now this register is spilled there is should not be any DBG_VALUE pointing
299 // to this register because they are all pointing to spilled value now.
300 LRIDbgValues.clear();
302 LR.LastUse = 0; // Don't kill register again
307 /// spillAll - Spill all dirty virtregs without killing them.
308 void RAFast::spillAll(MachineInstr *MI) {
309 if (LiveVirtRegs.empty()) return;
310 isBulkSpilling = true;
311 // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
312 // of spilling here is deterministic, if arbitrary.
313 for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
316 LiveVirtRegs.clear();
317 isBulkSpilling = false;
320 /// usePhysReg - Handle the direct use of a physical register.
321 /// Check that the register is not used by a virtreg.
322 /// Kill the physreg, marking it free.
323 /// This may add implicit kills to MO->getParent() and invalidate MO.
324 void RAFast::usePhysReg(MachineOperand &MO) {
325 unsigned PhysReg = MO.getReg();
326 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
327 "Bad usePhysReg operand");
329 switch (PhysRegState[PhysReg]) {
333 PhysRegState[PhysReg] = regFree;
336 UsedInInstr.set(PhysReg);
340 // The physreg was allocated to a virtual register. That means the value we
341 // wanted has been clobbered.
342 llvm_unreachable("Instruction uses an allocated register");
345 // Maybe a superregister is reserved?
346 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
347 unsigned Alias = *AS; ++AS) {
348 switch (PhysRegState[Alias]) {
352 assert(TRI->isSuperRegister(PhysReg, Alias) &&
353 "Instruction is not using a subregister of a reserved register");
354 // Leave the superregister in the working set.
355 PhysRegState[Alias] = regFree;
356 UsedInInstr.set(Alias);
357 MO.getParent()->addRegisterKilled(Alias, TRI, true);
360 if (TRI->isSuperRegister(PhysReg, Alias)) {
361 // Leave the superregister in the working set.
362 UsedInInstr.set(Alias);
363 MO.getParent()->addRegisterKilled(Alias, TRI, true);
366 // Some other alias was in the working set - clear it.
367 PhysRegState[Alias] = regDisabled;
370 llvm_unreachable("Instruction uses an alias of an allocated register");
374 // All aliases are disabled, bring register into working set.
375 PhysRegState[PhysReg] = regFree;
376 UsedInInstr.set(PhysReg);
380 /// definePhysReg - Mark PhysReg as reserved or free after spilling any
381 /// virtregs. This is very similar to defineVirtReg except the physreg is
382 /// reserved instead of allocated.
383 void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
385 UsedInInstr.set(PhysReg);
386 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
390 spillVirtReg(MI, VirtReg);
394 PhysRegState[PhysReg] = NewState;
398 // This is a disabled register, disable all aliases.
399 PhysRegState[PhysReg] = NewState;
400 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
401 unsigned Alias = *AS; ++AS) {
402 switch (unsigned VirtReg = PhysRegState[Alias]) {
406 spillVirtReg(MI, VirtReg);
410 PhysRegState[Alias] = regDisabled;
411 if (TRI->isSuperRegister(PhysReg, Alias))
419 // calcSpillCost - Return the cost of spilling clearing out PhysReg and
420 // aliases so it is free for allocation.
421 // Returns 0 when PhysReg is free or disabled with all aliases disabled - it
422 // can be allocated directly.
423 // Returns spillImpossible when PhysReg or an alias can't be spilled.
424 unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
425 if (UsedInInstr.test(PhysReg)) {
426 DEBUG(dbgs() << "PhysReg: " << PhysReg << " is already used in instr.\n");
427 return spillImpossible;
429 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
435 DEBUG(dbgs() << "VirtReg: " << VirtReg << " corresponding to PhysReg: "
436 << PhysReg << " is reserved already.\n");
437 return spillImpossible;
439 return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
442 // This is a disabled register, add up cost of aliases.
443 DEBUG(dbgs() << "\tRegister: " << PhysReg << " is disabled.\n");
445 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
446 unsigned Alias = *AS; ++AS) {
447 if (UsedInInstr.test(Alias))
448 return spillImpossible;
449 switch (unsigned VirtReg = PhysRegState[Alias]) {
456 return spillImpossible;
458 Cost += LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
466 /// assignVirtToPhysReg - This method updates local state so that we know
467 /// that PhysReg is the proper container for VirtReg now. The physical
468 /// register must not be used for anything else when this is called.
470 void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) {
471 DEBUG(dbgs() << "Assigning " << PrintReg(LRE.first, TRI) << " to "
472 << PrintReg(PhysReg, TRI) << "\n");
473 PhysRegState[PhysReg] = LRE.first;
474 assert(!LRE.second.PhysReg && "Already assigned a physreg");
475 LRE.second.PhysReg = PhysReg;
478 /// allocVirtReg - Allocate a physical register for VirtReg.
479 void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
480 const unsigned VirtReg = LRE.first;
482 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
483 "Can only allocate virtual registers");
485 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
487 // Ignore invalid hints.
488 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
489 !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint)))
492 // Take hint when possible.
494 // Ignore the hint if we would have to spill a dirty register.
495 unsigned Cost = calcSpillCost(Hint);
496 if (Cost < spillDirty) {
498 definePhysReg(MI, Hint, regFree);
499 return assignVirtToPhysReg(LRE, Hint);
503 ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC);
505 // First try to find a completely free register.
506 for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
507 unsigned PhysReg = *I;
508 if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg))
509 return assignVirtToPhysReg(LRE, PhysReg);
512 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
513 << RC->getName() << "\n");
515 unsigned BestReg = 0, BestCost = spillImpossible;
516 for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
517 unsigned Cost = calcSpillCost(*I);
518 DEBUG(dbgs() << "\tRegister: " << *I << "\n");
519 DEBUG(dbgs() << "\tCost: " << Cost << "\n");
520 DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n");
521 // Cost is 0 when all aliases are already disabled.
523 return assignVirtToPhysReg(LRE, *I);
525 BestReg = *I, BestCost = Cost;
529 definePhysReg(MI, BestReg, regFree);
530 return assignVirtToPhysReg(LRE, BestReg);
533 // Nothing we can do.
535 raw_string_ostream Msg(msg);
536 Msg << "Ran out of registers during register allocation!";
537 if (MI->isInlineAsm()) {
538 Msg << "\nPlease check your inline asm statement for "
539 << "invalid constraints:\n";
542 report_fatal_error(Msg.str());
545 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
546 RAFast::LiveRegMap::iterator
547 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
548 unsigned VirtReg, unsigned Hint) {
549 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
550 "Not a virtual register");
551 LiveRegMap::iterator LRI;
553 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
554 LiveReg &LR = LRI->second;
556 // If there is no hint, peek at the only use of this register.
557 if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
558 MRI->hasOneNonDBGUse(VirtReg)) {
559 const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
560 // It's a copy, use the destination register as a hint.
561 if (UseMI.isCopyLike())
562 Hint = UseMI.getOperand(0).getReg();
564 allocVirtReg(MI, *LRI, Hint);
565 } else if (LR.LastUse) {
566 // Redefining a live register - kill at the last use, unless it is this
567 // instruction defining VirtReg multiple times.
568 if (LR.LastUse != MI || LR.LastUse->getOperand(LR.LastOpNum).isUse())
571 assert(LR.PhysReg && "Register not assigned");
573 LR.LastOpNum = OpNum;
575 UsedInInstr.set(LR.PhysReg);
579 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
580 RAFast::LiveRegMap::iterator
581 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
582 unsigned VirtReg, unsigned Hint) {
583 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
584 "Not a virtual register");
585 LiveRegMap::iterator LRI;
587 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
588 LiveReg &LR = LRI->second;
589 MachineOperand &MO = MI->getOperand(OpNum);
591 allocVirtReg(MI, *LRI, Hint);
592 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
593 int FrameIndex = getStackSpaceFor(VirtReg, RC);
594 DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
595 << PrintReg(LR.PhysReg, TRI) << "\n");
596 TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI);
598 } else if (LR.Dirty) {
599 if (isLastUseOfLocalReg(MO)) {
600 DEBUG(dbgs() << "Killing last use: " << MO << "\n");
605 } else if (MO.isKill()) {
606 DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
608 } else if (MO.isDead()) {
609 DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
612 } else if (MO.isKill()) {
613 // We must remove kill flags from uses of reloaded registers because the
614 // register would be killed immediately, and there might be a second use:
615 // %foo = OR %x<kill>, %x
616 // This would cause a second reload of %x into a different register.
617 DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
619 } else if (MO.isDead()) {
620 DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
623 assert(LR.PhysReg && "Register not assigned");
625 LR.LastOpNum = OpNum;
626 UsedInInstr.set(LR.PhysReg);
630 // setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering
631 // subregs. This may invalidate any operand pointers.
632 // Return true if the operand kills its register.
633 bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) {
634 MachineOperand &MO = MI->getOperand(OpNum);
635 if (!MO.getSubReg()) {
637 return MO.isKill() || MO.isDead();
640 // Handle subregister index.
641 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
644 // A kill flag implies killing the full register. Add corresponding super
647 MI->addRegisterKilled(PhysReg, TRI, true);
653 // Handle special instruction operand like early clobbers and tied ops when
654 // there are additional physreg defines.
655 void RAFast::handleThroughOperands(MachineInstr *MI,
656 SmallVectorImpl<unsigned> &VirtDead) {
657 DEBUG(dbgs() << "Scanning for through registers:");
658 SmallSet<unsigned, 8> ThroughRegs;
659 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
660 MachineOperand &MO = MI->getOperand(i);
661 if (!MO.isReg()) continue;
662 unsigned Reg = MO.getReg();
663 if (!TargetRegisterInfo::isVirtualRegister(Reg))
665 if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
666 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
667 if (ThroughRegs.insert(Reg))
668 DEBUG(dbgs() << ' ' << PrintReg(Reg));
672 // If any physreg defines collide with preallocated through registers,
673 // we must spill and reallocate.
674 DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
675 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
676 MachineOperand &MO = MI->getOperand(i);
677 if (!MO.isReg() || !MO.isDef()) continue;
678 unsigned Reg = MO.getReg();
679 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
680 UsedInInstr.set(Reg);
681 if (ThroughRegs.count(PhysRegState[Reg]))
682 definePhysReg(MI, Reg, regFree);
683 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
684 UsedInInstr.set(*AS);
685 if (ThroughRegs.count(PhysRegState[*AS]))
686 definePhysReg(MI, *AS, regFree);
690 SmallVector<unsigned, 8> PartialDefs;
691 DEBUG(dbgs() << "Allocating tied uses and early clobbers.\n");
692 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
693 MachineOperand &MO = MI->getOperand(i);
694 if (!MO.isReg()) continue;
695 unsigned Reg = MO.getReg();
696 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
699 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
700 DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
702 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
703 unsigned PhysReg = LRI->second.PhysReg;
704 setPhysReg(MI, i, PhysReg);
705 // Note: we don't update the def operand yet. That would cause the normal
706 // def-scan to attempt spilling.
707 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
708 DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
709 // Reload the register, but don't assign to the operand just yet.
710 // That would confuse the later phys-def processing pass.
711 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
712 PartialDefs.push_back(LRI->second.PhysReg);
713 } else if (MO.isEarlyClobber()) {
714 // Note: defineVirtReg may invalidate MO.
715 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
716 unsigned PhysReg = LRI->second.PhysReg;
717 if (setPhysReg(MI, i, PhysReg))
718 VirtDead.push_back(Reg);
722 // Restore UsedInInstr to a state usable for allocating normal virtual uses.
724 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
725 MachineOperand &MO = MI->getOperand(i);
726 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
727 unsigned Reg = MO.getReg();
728 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
729 DEBUG(dbgs() << "\tSetting reg " << Reg << " as used in instr\n");
730 UsedInInstr.set(Reg);
733 // Also mark PartialDefs as used to avoid reallocation.
734 for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
735 UsedInInstr.set(PartialDefs[i]);
738 void RAFast::AllocateBasicBlock() {
739 DEBUG(dbgs() << "\nAllocating " << *MBB);
741 // FIXME: This should probably be added by instruction selection instead?
742 // If the last instruction in the block is a return, make sure to mark it as
743 // using all of the live-out values in the function. Things marked both call
744 // and return are tail calls; do not do this for them. The tail callee need
745 // not take the same registers as input that it produces as output, and there
746 // are dependencies for its input registers elsewhere.
747 if (!MBB->empty() && MBB->back().getDesc().isReturn() &&
748 !MBB->back().getDesc().isCall()) {
749 MachineInstr *Ret = &MBB->back();
751 for (MachineRegisterInfo::liveout_iterator
752 I = MF->getRegInfo().liveout_begin(),
753 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
754 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
755 "Cannot have a live-out virtual register.");
757 // Add live-out registers as implicit uses.
758 Ret->addRegisterKilled(*I, TRI, true);
762 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
763 assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
765 MachineBasicBlock::iterator MII = MBB->begin();
767 // Add live-in registers as live.
768 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
769 E = MBB->livein_end(); I != E; ++I)
770 if (RegClassInfo.isAllocatable(*I))
771 definePhysReg(MII, *I, regReserved);
773 SmallVector<unsigned, 8> VirtDead;
774 SmallVector<MachineInstr*, 32> Coalesced;
776 // Otherwise, sequentially allocate each instruction in the MBB.
777 while (MII != MBB->end()) {
778 MachineInstr *MI = MII++;
779 const TargetInstrDesc &TID = MI->getDesc();
781 dbgs() << "\n>> " << *MI << "Regs:";
782 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
783 if (PhysRegState[Reg] == regDisabled) continue;
784 dbgs() << " " << TRI->getName(Reg);
785 switch(PhysRegState[Reg]) {
792 dbgs() << '=' << PrintReg(PhysRegState[Reg]);
793 if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
795 assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
801 // Check that LiveVirtRegs is the inverse.
802 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
803 e = LiveVirtRegs.end(); i != e; ++i) {
804 assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
806 assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
808 assert(PhysRegState[i->second.PhysReg] == i->first &&
813 // Debug values are not allowed to change codegen in any way.
814 if (MI->isDebugValue()) {
815 bool ScanDbgValue = true;
816 while (ScanDbgValue) {
817 ScanDbgValue = false;
818 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
819 MachineOperand &MO = MI->getOperand(i);
820 if (!MO.isReg()) continue;
821 unsigned Reg = MO.getReg();
822 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
823 LiveDbgValueMap[Reg].push_back(MI);
824 LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
825 if (LRI != LiveVirtRegs.end())
826 setPhysReg(MI, i, LRI->second.PhysReg);
828 int SS = StackSlotForVirtReg[Reg];
830 // We can't allocate a physreg for a DebugValue, sorry!
831 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
835 // Modify DBG_VALUE now that the value is in a spill slot.
836 int64_t Offset = MI->getOperand(1).getImm();
837 const MDNode *MDPtr =
838 MI->getOperand(MI->getNumOperands()-1).getMetadata();
839 DebugLoc DL = MI->getDebugLoc();
840 if (MachineInstr *NewDV =
841 TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {
842 DEBUG(dbgs() << "Modifying debug info due to spill:" <<
844 MachineBasicBlock *MBB = MI->getParent();
845 MBB->insert(MBB->erase(MI), NewDV);
846 // Scan NewDV operands from the beginning.
851 // We can't allocate a physreg for a DebugValue; sorry!
852 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
863 // If this is a copy, we may be able to coalesce.
864 unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
866 CopyDst = MI->getOperand(0).getReg();
867 CopySrc = MI->getOperand(1).getReg();
868 CopyDstSub = MI->getOperand(0).getSubReg();
869 CopySrcSub = MI->getOperand(1).getSubReg();
872 // Track registers used by instruction.
876 // Mark physreg uses and early clobbers as used.
877 // Find the end of the virtreg operands
878 unsigned VirtOpEnd = 0;
879 bool hasTiedOps = false;
880 bool hasEarlyClobbers = false;
881 bool hasPartialRedefs = false;
882 bool hasPhysDefs = false;
883 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
884 MachineOperand &MO = MI->getOperand(i);
885 if (!MO.isReg()) continue;
886 unsigned Reg = MO.getReg();
888 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
891 hasTiedOps = hasTiedOps ||
892 TID.getOperandConstraint(i, TOI::TIED_TO) != -1;
894 if (MO.isEarlyClobber())
895 hasEarlyClobbers = true;
896 if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
897 hasPartialRedefs = true;
901 if (!RegClassInfo.isAllocatable(Reg)) continue;
904 } else if (MO.isEarlyClobber()) {
905 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
906 regFree : regReserved);
907 hasEarlyClobbers = true;
912 // The instruction may have virtual register operands that must be allocated
913 // the same register at use-time and def-time: early clobbers and tied
914 // operands. If there are also physical defs, these registers must avoid
915 // both physical defs and uses, making them more constrained than normal
917 // Similarly, if there are multiple defs and tied operands, we must make
918 // sure the same register is allocated to uses and defs.
919 // We didn't detect inline asm tied operands above, so just make this extra
920 // pass for all inline asm.
921 if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
922 (hasTiedOps && (hasPhysDefs || TID.getNumDefs() > 1))) {
923 handleThroughOperands(MI, VirtDead);
924 // Don't attempt coalescing when we have funny stuff going on.
926 // Pretend we have early clobbers so the use operands get marked below.
927 // This is not necessary for the common case of a single tied use.
928 hasEarlyClobbers = true;
932 // Allocate virtreg uses.
933 for (unsigned i = 0; i != VirtOpEnd; ++i) {
934 MachineOperand &MO = MI->getOperand(i);
935 if (!MO.isReg()) continue;
936 unsigned Reg = MO.getReg();
937 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
939 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
940 unsigned PhysReg = LRI->second.PhysReg;
941 CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
942 if (setPhysReg(MI, i, PhysReg))
947 MRI->addPhysRegsUsed(UsedInInstr);
949 // Track registers defined by instruction - early clobbers and tied uses at
952 if (hasEarlyClobbers) {
953 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
954 MachineOperand &MO = MI->getOperand(i);
955 if (!MO.isReg()) continue;
956 unsigned Reg = MO.getReg();
957 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
958 // Look for physreg defs and tied uses.
959 if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue;
960 UsedInInstr.set(Reg);
961 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
962 UsedInInstr.set(*AS);
966 unsigned DefOpEnd = MI->getNumOperands();
968 // Spill all virtregs before a call. This serves two purposes: 1. If an
969 // exception is thrown, the landing pad is going to expect to find
970 // registers in their spill slots, and 2. we don't have to wade through
971 // all the <imp-def> operands on the call instruction.
972 DefOpEnd = VirtOpEnd;
973 DEBUG(dbgs() << " Spilling remaining registers before call.\n");
976 // The imp-defs are skipped below, but we still need to mark those
977 // registers as used by the function.
978 SkippedInstrs.insert(&TID);
982 // Allocate defs and collect dead defs.
983 for (unsigned i = 0; i != DefOpEnd; ++i) {
984 MachineOperand &MO = MI->getOperand(i);
985 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
987 unsigned Reg = MO.getReg();
989 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
990 if (!RegClassInfo.isAllocatable(Reg)) continue;
991 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
992 regFree : regReserved);
995 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
996 unsigned PhysReg = LRI->second.PhysReg;
997 if (setPhysReg(MI, i, PhysReg)) {
998 VirtDead.push_back(Reg);
999 CopyDst = 0; // cancel coalescing;
1001 CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
1004 // Kill dead defs after the scan to ensure that multiple defs of the same
1005 // register are allocated identically. We didn't need to do this for uses
1006 // because we are crerating our own kill flags, and they are always at the
1008 for (unsigned i = 0, e = VirtDead.size(); i != e; ++i)
1009 killVirtReg(VirtDead[i]);
1012 MRI->addPhysRegsUsed(UsedInInstr);
1014 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
1015 DEBUG(dbgs() << "-- coalescing: " << *MI);
1016 Coalesced.push_back(MI);
1018 DEBUG(dbgs() << "<< " << *MI);
1022 // Spill all physical registers holding virtual registers now.
1023 DEBUG(dbgs() << "Spilling live registers at end of block.\n");
1024 spillAll(MBB->getFirstTerminator());
1026 // Erase all the coalesced copies. We are delaying it until now because
1027 // LiveVirtRegs might refer to the instrs.
1028 for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
1029 MBB->erase(Coalesced[i]);
1030 NumCopies += Coalesced.size();
1035 /// runOnMachineFunction - Register allocate the whole function
1037 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
1038 DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
1039 << "********** Function: "
1040 << ((Value*)Fn.getFunction())->getName() << '\n');
1042 MRI = &MF->getRegInfo();
1043 TM = &Fn.getTarget();
1044 TRI = TM->getRegisterInfo();
1045 TII = TM->getInstrInfo();
1046 RegClassInfo.runOnMachineFunction(Fn);
1047 UsedInInstr.resize(TRI->getNumRegs());
1049 // initialize the virtual->physical register map to have a 'null'
1050 // mapping for all virtual registers
1051 StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
1053 // Loop over all of the basic blocks, eliminating virtual register references
1054 for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
1055 MBBi != MBBe; ++MBBi) {
1057 AllocateBasicBlock();
1060 // Make sure the set of used physregs is closed under subreg operations.
1061 MRI->closePhysRegsUsed(*TRI);
1063 // Add the clobber lists for all the instructions we skipped earlier.
1064 for (SmallPtrSet<const TargetInstrDesc*, 4>::const_iterator
1065 I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I)
1066 if (const unsigned *Defs = (*I)->getImplicitDefs())
1068 MRI->setPhysRegUsed(*Defs++);
1070 SkippedInstrs.clear();
1071 StackSlotForVirtReg.clear();
1072 LiveDbgValueMap.clear();
1076 FunctionPass *llvm::createFastRegisterAllocator() {
1077 return new RAFast();