1 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/RegAllocRegistry.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/IndexedMap.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(NumStores, "Number of stores added");
40 STATISTIC(NumLoads , "Number of loads added");
41 STATISTIC(NumCopies, "Number of copies coalesced");
43 static RegisterRegAlloc
44 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
47 class RAFast : public MachineFunctionPass {
50 RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
51 isBulkSpilling(false) {
52 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
53 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
56 const TargetMachine *TM;
58 MachineRegisterInfo *MRI;
59 const TargetRegisterInfo *TRI;
60 const TargetInstrInfo *TII;
62 // Basic block currently being allocated.
63 MachineBasicBlock *MBB;
65 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
66 // values are spilled.
67 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
69 // Everything we know about a live virtual register.
71 MachineInstr *LastUse; // Last instr to use reg.
72 unsigned PhysReg; // Currently held here.
73 unsigned short LastOpNum; // OpNum on LastUse.
74 bool Dirty; // Register needs spill.
76 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
80 typedef DenseMap<unsigned, LiveReg> LiveRegMap;
81 typedef LiveRegMap::value_type LiveRegEntry;
83 // LiveVirtRegs - This map contains entries for each virtual register
84 // that is currently available in a physical register.
85 LiveRegMap LiveVirtRegs;
87 DenseMap<unsigned, MachineInstr *> LiveDbgValueMap;
89 // RegState - Track the state of a physical register.
91 // A disabled register is not available for allocation, but an alias may
92 // be in use. A register can only be moved out of the disabled state if
93 // all aliases are disabled.
96 // A free register is not currently in use and can be allocated
97 // immediately without checking aliases.
100 // A reserved register has been assigned expolicitly (e.g., setting up a
101 // call parameter), and it remains reserved until it is used.
104 // A register state may also be a virtual register number, indication that
105 // the physical register is currently allocated to a virtual register. In
106 // that case, LiveVirtRegs contains the inverse mapping.
109 // PhysRegState - One of the RegState enums, or a virtreg.
110 std::vector<unsigned> PhysRegState;
112 // UsedInInstr - BitVector of physregs that are used in the current
113 // instruction, and so cannot be allocated.
114 BitVector UsedInInstr;
116 // Allocatable - vector of allocatable physical registers.
117 BitVector Allocatable;
119 // SkippedInstrs - Descriptors of instructions whose clobber list was
120 // ignored because all registers were spilled. It is still necessary to
121 // mark all the clobbered registers as used by the function.
122 SmallPtrSet<const TargetInstrDesc*, 4> SkippedInstrs;
124 // isBulkSpilling - This flag is set when LiveRegMap will be cleared
125 // completely after spilling all live registers. LiveRegMap entries should
132 spillImpossible = ~0u
135 virtual const char *getPassName() const {
136 return "Fast Register Allocator";
139 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
140 AU.setPreservesCFG();
141 AU.addRequiredID(PHIEliminationID);
142 AU.addRequiredID(TwoAddressInstructionPassID);
143 MachineFunctionPass::getAnalysisUsage(AU);
147 bool runOnMachineFunction(MachineFunction &Fn);
148 void AllocateBasicBlock();
149 void handleThroughOperands(MachineInstr *MI,
150 SmallVectorImpl<unsigned> &VirtDead);
151 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
152 bool isLastUseOfLocalReg(MachineOperand&);
154 void addKillFlag(const LiveReg&);
155 void killVirtReg(LiveRegMap::iterator);
156 void killVirtReg(unsigned VirtReg);
157 void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
158 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
160 void usePhysReg(MachineOperand&);
161 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
162 unsigned calcSpillCost(unsigned PhysReg) const;
163 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
164 void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
165 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
166 unsigned VirtReg, unsigned Hint);
167 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
168 unsigned VirtReg, unsigned Hint);
169 void spillAll(MachineInstr *MI);
170 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
175 /// getStackSpaceFor - This allocates space for the specified virtual register
176 /// to be held on the stack.
177 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
178 // Find the location Reg would belong...
179 int SS = StackSlotForVirtReg[VirtReg];
181 return SS; // Already has space allocated?
183 // Allocate a new stack object for this spill location...
184 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
188 StackSlotForVirtReg[VirtReg] = FrameIdx;
192 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
193 /// its virtual register, and it is guaranteed to be a block-local register.
195 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
196 // Check for non-debug uses or defs following MO.
197 // This is the most likely way to fail - fast path it.
198 MachineOperand *Next = &MO;
199 while ((Next = Next->getNextOperandForReg()))
200 if (!Next->isDebug())
203 // If the register has ever been spilled or reloaded, we conservatively assume
204 // it is a global register used in multiple blocks.
205 if (StackSlotForVirtReg[MO.getReg()] != -1)
208 // Check that the use/def chain has exactly one operand - MO.
209 return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO;
212 /// addKillFlag - Set kill flags on last use of a virtual register.
213 void RAFast::addKillFlag(const LiveReg &LR) {
214 if (!LR.LastUse) return;
215 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
216 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
217 if (MO.getReg() == LR.PhysReg)
220 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
224 /// killVirtReg - Mark virtreg as no longer available.
225 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
226 addKillFlag(LRI->second);
227 const LiveReg &LR = LRI->second;
228 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
229 PhysRegState[LR.PhysReg] = regFree;
230 // Erase from LiveVirtRegs unless we're spilling in bulk.
232 LiveVirtRegs.erase(LRI);
235 /// killVirtReg - Mark virtreg as no longer available.
236 void RAFast::killVirtReg(unsigned VirtReg) {
237 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
238 "killVirtReg needs a virtual register");
239 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
240 if (LRI != LiveVirtRegs.end())
244 /// spillVirtReg - This method spills the value specified by VirtReg into the
245 /// corresponding stack slot if needed.
246 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
247 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
248 "Spilling a physical register is illegal!");
249 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
250 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
251 spillVirtReg(MI, LRI);
254 /// spillVirtReg - Do the actual work of spilling.
255 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
256 LiveRegMap::iterator LRI) {
257 LiveReg &LR = LRI->second;
258 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
261 // If this physreg is used by the instruction, we want to kill it on the
262 // instruction, not on the spill.
263 bool SpillKill = LR.LastUse != MI;
265 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->first, TRI)
266 << " in " << PrintReg(LR.PhysReg, TRI));
267 const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
268 int FI = getStackSpaceFor(LRI->first, RC);
269 DEBUG(dbgs() << " to stack slot #" << FI << "\n");
270 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
271 ++NumStores; // Update statistics
273 // If this register is used by DBG_VALUE then insert new DBG_VALUE to
274 // identify spilled location as the place to find corresponding variable's
276 if (MachineInstr *DBG = LiveDbgValueMap.lookup(LRI->first)) {
277 const MDNode *MDPtr =
278 DBG->getOperand(DBG->getNumOperands()-1).getMetadata();
280 if (DBG->getOperand(1).isImm())
281 Offset = DBG->getOperand(1).getImm();
283 if (MI == MBB->end()) {
284 // If MI is at basic block end then use last instruction's location.
285 MachineBasicBlock::iterator EI = MI;
286 DL = (--EI)->getDebugLoc();
289 DL = MI->getDebugLoc();
290 if (MachineInstr *NewDV =
291 TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) {
292 MachineBasicBlock *MBB = DBG->getParent();
293 MBB->insert(MI, NewDV);
294 DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
295 LiveDbgValueMap[LRI->first] = NewDV;
299 LR.LastUse = 0; // Don't kill register again
304 /// spillAll - Spill all dirty virtregs without killing them.
305 void RAFast::spillAll(MachineInstr *MI) {
306 if (LiveVirtRegs.empty()) return;
307 isBulkSpilling = true;
308 // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
309 // of spilling here is deterministic, if arbitrary.
310 for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
313 LiveVirtRegs.clear();
314 isBulkSpilling = false;
317 /// usePhysReg - Handle the direct use of a physical register.
318 /// Check that the register is not used by a virtreg.
319 /// Kill the physreg, marking it free.
320 /// This may add implicit kills to MO->getParent() and invalidate MO.
321 void RAFast::usePhysReg(MachineOperand &MO) {
322 unsigned PhysReg = MO.getReg();
323 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
324 "Bad usePhysReg operand");
326 switch (PhysRegState[PhysReg]) {
330 PhysRegState[PhysReg] = regFree;
333 UsedInInstr.set(PhysReg);
337 // The physreg was allocated to a virtual register. That means the value we
338 // wanted has been clobbered.
339 llvm_unreachable("Instruction uses an allocated register");
342 // Maybe a superregister is reserved?
343 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
344 unsigned Alias = *AS; ++AS) {
345 switch (PhysRegState[Alias]) {
349 assert(TRI->isSuperRegister(PhysReg, Alias) &&
350 "Instruction is not using a subregister of a reserved register");
351 // Leave the superregister in the working set.
352 PhysRegState[Alias] = regFree;
353 UsedInInstr.set(Alias);
354 MO.getParent()->addRegisterKilled(Alias, TRI, true);
357 if (TRI->isSuperRegister(PhysReg, Alias)) {
358 // Leave the superregister in the working set.
359 UsedInInstr.set(Alias);
360 MO.getParent()->addRegisterKilled(Alias, TRI, true);
363 // Some other alias was in the working set - clear it.
364 PhysRegState[Alias] = regDisabled;
367 llvm_unreachable("Instruction uses an alias of an allocated register");
371 // All aliases are disabled, bring register into working set.
372 PhysRegState[PhysReg] = regFree;
373 UsedInInstr.set(PhysReg);
377 /// definePhysReg - Mark PhysReg as reserved or free after spilling any
378 /// virtregs. This is very similar to defineVirtReg except the physreg is
379 /// reserved instead of allocated.
380 void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
382 UsedInInstr.set(PhysReg);
383 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
387 spillVirtReg(MI, VirtReg);
391 PhysRegState[PhysReg] = NewState;
395 // This is a disabled register, disable all aliases.
396 PhysRegState[PhysReg] = NewState;
397 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
398 unsigned Alias = *AS; ++AS) {
399 UsedInInstr.set(Alias);
400 switch (unsigned VirtReg = PhysRegState[Alias]) {
404 spillVirtReg(MI, VirtReg);
408 PhysRegState[Alias] = regDisabled;
409 if (TRI->isSuperRegister(PhysReg, Alias))
417 // calcSpillCost - Return the cost of spilling clearing out PhysReg and
418 // aliases so it is free for allocation.
419 // Returns 0 when PhysReg is free or disabled with all aliases disabled - it
420 // can be allocated directly.
421 // Returns spillImpossible when PhysReg or an alias can't be spilled.
422 unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
423 if (UsedInInstr.test(PhysReg))
424 return spillImpossible;
425 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
431 return spillImpossible;
433 return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
436 // This is a disabled register, add up const of aliases.
438 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
439 unsigned Alias = *AS; ++AS) {
440 if (UsedInInstr.test(Alias))
441 return spillImpossible;
442 switch (unsigned VirtReg = PhysRegState[Alias]) {
449 return spillImpossible;
451 Cost += LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
459 /// assignVirtToPhysReg - This method updates local state so that we know
460 /// that PhysReg is the proper container for VirtReg now. The physical
461 /// register must not be used for anything else when this is called.
463 void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) {
464 DEBUG(dbgs() << "Assigning " << PrintReg(LRE.first, TRI) << " to "
465 << PrintReg(PhysReg, TRI) << "\n");
466 PhysRegState[PhysReg] = LRE.first;
467 assert(!LRE.second.PhysReg && "Already assigned a physreg");
468 LRE.second.PhysReg = PhysReg;
471 /// allocVirtReg - Allocate a physical register for VirtReg.
472 void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
473 const unsigned VirtReg = LRE.first;
475 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
476 "Can only allocate virtual registers");
478 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
480 // Ignore invalid hints.
481 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
482 !RC->contains(Hint) || !Allocatable.test(Hint)))
485 // Take hint when possible.
487 switch(calcSpillCost(Hint)) {
489 definePhysReg(MI, Hint, regFree);
492 return assignVirtToPhysReg(LRE, Hint);
493 case spillImpossible:
498 TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
499 TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
501 // First try to find a completely free register.
502 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
503 unsigned PhysReg = *I;
504 if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg) &&
505 Allocatable.test(PhysReg))
506 return assignVirtToPhysReg(LRE, PhysReg);
509 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
510 << RC->getName() << "\n");
512 unsigned BestReg = 0, BestCost = spillImpossible;
513 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
514 if (!Allocatable.test(*I))
516 unsigned Cost = calcSpillCost(*I);
517 // Cost is 0 when all aliases are already disabled.
519 return assignVirtToPhysReg(LRE, *I);
521 BestReg = *I, BestCost = Cost;
525 definePhysReg(MI, BestReg, regFree);
526 return assignVirtToPhysReg(LRE, BestReg);
529 // Nothing we can do.
531 raw_string_ostream Msg(msg);
532 Msg << "Ran out of registers during register allocation!";
533 if (MI->isInlineAsm()) {
534 Msg << "\nPlease check your inline asm statement for "
535 << "invalid constraints:\n";
538 report_fatal_error(Msg.str());
541 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
542 RAFast::LiveRegMap::iterator
543 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
544 unsigned VirtReg, unsigned Hint) {
545 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
546 "Not a virtual register");
547 LiveRegMap::iterator LRI;
549 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
550 LiveReg &LR = LRI->second;
552 // If there is no hint, peek at the only use of this register.
553 if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
554 MRI->hasOneNonDBGUse(VirtReg)) {
555 const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
556 // It's a copy, use the destination register as a hint.
557 if (UseMI.isCopyLike())
558 Hint = UseMI.getOperand(0).getReg();
560 allocVirtReg(MI, *LRI, Hint);
561 } else if (LR.LastUse) {
562 // Redefining a live register - kill at the last use, unless it is this
563 // instruction defining VirtReg multiple times.
564 if (LR.LastUse != MI || LR.LastUse->getOperand(LR.LastOpNum).isUse())
567 assert(LR.PhysReg && "Register not assigned");
569 LR.LastOpNum = OpNum;
571 UsedInInstr.set(LR.PhysReg);
575 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
576 RAFast::LiveRegMap::iterator
577 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
578 unsigned VirtReg, unsigned Hint) {
579 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
580 "Not a virtual register");
581 LiveRegMap::iterator LRI;
583 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
584 LiveReg &LR = LRI->second;
585 MachineOperand &MO = MI->getOperand(OpNum);
587 allocVirtReg(MI, *LRI, Hint);
588 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
589 int FrameIndex = getStackSpaceFor(VirtReg, RC);
590 DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
591 << PrintReg(LR.PhysReg, TRI) << "\n");
592 TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI);
594 } else if (LR.Dirty) {
595 if (isLastUseOfLocalReg(MO)) {
596 DEBUG(dbgs() << "Killing last use: " << MO << "\n");
601 } else if (MO.isKill()) {
602 DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
604 } else if (MO.isDead()) {
605 DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
608 } else if (MO.isKill()) {
609 // We must remove kill flags from uses of reloaded registers because the
610 // register would be killed immediately, and there might be a second use:
611 // %foo = OR %x<kill>, %x
612 // This would cause a second reload of %x into a different register.
613 DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
615 } else if (MO.isDead()) {
616 DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
619 assert(LR.PhysReg && "Register not assigned");
621 LR.LastOpNum = OpNum;
622 UsedInInstr.set(LR.PhysReg);
626 // setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering
627 // subregs. This may invalidate any operand pointers.
628 // Return true if the operand kills its register.
629 bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) {
630 MachineOperand &MO = MI->getOperand(OpNum);
631 if (!MO.getSubReg()) {
633 return MO.isKill() || MO.isDead();
636 // Handle subregister index.
637 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
640 // A kill flag implies killing the full register. Add corresponding super
643 MI->addRegisterKilled(PhysReg, TRI, true);
649 // Handle special instruction operand like early clobbers and tied ops when
650 // there are additional physreg defines.
651 void RAFast::handleThroughOperands(MachineInstr *MI,
652 SmallVectorImpl<unsigned> &VirtDead) {
653 DEBUG(dbgs() << "Scanning for through registers:");
654 SmallSet<unsigned, 8> ThroughRegs;
655 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
656 MachineOperand &MO = MI->getOperand(i);
657 if (!MO.isReg()) continue;
658 unsigned Reg = MO.getReg();
659 if (!TargetRegisterInfo::isVirtualRegister(Reg))
661 if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
662 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
663 if (ThroughRegs.insert(Reg))
664 DEBUG(dbgs() << ' ' << PrintReg(Reg));
668 // If any physreg defines collide with preallocated through registers,
669 // we must spill and reallocate.
670 DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
671 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
672 MachineOperand &MO = MI->getOperand(i);
673 if (!MO.isReg() || !MO.isDef()) continue;
674 unsigned Reg = MO.getReg();
675 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
676 UsedInInstr.set(Reg);
677 if (ThroughRegs.count(PhysRegState[Reg]))
678 definePhysReg(MI, Reg, regFree);
679 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
680 UsedInInstr.set(*AS);
681 if (ThroughRegs.count(PhysRegState[*AS]))
682 definePhysReg(MI, *AS, regFree);
686 SmallVector<unsigned, 8> PartialDefs;
687 DEBUG(dbgs() << "Allocating tied uses and early clobbers.\n");
688 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
689 MachineOperand &MO = MI->getOperand(i);
690 if (!MO.isReg()) continue;
691 unsigned Reg = MO.getReg();
692 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
695 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
696 DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
698 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
699 unsigned PhysReg = LRI->second.PhysReg;
700 setPhysReg(MI, i, PhysReg);
701 // Note: we don't update the def operand yet. That would cause the normal
702 // def-scan to attempt spilling.
703 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
704 DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
705 // Reload the register, but don't assign to the operand just yet.
706 // That would confuse the later phys-def processing pass.
707 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
708 PartialDefs.push_back(LRI->second.PhysReg);
709 } else if (MO.isEarlyClobber()) {
710 // Note: defineVirtReg may invalidate MO.
711 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
712 unsigned PhysReg = LRI->second.PhysReg;
713 if (setPhysReg(MI, i, PhysReg))
714 VirtDead.push_back(Reg);
718 // Restore UsedInInstr to a state usable for allocating normal virtual uses.
720 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
721 MachineOperand &MO = MI->getOperand(i);
722 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
723 unsigned Reg = MO.getReg();
724 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
725 UsedInInstr.set(Reg);
726 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
727 UsedInInstr.set(*AS);
730 // Also mark PartialDefs as used to avoid reallocation.
731 for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
732 UsedInInstr.set(PartialDefs[i]);
735 void RAFast::AllocateBasicBlock() {
736 DEBUG(dbgs() << "\nAllocating " << *MBB);
738 // FIXME: This should probably be added by instruction selection instead?
739 // If the last instruction in the block is a return, make sure to mark it as
740 // using all of the live-out values in the function. Things marked both call
741 // and return are tail calls; do not do this for them. The tail callee need
742 // not take the same registers as input that it produces as output, and there
743 // are dependencies for its input registers elsewhere.
744 if (!MBB->empty() && MBB->back().getDesc().isReturn() &&
745 !MBB->back().getDesc().isCall()) {
746 MachineInstr *Ret = &MBB->back();
748 for (MachineRegisterInfo::liveout_iterator
749 I = MF->getRegInfo().liveout_begin(),
750 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
751 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
752 "Cannot have a live-out virtual register.");
754 // Add live-out registers as implicit uses.
755 Ret->addRegisterKilled(*I, TRI, true);
759 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
760 assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
762 MachineBasicBlock::iterator MII = MBB->begin();
764 // Add live-in registers as live.
765 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
766 E = MBB->livein_end(); I != E; ++I)
767 if (Allocatable.test(*I))
768 definePhysReg(MII, *I, regReserved);
770 SmallVector<unsigned, 8> VirtDead;
771 SmallVector<MachineInstr*, 32> Coalesced;
773 // Otherwise, sequentially allocate each instruction in the MBB.
774 while (MII != MBB->end()) {
775 MachineInstr *MI = MII++;
776 const TargetInstrDesc &TID = MI->getDesc();
778 dbgs() << "\n>> " << *MI << "Regs:";
779 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
780 if (PhysRegState[Reg] == regDisabled) continue;
781 dbgs() << " " << TRI->getName(Reg);
782 switch(PhysRegState[Reg]) {
789 dbgs() << '=' << PrintReg(PhysRegState[Reg]);
790 if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
792 assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
798 // Check that LiveVirtRegs is the inverse.
799 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
800 e = LiveVirtRegs.end(); i != e; ++i) {
801 assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
803 assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
805 assert(PhysRegState[i->second.PhysReg] == i->first &&
810 // Debug values are not allowed to change codegen in any way.
811 if (MI->isDebugValue()) {
812 bool ScanDbgValue = true;
813 while (ScanDbgValue) {
814 ScanDbgValue = false;
815 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
816 MachineOperand &MO = MI->getOperand(i);
817 if (!MO.isReg()) continue;
818 unsigned Reg = MO.getReg();
819 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
820 LiveDbgValueMap[Reg] = MI;
821 LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
822 if (LRI != LiveVirtRegs.end())
823 setPhysReg(MI, i, LRI->second.PhysReg);
825 int SS = StackSlotForVirtReg[Reg];
827 // We can't allocate a physreg for a DebugValue, sorry!
828 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
832 // Modify DBG_VALUE now that the value is in a spill slot.
833 int64_t Offset = MI->getOperand(1).getImm();
834 const MDNode *MDPtr =
835 MI->getOperand(MI->getNumOperands()-1).getMetadata();
836 DebugLoc DL = MI->getDebugLoc();
837 if (MachineInstr *NewDV =
838 TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {
839 DEBUG(dbgs() << "Modifying debug info due to spill:" <<
841 MachineBasicBlock *MBB = MI->getParent();
842 MBB->insert(MBB->erase(MI), NewDV);
843 // Scan NewDV operands from the beginning.
848 // We can't allocate a physreg for a DebugValue; sorry!
849 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
860 // If this is a copy, we may be able to coalesce.
861 unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
863 CopyDst = MI->getOperand(0).getReg();
864 CopySrc = MI->getOperand(1).getReg();
865 CopyDstSub = MI->getOperand(0).getSubReg();
866 CopySrcSub = MI->getOperand(1).getSubReg();
869 // Track registers used by instruction.
873 // Mark physreg uses and early clobbers as used.
874 // Find the end of the virtreg operands
875 unsigned VirtOpEnd = 0;
876 bool hasTiedOps = false;
877 bool hasEarlyClobbers = false;
878 bool hasPartialRedefs = false;
879 bool hasPhysDefs = false;
880 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
881 MachineOperand &MO = MI->getOperand(i);
882 if (!MO.isReg()) continue;
883 unsigned Reg = MO.getReg();
885 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
888 hasTiedOps = hasTiedOps ||
889 TID.getOperandConstraint(i, TOI::TIED_TO) != -1;
891 if (MO.isEarlyClobber())
892 hasEarlyClobbers = true;
893 if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
894 hasPartialRedefs = true;
898 if (!Allocatable.test(Reg)) continue;
901 } else if (MO.isEarlyClobber()) {
902 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
903 regFree : regReserved);
904 hasEarlyClobbers = true;
909 // The instruction may have virtual register operands that must be allocated
910 // the same register at use-time and def-time: early clobbers and tied
911 // operands. If there are also physical defs, these registers must avoid
912 // both physical defs and uses, making them more constrained than normal
914 // Similarly, if there are multiple defs and tied operands, we must make
915 // sure the same register is allocated to uses and defs.
916 // We didn't detect inline asm tied operands above, so just make this extra
917 // pass for all inline asm.
918 if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
919 (hasTiedOps && (hasPhysDefs || TID.getNumDefs() > 1))) {
920 handleThroughOperands(MI, VirtDead);
921 // Don't attempt coalescing when we have funny stuff going on.
923 // Pretend we have early clobbers so the use operands get marked below.
924 // This is not necessary for the common case of a single tied use.
925 hasEarlyClobbers = true;
929 // Allocate virtreg uses.
930 for (unsigned i = 0; i != VirtOpEnd; ++i) {
931 MachineOperand &MO = MI->getOperand(i);
932 if (!MO.isReg()) continue;
933 unsigned Reg = MO.getReg();
934 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
936 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
937 unsigned PhysReg = LRI->second.PhysReg;
938 CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
939 if (setPhysReg(MI, i, PhysReg))
944 MRI->addPhysRegsUsed(UsedInInstr);
946 // Track registers defined by instruction - early clobbers and tied uses at
949 if (hasEarlyClobbers) {
950 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
951 MachineOperand &MO = MI->getOperand(i);
952 if (!MO.isReg()) continue;
953 unsigned Reg = MO.getReg();
954 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
955 // Look for physreg defs and tied uses.
956 if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue;
957 UsedInInstr.set(Reg);
958 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
959 UsedInInstr.set(*AS);
963 unsigned DefOpEnd = MI->getNumOperands();
965 // Spill all virtregs before a call. This serves two purposes: 1. If an
966 // exception is thrown, the landing pad is going to expect to find
967 // registers in their spill slots, and 2. we don't have to wade through
968 // all the <imp-def> operands on the call instruction.
969 DefOpEnd = VirtOpEnd;
970 DEBUG(dbgs() << " Spilling remaining registers before call.\n");
973 // The imp-defs are skipped below, but we still need to mark those
974 // registers as used by the function.
975 SkippedInstrs.insert(&TID);
979 // Allocate defs and collect dead defs.
980 for (unsigned i = 0; i != DefOpEnd; ++i) {
981 MachineOperand &MO = MI->getOperand(i);
982 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
984 unsigned Reg = MO.getReg();
986 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
987 if (!Allocatable.test(Reg)) continue;
988 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
989 regFree : regReserved);
992 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
993 unsigned PhysReg = LRI->second.PhysReg;
994 if (setPhysReg(MI, i, PhysReg)) {
995 VirtDead.push_back(Reg);
996 CopyDst = 0; // cancel coalescing;
998 CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
1001 // Kill dead defs after the scan to ensure that multiple defs of the same
1002 // register are allocated identically. We didn't need to do this for uses
1003 // because we are crerating our own kill flags, and they are always at the
1005 for (unsigned i = 0, e = VirtDead.size(); i != e; ++i)
1006 killVirtReg(VirtDead[i]);
1009 MRI->addPhysRegsUsed(UsedInInstr);
1011 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
1012 DEBUG(dbgs() << "-- coalescing: " << *MI);
1013 Coalesced.push_back(MI);
1015 DEBUG(dbgs() << "<< " << *MI);
1019 // Spill all physical registers holding virtual registers now.
1020 DEBUG(dbgs() << "Spilling live registers at end of block.\n");
1021 spillAll(MBB->getFirstTerminator());
1023 // Erase all the coalesced copies. We are delaying it until now because
1024 // LiveVirtRegs might refer to the instrs.
1025 for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
1026 MBB->erase(Coalesced[i]);
1027 NumCopies += Coalesced.size();
1032 /// runOnMachineFunction - Register allocate the whole function
1034 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
1035 DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
1036 << "********** Function: "
1037 << ((Value*)Fn.getFunction())->getName() << '\n');
1039 MRI = &MF->getRegInfo();
1040 TM = &Fn.getTarget();
1041 TRI = TM->getRegisterInfo();
1042 TII = TM->getInstrInfo();
1044 UsedInInstr.resize(TRI->getNumRegs());
1045 Allocatable = TRI->getAllocatableSet(*MF);
1047 // initialize the virtual->physical register map to have a 'null'
1048 // mapping for all virtual registers
1049 StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
1051 // Loop over all of the basic blocks, eliminating virtual register references
1052 for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
1053 MBBi != MBBe; ++MBBi) {
1055 AllocateBasicBlock();
1058 // Make sure the set of used physregs is closed under subreg operations.
1059 MRI->closePhysRegsUsed(*TRI);
1061 // Add the clobber lists for all the instructions we skipped earlier.
1062 for (SmallPtrSet<const TargetInstrDesc*, 4>::const_iterator
1063 I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I)
1064 if (const unsigned *Defs = (*I)->getImplicitDefs())
1066 MRI->setPhysRegUsed(*Defs++);
1068 SkippedInstrs.clear();
1069 StackSlotForVirtReg.clear();
1070 LiveDbgValueMap.clear();
1074 FunctionPass *llvm::createFastRegisterAllocator() {
1075 return new RAFast();