1 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/SparseSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegAllocRegistry.h"
30 #include "llvm/CodeGen/RegisterClassInfo.h"
31 #include "llvm/IR/BasicBlock.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
41 STATISTIC(NumStores, "Number of stores added");
42 STATISTIC(NumLoads , "Number of loads added");
43 STATISTIC(NumCopies, "Number of copies coalesced");
45 static RegisterRegAlloc
46 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
49 class RAFast : public MachineFunctionPass {
52 RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
53 isBulkSpilling(false) {}
55 const TargetMachine *TM;
57 MachineRegisterInfo *MRI;
58 const TargetRegisterInfo *TRI;
59 const TargetInstrInfo *TII;
60 RegisterClassInfo RegClassInfo;
62 // Basic block currently being allocated.
63 MachineBasicBlock *MBB;
65 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
66 // values are spilled.
67 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
69 // Everything we know about a live virtual register.
71 MachineInstr *LastUse; // Last instr to use reg.
72 unsigned VirtReg; // Virtual register number.
73 unsigned PhysReg; // Currently held here.
74 unsigned short LastOpNum; // OpNum on LastUse.
75 bool Dirty; // Register needs spill.
77 explicit LiveReg(unsigned v)
78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
80 unsigned getSparseSetIndex() const {
81 return TargetRegisterInfo::virtReg2Index(VirtReg);
85 typedef SparseSet<LiveReg> LiveRegMap;
87 // LiveVirtRegs - This map contains entries for each virtual register
88 // that is currently available in a physical register.
89 LiveRegMap LiveVirtRegs;
91 DenseMap<unsigned, SmallVector<MachineInstr *, 4> > LiveDbgValueMap;
93 // RegState - Track the state of a physical register.
95 // A disabled register is not available for allocation, but an alias may
96 // be in use. A register can only be moved out of the disabled state if
97 // all aliases are disabled.
100 // A free register is not currently in use and can be allocated
101 // immediately without checking aliases.
104 // A reserved register has been assigned explicitly (e.g., setting up a
105 // call parameter), and it remains reserved until it is used.
108 // A register state may also be a virtual register number, indication that
109 // the physical register is currently allocated to a virtual register. In
110 // that case, LiveVirtRegs contains the inverse mapping.
113 // PhysRegState - One of the RegState enums, or a virtreg.
114 std::vector<unsigned> PhysRegState;
116 // Set of register units.
117 typedef SparseSet<unsigned> UsedInInstrSet;
119 // Set of register units that are used in the current instruction, and so
120 // cannot be allocated.
121 UsedInInstrSet UsedInInstr;
123 // Mark a physreg as used in this instruction.
124 void markRegUsedInInstr(unsigned PhysReg) {
125 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
126 UsedInInstr.insert(*Units);
129 // Check if a physreg or any of its aliases are used in this instruction.
130 bool isRegUsedInInstr(unsigned PhysReg) const {
131 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
132 if (UsedInInstr.count(*Units))
137 // SkippedInstrs - Descriptors of instructions whose clobber list was
138 // ignored because all registers were spilled. It is still necessary to
139 // mark all the clobbered registers as used by the function.
140 SmallPtrSet<const MCInstrDesc*, 4> SkippedInstrs;
142 // isBulkSpilling - This flag is set when LiveRegMap will be cleared
143 // completely after spilling all live registers. LiveRegMap entries should
150 spillImpossible = ~0u
153 virtual const char *getPassName() const {
154 return "Fast Register Allocator";
157 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
158 AU.setPreservesCFG();
159 MachineFunctionPass::getAnalysisUsage(AU);
163 bool runOnMachineFunction(MachineFunction &Fn);
164 void AllocateBasicBlock();
165 void handleThroughOperands(MachineInstr *MI,
166 SmallVectorImpl<unsigned> &VirtDead);
167 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
168 bool isLastUseOfLocalReg(MachineOperand&);
170 void addKillFlag(const LiveReg&);
171 void killVirtReg(LiveRegMap::iterator);
172 void killVirtReg(unsigned VirtReg);
173 void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
174 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
176 void usePhysReg(MachineOperand&);
177 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
178 unsigned calcSpillCost(unsigned PhysReg) const;
179 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg);
180 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
181 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
183 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
184 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
186 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
187 LiveRegMap::iterator allocVirtReg(MachineInstr *MI, LiveRegMap::iterator,
189 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
190 unsigned VirtReg, unsigned Hint);
191 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
192 unsigned VirtReg, unsigned Hint);
193 void spillAll(MachineBasicBlock::iterator MI);
194 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
199 /// getStackSpaceFor - This allocates space for the specified virtual register
200 /// to be held on the stack.
201 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
202 // Find the location Reg would belong...
203 int SS = StackSlotForVirtReg[VirtReg];
205 return SS; // Already has space allocated?
207 // Allocate a new stack object for this spill location...
208 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
212 StackSlotForVirtReg[VirtReg] = FrameIdx;
216 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
217 /// its virtual register, and it is guaranteed to be a block-local register.
219 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
220 // If the register has ever been spilled or reloaded, we conservatively assume
221 // it is a global register used in multiple blocks.
222 if (StackSlotForVirtReg[MO.getReg()] != -1)
225 // Check that the use/def chain has exactly one operand - MO.
226 MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg());
227 if (&I.getOperand() != &MO)
229 return ++I == MRI->reg_nodbg_end();
232 /// addKillFlag - Set kill flags on last use of a virtual register.
233 void RAFast::addKillFlag(const LiveReg &LR) {
234 if (!LR.LastUse) return;
235 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
236 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
237 if (MO.getReg() == LR.PhysReg)
240 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
244 /// killVirtReg - Mark virtreg as no longer available.
245 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
247 assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
248 "Broken RegState mapping");
249 PhysRegState[LRI->PhysReg] = regFree;
250 // Erase from LiveVirtRegs unless we're spilling in bulk.
252 LiveVirtRegs.erase(LRI);
255 /// killVirtReg - Mark virtreg as no longer available.
256 void RAFast::killVirtReg(unsigned VirtReg) {
257 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
258 "killVirtReg needs a virtual register");
259 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
260 if (LRI != LiveVirtRegs.end())
264 /// spillVirtReg - This method spills the value specified by VirtReg into the
265 /// corresponding stack slot if needed.
266 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
267 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
268 "Spilling a physical register is illegal!");
269 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
270 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
271 spillVirtReg(MI, LRI);
274 /// spillVirtReg - Do the actual work of spilling.
275 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
276 LiveRegMap::iterator LRI) {
278 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
281 // If this physreg is used by the instruction, we want to kill it on the
282 // instruction, not on the spill.
283 bool SpillKill = LR.LastUse != MI;
285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
286 << " in " << PrintReg(LR.PhysReg, TRI));
287 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
288 int FI = getStackSpaceFor(LRI->VirtReg, RC);
289 DEBUG(dbgs() << " to stack slot #" << FI << "\n");
290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
291 ++NumStores; // Update statistics
293 // If this register is used by DBG_VALUE then insert new DBG_VALUE to
294 // identify spilled location as the place to find corresponding variable's
296 SmallVector<MachineInstr *, 4> &LRIDbgValues =
297 LiveDbgValueMap[LRI->VirtReg];
298 for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {
299 MachineInstr *DBG = LRIDbgValues[li];
300 const MDNode *MDPtr = DBG->getOperand(2).getMetadata();
301 int64_t Offset = DBG->getOperand(1).getImm();
303 if (MI == MBB->end()) {
304 // If MI is at basic block end then use last instruction's location.
305 MachineBasicBlock::iterator EI = MI;
306 DL = (--EI)->getDebugLoc();
308 DL = MI->getDebugLoc();
309 MachineBasicBlock *MBB = DBG->getParent();
310 MachineInstr *NewDV =
311 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE))
312 .addFrameIndex(FI).addImm(Offset).addMetadata(MDPtr);
314 DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
316 // Now this register is spilled there is should not be any DBG_VALUE
317 // pointing to this register because they are all pointing to spilled value
319 LRIDbgValues.clear();
321 LR.LastUse = 0; // Don't kill register again
326 /// spillAll - Spill all dirty virtregs without killing them.
327 void RAFast::spillAll(MachineBasicBlock::iterator MI) {
328 if (LiveVirtRegs.empty()) return;
329 isBulkSpilling = true;
330 // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
331 // of spilling here is deterministic, if arbitrary.
332 for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
335 LiveVirtRegs.clear();
336 isBulkSpilling = false;
339 /// usePhysReg - Handle the direct use of a physical register.
340 /// Check that the register is not used by a virtreg.
341 /// Kill the physreg, marking it free.
342 /// This may add implicit kills to MO->getParent() and invalidate MO.
343 void RAFast::usePhysReg(MachineOperand &MO) {
344 unsigned PhysReg = MO.getReg();
345 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
346 "Bad usePhysReg operand");
347 markRegUsedInInstr(PhysReg);
348 switch (PhysRegState[PhysReg]) {
352 PhysRegState[PhysReg] = regFree;
358 // The physreg was allocated to a virtual register. That means the value we
359 // wanted has been clobbered.
360 llvm_unreachable("Instruction uses an allocated register");
363 // Maybe a superregister is reserved?
364 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
365 unsigned Alias = *AI;
366 switch (PhysRegState[Alias]) {
370 assert(TRI->isSuperRegister(PhysReg, Alias) &&
371 "Instruction is not using a subregister of a reserved register");
372 // Leave the superregister in the working set.
373 PhysRegState[Alias] = regFree;
374 MO.getParent()->addRegisterKilled(Alias, TRI, true);
377 if (TRI->isSuperRegister(PhysReg, Alias)) {
378 // Leave the superregister in the working set.
379 MO.getParent()->addRegisterKilled(Alias, TRI, true);
382 // Some other alias was in the working set - clear it.
383 PhysRegState[Alias] = regDisabled;
386 llvm_unreachable("Instruction uses an alias of an allocated register");
390 // All aliases are disabled, bring register into working set.
391 PhysRegState[PhysReg] = regFree;
395 /// definePhysReg - Mark PhysReg as reserved or free after spilling any
396 /// virtregs. This is very similar to defineVirtReg except the physreg is
397 /// reserved instead of allocated.
398 void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
400 markRegUsedInInstr(PhysReg);
401 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
405 spillVirtReg(MI, VirtReg);
409 PhysRegState[PhysReg] = NewState;
413 // This is a disabled register, disable all aliases.
414 PhysRegState[PhysReg] = NewState;
415 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
416 unsigned Alias = *AI;
417 switch (unsigned VirtReg = PhysRegState[Alias]) {
421 spillVirtReg(MI, VirtReg);
425 PhysRegState[Alias] = regDisabled;
426 if (TRI->isSuperRegister(PhysReg, Alias))
434 // calcSpillCost - Return the cost of spilling clearing out PhysReg and
435 // aliases so it is free for allocation.
436 // Returns 0 when PhysReg is free or disabled with all aliases disabled - it
437 // can be allocated directly.
438 // Returns spillImpossible when PhysReg or an alias can't be spilled.
439 unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
440 if (isRegUsedInInstr(PhysReg)) {
441 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n");
442 return spillImpossible;
444 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
450 DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
451 << PrintReg(PhysReg, TRI) << " is reserved already.\n");
452 return spillImpossible;
454 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
455 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
456 return I->Dirty ? spillDirty : spillClean;
460 // This is a disabled register, add up cost of aliases.
461 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n");
463 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
464 unsigned Alias = *AI;
465 switch (unsigned VirtReg = PhysRegState[Alias]) {
472 return spillImpossible;
474 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
475 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
476 Cost += I->Dirty ? spillDirty : spillClean;
485 /// assignVirtToPhysReg - This method updates local state so that we know
486 /// that PhysReg is the proper container for VirtReg now. The physical
487 /// register must not be used for anything else when this is called.
489 void RAFast::assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) {
490 DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
491 << PrintReg(PhysReg, TRI) << "\n");
492 PhysRegState[PhysReg] = LR.VirtReg;
493 assert(!LR.PhysReg && "Already assigned a physreg");
494 LR.PhysReg = PhysReg;
497 RAFast::LiveRegMap::iterator
498 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
499 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
500 assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared");
501 assignVirtToPhysReg(*LRI, PhysReg);
505 /// allocVirtReg - Allocate a physical register for VirtReg.
506 RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI,
507 LiveRegMap::iterator LRI,
509 const unsigned VirtReg = LRI->VirtReg;
511 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
512 "Can only allocate virtual registers");
514 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
516 // Ignore invalid hints.
517 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
518 !RC->contains(Hint) || !MRI->isAllocatable(Hint)))
521 // Take hint when possible.
523 // Ignore the hint if we would have to spill a dirty register.
524 unsigned Cost = calcSpillCost(Hint);
525 if (Cost < spillDirty) {
527 definePhysReg(MI, Hint, regFree);
528 // definePhysReg may kill virtual registers and modify LiveVirtRegs.
529 // That invalidates LRI, so run a new lookup for VirtReg.
530 return assignVirtToPhysReg(VirtReg, Hint);
534 ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
536 // First try to find a completely free register.
537 for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
538 unsigned PhysReg = *I;
539 if (PhysRegState[PhysReg] == regFree && !isRegUsedInInstr(PhysReg)) {
540 assignVirtToPhysReg(*LRI, PhysReg);
545 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
546 << RC->getName() << "\n");
548 unsigned BestReg = 0, BestCost = spillImpossible;
549 for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
550 unsigned Cost = calcSpillCost(*I);
551 DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n");
552 DEBUG(dbgs() << "\tCost: " << Cost << "\n");
553 DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n");
554 // Cost is 0 when all aliases are already disabled.
556 assignVirtToPhysReg(*LRI, *I);
560 BestReg = *I, BestCost = Cost;
564 definePhysReg(MI, BestReg, regFree);
565 // definePhysReg may kill virtual registers and modify LiveVirtRegs.
566 // That invalidates LRI, so run a new lookup for VirtReg.
567 return assignVirtToPhysReg(VirtReg, BestReg);
570 // Nothing we can do. Report an error and keep going with a bad allocation.
571 MI->emitError("ran out of registers during register allocation");
572 definePhysReg(MI, *AO.begin(), regFree);
573 return assignVirtToPhysReg(VirtReg, *AO.begin());
576 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
577 RAFast::LiveRegMap::iterator
578 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
579 unsigned VirtReg, unsigned Hint) {
580 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
581 "Not a virtual register");
582 LiveRegMap::iterator LRI;
584 tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
586 // If there is no hint, peek at the only use of this register.
587 if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
588 MRI->hasOneNonDBGUse(VirtReg)) {
589 const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
590 // It's a copy, use the destination register as a hint.
591 if (UseMI.isCopyLike())
592 Hint = UseMI.getOperand(0).getReg();
594 LRI = allocVirtReg(MI, LRI, Hint);
595 } else if (LRI->LastUse) {
596 // Redefining a live register - kill at the last use, unless it is this
597 // instruction defining VirtReg multiple times.
598 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse())
601 assert(LRI->PhysReg && "Register not assigned");
603 LRI->LastOpNum = OpNum;
605 markRegUsedInInstr(LRI->PhysReg);
609 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
610 RAFast::LiveRegMap::iterator
611 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
612 unsigned VirtReg, unsigned Hint) {
613 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
614 "Not a virtual register");
615 LiveRegMap::iterator LRI;
617 tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
618 MachineOperand &MO = MI->getOperand(OpNum);
620 LRI = allocVirtReg(MI, LRI, Hint);
621 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
622 int FrameIndex = getStackSpaceFor(VirtReg, RC);
623 DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
624 << PrintReg(LRI->PhysReg, TRI) << "\n");
625 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
627 } else if (LRI->Dirty) {
628 if (isLastUseOfLocalReg(MO)) {
629 DEBUG(dbgs() << "Killing last use: " << MO << "\n");
634 } else if (MO.isKill()) {
635 DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
637 } else if (MO.isDead()) {
638 DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
641 } else if (MO.isKill()) {
642 // We must remove kill flags from uses of reloaded registers because the
643 // register would be killed immediately, and there might be a second use:
644 // %foo = OR %x<kill>, %x
645 // This would cause a second reload of %x into a different register.
646 DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
648 } else if (MO.isDead()) {
649 DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
652 assert(LRI->PhysReg && "Register not assigned");
654 LRI->LastOpNum = OpNum;
655 markRegUsedInInstr(LRI->PhysReg);
659 // setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering
660 // subregs. This may invalidate any operand pointers.
661 // Return true if the operand kills its register.
662 bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) {
663 MachineOperand &MO = MI->getOperand(OpNum);
664 bool Dead = MO.isDead();
665 if (!MO.getSubReg()) {
667 return MO.isKill() || Dead;
670 // Handle subregister index.
671 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
674 // A kill flag implies killing the full register. Add corresponding super
677 MI->addRegisterKilled(PhysReg, TRI, true);
681 // A <def,read-undef> of a sub-register requires an implicit def of the full
683 if (MO.isDef() && MO.isUndef())
684 MI->addRegisterDefined(PhysReg, TRI);
689 // Handle special instruction operand like early clobbers and tied ops when
690 // there are additional physreg defines.
691 void RAFast::handleThroughOperands(MachineInstr *MI,
692 SmallVectorImpl<unsigned> &VirtDead) {
693 DEBUG(dbgs() << "Scanning for through registers:");
694 SmallSet<unsigned, 8> ThroughRegs;
695 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
696 MachineOperand &MO = MI->getOperand(i);
697 if (!MO.isReg()) continue;
698 unsigned Reg = MO.getReg();
699 if (!TargetRegisterInfo::isVirtualRegister(Reg))
701 if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
702 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
703 if (ThroughRegs.insert(Reg))
704 DEBUG(dbgs() << ' ' << PrintReg(Reg));
708 // If any physreg defines collide with preallocated through registers,
709 // we must spill and reallocate.
710 DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
711 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
712 MachineOperand &MO = MI->getOperand(i);
713 if (!MO.isReg() || !MO.isDef()) continue;
714 unsigned Reg = MO.getReg();
715 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
716 markRegUsedInInstr(Reg);
717 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
718 if (ThroughRegs.count(PhysRegState[*AI]))
719 definePhysReg(MI, *AI, regFree);
723 SmallVector<unsigned, 8> PartialDefs;
724 DEBUG(dbgs() << "Allocating tied uses.\n");
725 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
726 MachineOperand &MO = MI->getOperand(i);
727 if (!MO.isReg()) continue;
728 unsigned Reg = MO.getReg();
729 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
732 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
733 DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
735 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
736 unsigned PhysReg = LRI->PhysReg;
737 setPhysReg(MI, i, PhysReg);
738 // Note: we don't update the def operand yet. That would cause the normal
739 // def-scan to attempt spilling.
740 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
741 DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
742 // Reload the register, but don't assign to the operand just yet.
743 // That would confuse the later phys-def processing pass.
744 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
745 PartialDefs.push_back(LRI->PhysReg);
749 DEBUG(dbgs() << "Allocating early clobbers.\n");
750 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
751 MachineOperand &MO = MI->getOperand(i);
752 if (!MO.isReg()) continue;
753 unsigned Reg = MO.getReg();
754 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
755 if (!MO.isEarlyClobber())
757 // Note: defineVirtReg may invalidate MO.
758 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
759 unsigned PhysReg = LRI->PhysReg;
760 if (setPhysReg(MI, i, PhysReg))
761 VirtDead.push_back(Reg);
764 // Restore UsedInInstr to a state usable for allocating normal virtual uses.
766 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
767 MachineOperand &MO = MI->getOperand(i);
768 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
769 unsigned Reg = MO.getReg();
770 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
771 DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI)
772 << " as used in instr\n");
773 markRegUsedInInstr(Reg);
776 // Also mark PartialDefs as used to avoid reallocation.
777 for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
778 markRegUsedInInstr(PartialDefs[i]);
781 void RAFast::AllocateBasicBlock() {
782 DEBUG(dbgs() << "\nAllocating " << *MBB);
784 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
785 assert(LiveVirtRegs.empty() && "Mapping not cleared from last block?");
787 MachineBasicBlock::iterator MII = MBB->begin();
789 // Add live-in registers as live.
790 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
791 E = MBB->livein_end(); I != E; ++I)
792 if (MRI->isAllocatable(*I))
793 definePhysReg(MII, *I, regReserved);
795 SmallVector<unsigned, 8> VirtDead;
796 SmallVector<MachineInstr*, 32> Coalesced;
798 // Otherwise, sequentially allocate each instruction in the MBB.
799 while (MII != MBB->end()) {
800 MachineInstr *MI = MII++;
801 const MCInstrDesc &MCID = MI->getDesc();
803 dbgs() << "\n>> " << *MI << "Regs:";
804 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
805 if (PhysRegState[Reg] == regDisabled) continue;
806 dbgs() << " " << TRI->getName(Reg);
807 switch(PhysRegState[Reg]) {
814 dbgs() << '=' << PrintReg(PhysRegState[Reg]);
815 LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]);
816 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
819 assert(I->PhysReg == Reg && "Bad inverse map");
825 // Check that LiveVirtRegs is the inverse.
826 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
827 e = LiveVirtRegs.end(); i != e; ++i) {
828 assert(TargetRegisterInfo::isVirtualRegister(i->VirtReg) &&
830 assert(TargetRegisterInfo::isPhysicalRegister(i->PhysReg) &&
832 assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");
836 // Debug values are not allowed to change codegen in any way.
837 if (MI->isDebugValue()) {
838 bool ScanDbgValue = true;
839 while (ScanDbgValue) {
840 ScanDbgValue = false;
841 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
842 MachineOperand &MO = MI->getOperand(i);
843 if (!MO.isReg()) continue;
844 unsigned Reg = MO.getReg();
845 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
846 LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
847 if (LRI != LiveVirtRegs.end())
848 setPhysReg(MI, i, LRI->PhysReg);
850 int SS = StackSlotForVirtReg[Reg];
852 // We can't allocate a physreg for a DebugValue, sorry!
853 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
857 // Modify DBG_VALUE now that the value is in a spill slot.
858 int64_t Offset = MI->getOperand(1).getImm();
859 const MDNode *MDPtr =
860 MI->getOperand(MI->getNumOperands()-1).getMetadata();
861 DebugLoc DL = MI->getDebugLoc();
862 MachineBasicBlock *MBB = MI->getParent();
863 MachineInstr *NewDV = BuildMI(*MBB, MBB->erase(MI), DL,
864 TII->get(TargetOpcode::DBG_VALUE))
865 .addFrameIndex(SS).addImm(Offset).addMetadata(MDPtr);
866 DEBUG(dbgs() << "Modifying debug info due to spill:"
868 // Scan NewDV operands from the beginning.
874 LiveDbgValueMap[Reg].push_back(MI);
881 // If this is a copy, we may be able to coalesce.
882 unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
884 CopyDst = MI->getOperand(0).getReg();
885 CopySrc = MI->getOperand(1).getReg();
886 CopyDstSub = MI->getOperand(0).getSubReg();
887 CopySrcSub = MI->getOperand(1).getSubReg();
890 // Track registers used by instruction.
894 // Mark physreg uses and early clobbers as used.
895 // Find the end of the virtreg operands
896 unsigned VirtOpEnd = 0;
897 bool hasTiedOps = false;
898 bool hasEarlyClobbers = false;
899 bool hasPartialRedefs = false;
900 bool hasPhysDefs = false;
901 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
902 MachineOperand &MO = MI->getOperand(i);
903 // Make sure MRI knows about registers clobbered by regmasks.
904 if (MO.isRegMask()) {
905 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
908 if (!MO.isReg()) continue;
909 unsigned Reg = MO.getReg();
911 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
914 hasTiedOps = hasTiedOps ||
915 MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1;
917 if (MO.isEarlyClobber())
918 hasEarlyClobbers = true;
919 if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
920 hasPartialRedefs = true;
924 if (!MRI->isAllocatable(Reg)) continue;
927 } else if (MO.isEarlyClobber()) {
928 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
929 regFree : regReserved);
930 hasEarlyClobbers = true;
935 // The instruction may have virtual register operands that must be allocated
936 // the same register at use-time and def-time: early clobbers and tied
937 // operands. If there are also physical defs, these registers must avoid
938 // both physical defs and uses, making them more constrained than normal
940 // Similarly, if there are multiple defs and tied operands, we must make
941 // sure the same register is allocated to uses and defs.
942 // We didn't detect inline asm tied operands above, so just make this extra
943 // pass for all inline asm.
944 if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
945 (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) {
946 handleThroughOperands(MI, VirtDead);
947 // Don't attempt coalescing when we have funny stuff going on.
949 // Pretend we have early clobbers so the use operands get marked below.
950 // This is not necessary for the common case of a single tied use.
951 hasEarlyClobbers = true;
955 // Allocate virtreg uses.
956 for (unsigned i = 0; i != VirtOpEnd; ++i) {
957 MachineOperand &MO = MI->getOperand(i);
958 if (!MO.isReg()) continue;
959 unsigned Reg = MO.getReg();
960 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
962 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
963 unsigned PhysReg = LRI->PhysReg;
964 CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
965 if (setPhysReg(MI, i, PhysReg))
970 for (UsedInInstrSet::iterator
971 I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I)
972 MRI->setRegUnitUsed(*I);
974 // Track registers defined by instruction - early clobbers and tied uses at
977 if (hasEarlyClobbers) {
978 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
979 MachineOperand &MO = MI->getOperand(i);
980 if (!MO.isReg()) continue;
981 unsigned Reg = MO.getReg();
982 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
983 // Look for physreg defs and tied uses.
984 if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue;
985 markRegUsedInInstr(Reg);
989 unsigned DefOpEnd = MI->getNumOperands();
991 // Spill all virtregs before a call. This serves two purposes: 1. If an
992 // exception is thrown, the landing pad is going to expect to find
993 // registers in their spill slots, and 2. we don't have to wade through
994 // all the <imp-def> operands on the call instruction.
995 DefOpEnd = VirtOpEnd;
996 DEBUG(dbgs() << " Spilling remaining registers before call.\n");
999 // The imp-defs are skipped below, but we still need to mark those
1000 // registers as used by the function.
1001 SkippedInstrs.insert(&MCID);
1005 // Allocate defs and collect dead defs.
1006 for (unsigned i = 0; i != DefOpEnd; ++i) {
1007 MachineOperand &MO = MI->getOperand(i);
1008 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
1010 unsigned Reg = MO.getReg();
1012 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1013 if (!MRI->isAllocatable(Reg)) continue;
1014 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
1015 regFree : regReserved);
1018 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
1019 unsigned PhysReg = LRI->PhysReg;
1020 if (setPhysReg(MI, i, PhysReg)) {
1021 VirtDead.push_back(Reg);
1022 CopyDst = 0; // cancel coalescing;
1024 CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
1027 // Kill dead defs after the scan to ensure that multiple defs of the same
1028 // register are allocated identically. We didn't need to do this for uses
1029 // because we are crerating our own kill flags, and they are always at the
1031 for (unsigned i = 0, e = VirtDead.size(); i != e; ++i)
1032 killVirtReg(VirtDead[i]);
1035 for (UsedInInstrSet::iterator
1036 I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I)
1037 MRI->setRegUnitUsed(*I);
1039 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
1040 DEBUG(dbgs() << "-- coalescing: " << *MI);
1041 Coalesced.push_back(MI);
1043 DEBUG(dbgs() << "<< " << *MI);
1047 // Spill all physical registers holding virtual registers now.
1048 DEBUG(dbgs() << "Spilling live registers at end of block.\n");
1049 spillAll(MBB->getFirstTerminator());
1051 // Erase all the coalesced copies. We are delaying it until now because
1052 // LiveVirtRegs might refer to the instrs.
1053 for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
1054 MBB->erase(Coalesced[i]);
1055 NumCopies += Coalesced.size();
1060 /// runOnMachineFunction - Register allocate the whole function
1062 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
1063 DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
1064 << "********** Function: " << Fn.getName() << '\n');
1066 MRI = &MF->getRegInfo();
1067 TM = &Fn.getTarget();
1068 TRI = TM->getRegisterInfo();
1069 TII = TM->getInstrInfo();
1070 MRI->freezeReservedRegs(Fn);
1071 RegClassInfo.runOnMachineFunction(Fn);
1072 UsedInInstr.clear();
1073 UsedInInstr.setUniverse(TRI->getNumRegUnits());
1075 assert(!MRI->isSSA() && "regalloc requires leaving SSA");
1077 // initialize the virtual->physical register map to have a 'null'
1078 // mapping for all virtual registers
1079 StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
1080 LiveVirtRegs.setUniverse(MRI->getNumVirtRegs());
1082 // Loop over all of the basic blocks, eliminating virtual register references
1083 for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
1084 MBBi != MBBe; ++MBBi) {
1086 AllocateBasicBlock();
1089 // Add the clobber lists for all the instructions we skipped earlier.
1090 for (SmallPtrSet<const MCInstrDesc*, 4>::const_iterator
1091 I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I)
1092 if (const uint16_t *Defs = (*I)->getImplicitDefs())
1094 MRI->setPhysRegUsed(*Defs++);
1096 // All machine operands and other references to virtual registers have been
1097 // replaced. Remove the virtual registers.
1098 MRI->clearVirtRegs();
1100 SkippedInstrs.clear();
1101 StackSlotForVirtReg.clear();
1102 LiveDbgValueMap.clear();
1106 FunctionPass *llvm::createFastRegisterAllocator() {
1107 return new RAFast();