1 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/IndexedMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(NumStores, "Number of stores added");
39 STATISTIC(NumLoads , "Number of loads added");
41 static RegisterRegAlloc
42 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
45 class RAFast : public MachineFunctionPass {
48 RAFast() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1),
49 atEndOfBlock(false) {}
51 const TargetMachine *TM;
53 MachineRegisterInfo *MRI;
54 const TargetRegisterInfo *TRI;
55 const TargetInstrInfo *TII;
57 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
58 // values are spilled.
59 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
61 // Everything we know about a live virtual register.
63 MachineInstr *LastUse; // Last instr to use reg.
64 unsigned PhysReg; // Currently held here.
65 unsigned short LastOpNum; // OpNum on LastUse.
66 bool Dirty; // Register needs spill.
68 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
70 assert(p && "Don't create LiveRegs without a PhysReg");
74 typedef DenseMap<unsigned, LiveReg> LiveRegMap;
76 // LiveVirtRegs - This map contains entries for each virtual register
77 // that is currently available in a physical register.
78 LiveRegMap LiveVirtRegs;
80 // RegState - Track the state of a physical register.
82 // A disabled register is not available for allocation, but an alias may
83 // be in use. A register can only be moved out of the disabled state if
84 // all aliases are disabled.
87 // A free register is not currently in use and can be allocated
88 // immediately without checking aliases.
91 // A reserved register has been assigned expolicitly (e.g., setting up a
92 // call parameter), and it remains reserved until it is used.
95 // A register state may also be a virtual register number, indication that
96 // the physical register is currently allocated to a virtual register. In
97 // that case, LiveVirtRegs contains the inverse mapping.
100 // PhysRegState - One of the RegState enums, or a virtreg.
101 std::vector<unsigned> PhysRegState;
103 // UsedInInstr - BitVector of physregs that are used in the current
104 // instruction, and so cannot be allocated.
105 BitVector UsedInInstr;
107 // ReservedRegs - vector of reserved physical registers.
108 BitVector ReservedRegs;
110 // atEndOfBlock - This flag is set after allocating all instructions in a
111 // block, before emitting final spills. When it is set, LiveRegMap is no
112 // longer updated properly sonce it will be cleared anyway.
116 virtual const char *getPassName() const {
117 return "Fast Register Allocator";
120 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
121 AU.setPreservesCFG();
122 AU.addRequiredID(PHIEliminationID);
123 AU.addRequiredID(TwoAddressInstructionPassID);
124 MachineFunctionPass::getAnalysisUsage(AU);
128 bool runOnMachineFunction(MachineFunction &Fn);
129 void AllocateBasicBlock(MachineBasicBlock &MBB);
130 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
131 void addKillFlag(LiveRegMap::iterator i);
132 void killVirtReg(LiveRegMap::iterator i);
133 void killVirtReg(unsigned VirtReg);
134 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
135 LiveRegMap::iterator i, bool isKill);
136 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
137 unsigned VirtReg, bool isKill);
138 void killPhysReg(unsigned PhysReg);
139 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
140 unsigned PhysReg, bool isKill);
141 LiveRegMap::iterator assignVirtToPhysReg(unsigned VirtReg,
143 LiveRegMap::iterator allocVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
144 unsigned VirtReg, unsigned Hint);
145 unsigned defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
146 unsigned OpNum, unsigned VirtReg, unsigned Hint);
147 unsigned reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
148 unsigned OpNum, unsigned VirtReg, unsigned Hint);
149 void reservePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
151 void spillAll(MachineBasicBlock &MBB, MachineInstr *MI);
152 void setPhysReg(MachineOperand &MO, unsigned PhysReg);
157 /// getStackSpaceFor - This allocates space for the specified virtual register
158 /// to be held on the stack.
159 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
160 // Find the location Reg would belong...
161 int SS = StackSlotForVirtReg[VirtReg];
163 return SS; // Already has space allocated?
165 // Allocate a new stack object for this spill location...
166 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
170 StackSlotForVirtReg[VirtReg] = FrameIdx;
174 /// addKillFlag - Set kill flags on last use of a virtual register.
175 void RAFast::addKillFlag(LiveRegMap::iterator lri) {
176 assert(lri != LiveVirtRegs.end() && "Killing unmapped virtual register");
177 const LiveReg &LR = lri->second;
179 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
182 else if (!LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum))
187 /// killVirtReg - Mark virtreg as no longer available.
188 void RAFast::killVirtReg(LiveRegMap::iterator lri) {
190 const LiveReg &LR = lri->second;
191 assert(PhysRegState[LR.PhysReg] == lri->first && "Broken RegState mapping");
192 PhysRegState[LR.PhysReg] = regFree;
193 // Erase from LiveVirtRegs unless we're at the end of the block when
194 // everything will be bulk erased.
196 LiveVirtRegs.erase(lri);
199 /// killVirtReg - Mark virtreg as no longer available.
200 void RAFast::killVirtReg(unsigned VirtReg) {
201 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
202 "killVirtReg needs a virtual register");
203 LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
204 if (lri != LiveVirtRegs.end())
208 /// spillVirtReg - This method spills the value specified by VirtReg into the
209 /// corresponding stack slot if needed. If isKill is set, the register is also
211 void RAFast::spillVirtReg(MachineBasicBlock &MBB,
212 MachineBasicBlock::iterator MI,
213 unsigned VirtReg, bool isKill) {
214 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
215 "Spilling a physical register is illegal!");
216 LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
217 assert(lri != LiveVirtRegs.end() && "Spilling unmapped virtual register");
218 spillVirtReg(MBB, MI, lri, isKill);
221 /// spillVirtReg - Do the actual work of spilling.
222 void RAFast::spillVirtReg(MachineBasicBlock &MBB,
223 MachineBasicBlock::iterator MI,
224 LiveRegMap::iterator lri, bool isKill) {
225 LiveReg &LR = lri->second;
226 assert(PhysRegState[LR.PhysReg] == lri->first && "Broken RegState mapping");
228 // If this physreg is used by the instruction, we want to kill it on the
229 // instruction, not on the spill.
230 bool spillKill = isKill && LR.LastUse != MI;
234 DEBUG(dbgs() << "Spilling %reg" << lri->first
235 << " in " << TRI->getName(LR.PhysReg));
236 const TargetRegisterClass *RC = MRI->getRegClass(lri->first);
237 int FrameIndex = getStackSpaceFor(lri->first, RC);
238 DEBUG(dbgs() << " to stack slot #" << FrameIndex << "\n");
239 TII->storeRegToStackSlot(MBB, MI, LR.PhysReg, spillKill,
240 FrameIndex, RC, TRI);
241 ++NumStores; // Update statistics
244 LR.LastUse = 0; // Don't kill register again
246 MachineInstr *Spill = llvm::prior(MI);
248 LR.LastOpNum = Spill->findRegisterUseOperandIdx(LR.PhysReg);
256 /// spillAll - Spill all dirty virtregs without killing them.
257 void RAFast::spillAll(MachineBasicBlock &MBB, MachineInstr *MI) {
258 SmallVector<unsigned, 16> Dirty;
259 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
260 e = LiveVirtRegs.end(); i != e; ++i)
262 Dirty.push_back(i->first);
263 for (unsigned i = 0, e = Dirty.size(); i != e; ++i)
264 spillVirtReg(MBB, MI, Dirty[i], false);
267 /// killPhysReg - Kill any virtual register aliased by PhysReg.
268 void RAFast::killPhysReg(unsigned PhysReg) {
269 // Fast path for the normal case.
270 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
276 PhysRegState[PhysReg] = regFree;
279 killVirtReg(VirtReg);
283 // This is a disabled register, we have to check aliases.
284 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
285 unsigned Alias = *AS; ++AS) {
286 switch (unsigned VirtReg = PhysRegState[Alias]) {
291 PhysRegState[Alias] = regFree;
294 killVirtReg(VirtReg);
300 /// spillPhysReg - Spill any dirty virtual registers that aliases PhysReg. If
301 /// isKill is set, they are also killed.
302 void RAFast::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
303 unsigned PhysReg, bool isKill) {
304 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
311 PhysRegState[PhysReg] = regFree;
314 spillVirtReg(MBB, MI, VirtReg, isKill);
318 // This is a disabled register, we have to check aliases.
319 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
320 unsigned Alias = *AS; ++AS) {
321 switch (unsigned VirtReg = PhysRegState[Alias]) {
327 PhysRegState[Alias] = regFree;
330 spillVirtReg(MBB, MI, VirtReg, isKill);
336 /// assignVirtToPhysReg - This method updates local state so that we know
337 /// that PhysReg is the proper container for VirtReg now. The physical
338 /// register must not be used for anything else when this is called.
340 RAFast::LiveRegMap::iterator
341 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
342 DEBUG(dbgs() << "Assigning %reg" << VirtReg << " to "
343 << TRI->getName(PhysReg) << "\n");
344 PhysRegState[PhysReg] = VirtReg;
345 return LiveVirtRegs.insert(std::make_pair(VirtReg, PhysReg)).first;
348 /// allocVirtReg - Allocate a physical register for VirtReg.
349 RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
353 const unsigned spillCost = 100;
354 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
355 "Can only allocate virtual registers");
357 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
358 TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
359 TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
361 // Ignore invalid hints.
362 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
363 !RC->contains(Hint) || UsedInInstr.test(Hint)))
366 // If there is no hint, peek at the first use of this register.
367 if (!Hint && !MRI->use_nodbg_empty(VirtReg)) {
368 MachineInstr &MI = *MRI->use_nodbg_begin(VirtReg);
369 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
370 // Copy to physreg -> use physreg as hint.
371 if (TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
372 SrcReg == VirtReg && TargetRegisterInfo::isPhysicalRegister(DstReg) &&
373 RC->contains(DstReg) && !UsedInInstr.test(DstReg)) {
375 DEBUG(dbgs() << "%reg" << VirtReg << " gets hint from " << MI);
379 // Take hint when possible.
381 assert(RC->contains(Hint) && !UsedInInstr.test(Hint) &&
382 "Invalid hint should have been cleared");
383 switch(PhysRegState[Hint]) {
388 spillVirtReg(MBB, MI, PhysRegState[Hint], true);
391 return assignVirtToPhysReg(VirtReg, Hint);
395 // First try to find a completely free register.
396 unsigned BestCost = 0, BestReg = 0;
397 bool hasDisabled = false;
398 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
399 unsigned PhysReg = *I;
400 switch(PhysRegState[PhysReg]) {
406 if (!UsedInInstr.test(PhysReg))
407 return assignVirtToPhysReg(VirtReg, PhysReg);
410 // Grab the first spillable register we meet.
411 if (!BestReg && !UsedInInstr.test(PhysReg))
412 BestReg = PhysReg, BestCost = spillCost;
417 DEBUG(dbgs() << "Allocating %reg" << VirtReg << " from " << RC->getName()
418 << " candidate=" << TRI->getName(BestReg) << "\n");
420 // Try to extend the working set for RC if there were any disabled registers.
421 if (hasDisabled && (!BestReg || BestCost >= spillCost)) {
422 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
423 unsigned PhysReg = *I;
424 if (PhysRegState[PhysReg] != regDisabled || UsedInInstr.test(PhysReg))
427 // Calculate the cost of bringing PhysReg into the working set.
429 bool Impossible = false;
430 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
431 unsigned Alias = *AS; ++AS) {
432 if (UsedInInstr.test(Alias)) {
436 switch (PhysRegState[Alias]) {
450 if (Impossible) continue;
451 DEBUG(dbgs() << "- candidate " << TRI->getName(PhysReg)
452 << " cost=" << Cost << "\n");
453 if (!BestReg || Cost < BestCost) {
456 if (Cost < spillCost) break;
462 // BestCost is 0 when all aliases are already disabled.
464 if (PhysRegState[BestReg] != regDisabled)
465 spillVirtReg(MBB, MI, PhysRegState[BestReg], true);
467 // Make sure all aliases are disabled.
468 for (const unsigned *AS = TRI->getAliasSet(BestReg);
469 unsigned Alias = *AS; ++AS) {
470 switch (PhysRegState[Alias]) {
474 PhysRegState[Alias] = regDisabled;
477 spillVirtReg(MBB, MI, PhysRegState[Alias], true);
478 PhysRegState[Alias] = regDisabled;
484 return assignVirtToPhysReg(VirtReg, BestReg);
487 // Nothing we can do.
489 raw_string_ostream Msg(msg);
490 Msg << "Ran out of registers during register allocation!";
491 if (MI->isInlineAsm()) {
492 Msg << "\nPlease check your inline asm statement for "
493 << "invalid constraints:\n";
496 report_fatal_error(Msg.str());
497 return LiveVirtRegs.end();
500 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
501 unsigned RAFast::defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
502 unsigned OpNum, unsigned VirtReg, unsigned Hint) {
503 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
504 "Not a virtual register");
505 LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
506 if (lri == LiveVirtRegs.end())
507 lri = allocVirtReg(MBB, MI, VirtReg, Hint);
509 addKillFlag(lri); // Kill before redefine.
510 LiveReg &LR = lri->second;
512 LR.LastOpNum = OpNum;
514 UsedInInstr.set(LR.PhysReg);
518 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
519 unsigned RAFast::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
520 unsigned OpNum, unsigned VirtReg, unsigned Hint) {
521 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
522 "Not a virtual register");
523 LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
524 if (lri == LiveVirtRegs.end()) {
525 lri = allocVirtReg(MBB, MI, VirtReg, Hint);
526 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
527 int FrameIndex = getStackSpaceFor(VirtReg, RC);
528 DEBUG(dbgs() << "Reloading %reg" << VirtReg << " into "
529 << TRI->getName(lri->second.PhysReg) << "\n");
530 TII->loadRegFromStackSlot(MBB, MI, lri->second.PhysReg, FrameIndex, RC,
534 LiveReg &LR = lri->second;
536 LR.LastOpNum = OpNum;
537 UsedInInstr.set(LR.PhysReg);
541 /// reservePhysReg - Mark PhysReg as reserved. This is very similar to
542 /// defineVirtReg except the physreg is reserved instead of allocated.
543 void RAFast::reservePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
545 UsedInInstr.set(PhysReg);
546 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
550 PhysRegState[PhysReg] = regReserved;
555 spillVirtReg(MBB, MI, VirtReg, true);
556 PhysRegState[PhysReg] = regReserved;
560 // This is a disabled register, disable all aliases.
561 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
562 unsigned Alias = *AS; ++AS) {
563 UsedInInstr.set(Alias);
564 switch (unsigned VirtReg = PhysRegState[Alias]) {
569 // is a super register already reserved?
570 if (TRI->isSuperRegister(PhysReg, Alias))
574 spillVirtReg(MBB, MI, VirtReg, true);
577 PhysRegState[Alias] = regDisabled;
579 PhysRegState[PhysReg] = regReserved;
582 // setPhysReg - Change MO the refer the PhysReg, considering subregs.
583 void RAFast::setPhysReg(MachineOperand &MO, unsigned PhysReg) {
584 if (unsigned Idx = MO.getSubReg()) {
585 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, Idx) : 0);
591 void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
592 DEBUG(dbgs() << "\nAllocating " << MBB);
594 atEndOfBlock = false;
595 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
596 assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
598 MachineBasicBlock::iterator MII = MBB.begin();
600 // Add live-in registers as live.
601 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
602 E = MBB.livein_end(); I != E; ++I)
603 reservePhysReg(MBB, MII, *I);
605 SmallVector<unsigned, 8> VirtKills, PhysKills, PhysDefs;
607 // Otherwise, sequentially allocate each instruction in the MBB.
608 while (MII != MBB.end()) {
609 MachineInstr *MI = MII++;
610 const TargetInstrDesc &TID = MI->getDesc();
612 dbgs() << "\n>> " << *MI << "Regs:";
613 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
614 if (PhysRegState[Reg] == regDisabled) continue;
615 dbgs() << " " << TRI->getName(Reg);
616 switch(PhysRegState[Reg]) {
623 dbgs() << "=%reg" << PhysRegState[Reg];
624 if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
626 assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
632 // Check that LiveVirtRegs is the inverse.
633 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
634 e = LiveVirtRegs.end(); i != e; ++i) {
635 assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
637 assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
639 assert(PhysRegState[i->second.PhysReg] == i->first &&
644 // Debug values are not allowed to change codegen in any way.
645 if (MI->isDebugValue()) {
646 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
647 MachineOperand &MO = MI->getOperand(i);
648 if (!MO.isReg()) continue;
649 unsigned Reg = MO.getReg();
650 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
651 LiveRegMap::iterator lri = LiveVirtRegs.find(Reg);
652 if (lri != LiveVirtRegs.end())
653 setPhysReg(MO, lri->second.PhysReg);
655 MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
661 // If this is a copy, we may be able to coalesce.
662 unsigned CopySrc, CopyDst, CopySrcSub, CopyDstSub;
663 if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
664 CopySrc = CopyDst = 0;
666 // Track registers used by instruction.
671 // Mark physreg uses and early clobbers as used.
672 // Collect PhysKills.
673 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
674 MachineOperand &MO = MI->getOperand(i);
675 if (!MO.isReg()) continue;
676 unsigned Reg = MO.getReg();
677 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg) ||
678 ReservedRegs.test(Reg)) continue;
681 // We are using a physreg directly. It had better not be clobbered by a
683 assert(PhysRegState[Reg] <= regReserved && "Using clobbered physreg");
684 if (PhysRegState[Reg] == regDisabled)
685 for (const unsigned *AS = TRI->getAliasSet(Reg);
686 unsigned Alias = *AS; ++AS)
687 assert(PhysRegState[Alias] <= regReserved &&
688 "Physreg alias was clobbered");
690 PhysKills.push_back(Reg); // Any clean physreg use is a kill.
691 UsedInInstr.set(Reg);
692 } else if (MO.isEarlyClobber()) {
693 spillPhysReg(MBB, MI, Reg, true);
694 UsedInInstr.set(Reg);
695 PhysDefs.push_back(Reg);
700 // Allocate virtreg uses and early clobbers.
702 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
703 MachineOperand &MO = MI->getOperand(i);
704 if (!MO.isReg()) continue;
705 unsigned Reg = MO.getReg();
706 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
708 unsigned PhysReg = reloadVirtReg(MBB, MI, i, Reg, CopyDst);
711 setPhysReg(MO, PhysReg);
713 VirtKills.push_back(Reg);
714 } else if (MO.isEarlyClobber()) {
715 unsigned PhysReg = defineVirtReg(MBB, MI, i, Reg, 0);
716 setPhysReg(MO, PhysReg);
717 PhysDefs.push_back(PhysReg);
721 // Process virtreg kills
722 for (unsigned i = 0, e = VirtKills.size(); i != e; ++i)
723 killVirtReg(VirtKills[i]);
726 // Process physreg kills
727 for (unsigned i = 0, e = PhysKills.size(); i != e; ++i)
728 killPhysReg(PhysKills[i]);
731 MRI->addPhysRegsUsed(UsedInInstr);
733 // Track registers defined by instruction - early clobbers at this point.
735 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
736 unsigned PhysReg = PhysDefs[i];
737 UsedInInstr.set(PhysReg);
738 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
739 unsigned Alias = *AS; ++AS)
740 UsedInInstr.set(Alias);
744 // Allocate defs and collect dead defs.
745 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
746 MachineOperand &MO = MI->getOperand(i);
747 if (!MO.isReg() || !MO.isDef() || !MO.getReg()) continue;
748 unsigned Reg = MO.getReg();
750 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
751 if (ReservedRegs.test(Reg)) continue;
753 spillPhysReg(MBB, MI, Reg, true);
755 reservePhysReg(MBB, MI, Reg);
757 PhysKills.push_back(Reg);
761 VirtKills.push_back(Reg);
762 unsigned PhysReg = defineVirtReg(MBB, MI, i, Reg, CopySrc);
765 setPhysReg(MO, PhysReg);
768 // Spill all dirty virtregs before a call, in case of an exception.
770 DEBUG(dbgs() << " Spilling remaining registers before call.\n");
774 // Process virtreg deads.
775 for (unsigned i = 0, e = VirtKills.size(); i != e; ++i)
776 killVirtReg(VirtKills[i]);
779 // Process physreg deads.
780 for (unsigned i = 0, e = PhysKills.size(); i != e; ++i)
781 killPhysReg(PhysKills[i]);
784 MRI->addPhysRegsUsed(UsedInInstr);
786 DEBUG(dbgs() << "<< " << *MI);
789 // Spill all physical registers holding virtual registers now.
791 DEBUG(dbgs() << "Killing live registers at end of block.\n");
792 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
793 for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
795 spillVirtReg(MBB, MI, i, true);
796 LiveVirtRegs.clear();
801 /// runOnMachineFunction - Register allocate the whole function
803 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
804 DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
805 << "********** Function: "
806 << ((Value*)Fn.getFunction())->getName() << '\n');
808 MRI = &MF->getRegInfo();
809 TM = &Fn.getTarget();
810 TRI = TM->getRegisterInfo();
811 TII = TM->getInstrInfo();
813 UsedInInstr.resize(TRI->getNumRegs());
814 ReservedRegs = TRI->getReservedRegs(*MF);
816 // initialize the virtual->physical register map to have a 'null'
817 // mapping for all virtual registers
818 unsigned LastVirtReg = MRI->getLastVirtReg();
819 StackSlotForVirtReg.grow(LastVirtReg);
821 // Loop over all of the basic blocks, eliminating virtual register references
822 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
824 AllocateBasicBlock(*MBB);
826 // Make sure the set of used physregs is closed under subreg operations.
827 MRI->closePhysRegsUsed(*TRI);
829 StackSlotForVirtReg.clear();
833 FunctionPass *llvm::createFastRegisterAllocator() {