1 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/IndexedMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(NumStores, "Number of stores added");
39 STATISTIC(NumLoads , "Number of loads added");
41 static RegisterRegAlloc
42 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
45 class RAFast : public MachineFunctionPass {
48 RAFast() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {}
50 const TargetMachine *TM;
52 const TargetRegisterInfo *TRI;
53 const TargetInstrInfo *TII;
55 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
56 // values are spilled.
57 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
59 // Everything we know about a live virtual register.
61 MachineInstr *LastUse; // Last instr to use reg.
62 unsigned PhysReg; // Currently held here.
63 unsigned short LastOpNum; // OpNum on LastUse.
64 bool Dirty; // Register needs spill.
66 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
68 assert(p && "Don't create LiveRegs without a PhysReg");
72 typedef DenseMap<unsigned, LiveReg> LiveRegMap;
74 // LiveVirtRegs - This map contains entries for each virtual register
75 // that is currently available in a physical register.
76 LiveRegMap LiveVirtRegs;
78 // RegState - Track the state of a physical register.
80 // A disabled register is not available for allocation, but an alias may
81 // be in use. A register can only be moved out of the disabled state if
82 // all aliases are disabled.
85 // A free register is not currently in use and can be allocated
86 // immediately without checking aliases.
89 // A reserved register has been assigned expolicitly (e.g., setting up a
90 // call parameter), and it remains reserved until it is used.
93 // A register state may also be a virtual register number, indication that
94 // the physical register is currently allocated to a virtual register. In
95 // that case, LiveVirtRegs contains the inverse mapping.
98 // PhysRegState - One of the RegState enums, or a virtreg.
99 std::vector<unsigned> PhysRegState;
101 // UsedInInstr - BitVector of physregs that are used in the current
102 // instruction, and so cannot be allocated.
103 BitVector UsedInInstr;
105 // ReservedRegs - vector of reserved physical registers.
106 BitVector ReservedRegs;
109 virtual const char *getPassName() const {
110 return "Fast Register Allocator";
113 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
114 AU.setPreservesCFG();
115 AU.addRequiredID(PHIEliminationID);
116 AU.addRequiredID(TwoAddressInstructionPassID);
117 MachineFunctionPass::getAnalysisUsage(AU);
121 bool runOnMachineFunction(MachineFunction &Fn);
122 void AllocateBasicBlock(MachineBasicBlock &MBB);
123 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
124 void killVirtReg(unsigned VirtReg);
125 void killVirtReg(LiveRegMap::iterator i);
126 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
127 unsigned VirtReg, bool isKill);
128 void killPhysReg(unsigned PhysReg);
129 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
130 unsigned PhysReg, bool isKill);
131 LiveRegMap::iterator assignVirtToPhysReg(unsigned VirtReg,
133 LiveRegMap::iterator allocVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
135 unsigned defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
136 unsigned OpNum, unsigned VirtReg);
137 unsigned reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
138 unsigned OpNum, unsigned VirtReg);
139 void reservePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
141 void spillAll(MachineBasicBlock &MBB, MachineInstr *MI);
142 void setPhysReg(MachineOperand &MO, unsigned PhysReg);
147 /// getStackSpaceFor - This allocates space for the specified virtual register
148 /// to be held on the stack.
149 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
150 // Find the location Reg would belong...
151 int SS = StackSlotForVirtReg[VirtReg];
153 return SS; // Already has space allocated?
155 // Allocate a new stack object for this spill location...
156 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
160 StackSlotForVirtReg[VirtReg] = FrameIdx;
164 /// killVirtReg - Mark virtreg as no longer available.
165 void RAFast::killVirtReg(LiveRegMap::iterator i) {
166 assert(i != LiveVirtRegs.end() && "Killing unmapped virtual register");
167 unsigned VirtReg = i->first;
168 const LiveReg &LR = i->second;
169 assert(PhysRegState[LR.PhysReg] == VirtReg && "Broken RegState mapping");
170 PhysRegState[LR.PhysReg] = regFree;
172 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
173 if (MO.isUse()) MO.setIsKill();
175 DEBUG(dbgs() << " - last seen here: " << *LR.LastUse);
177 LiveVirtRegs.erase(i);
180 /// killVirtReg - Mark virtreg as no longer available.
181 void RAFast::killVirtReg(unsigned VirtReg) {
182 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
183 "killVirtReg needs a virtual register");
184 DEBUG(dbgs() << " Killing %reg" << VirtReg << "\n");
185 LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg);
186 if (i != LiveVirtRegs.end())
190 /// spillVirtReg - This method spills the value specified by VirtReg into the
191 /// corresponding stack slot if needed. If isKill is set, the register is also
193 void RAFast::spillVirtReg(MachineBasicBlock &MBB,
194 MachineBasicBlock::iterator MI,
195 unsigned VirtReg, bool isKill) {
196 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
197 "Spilling a physical register is illegal!");
198 LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg);
199 assert(i != LiveVirtRegs.end() && "Spilling unmapped virtual register");
200 LiveReg &LR = i->second;
201 assert(PhysRegState[LR.PhysReg] == VirtReg && "Broken RegState mapping");
203 // If this physreg is used by the instruction, we want to kill it on the
204 // instruction, not on the spill.
205 bool spillKill = isKill && LR.LastUse != MI;
209 DEBUG(dbgs() << " Spilling register " << TRI->getName(LR.PhysReg)
210 << " containing %reg" << VirtReg);
211 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
212 int FrameIndex = getStackSpaceFor(VirtReg, RC);
213 DEBUG(dbgs() << " to stack slot #" << FrameIndex << "\n");
214 TII->storeRegToStackSlot(MBB, MI, LR.PhysReg, spillKill,
215 FrameIndex, RC, TRI);
216 ++NumStores; // Update statistics
219 LR.LastUse = 0; // Don't kill register again
221 MachineInstr *Spill = llvm::prior(MI);
223 LR.LastOpNum = Spill->findRegisterUseOperandIdx(LR.PhysReg);
231 /// spillAll - Spill all dirty virtregs without killing them.
232 void RAFast::spillAll(MachineBasicBlock &MBB, MachineInstr *MI) {
233 SmallVector<unsigned, 16> Dirty;
234 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
235 e = LiveVirtRegs.end(); i != e; ++i)
237 Dirty.push_back(i->first);
238 for (unsigned i = 0, e = Dirty.size(); i != e; ++i)
239 spillVirtReg(MBB, MI, Dirty[i], false);
242 /// killPhysReg - Kill any virtual register aliased by PhysReg.
243 void RAFast::killPhysReg(unsigned PhysReg) {
244 // Fast path for the normal case.
245 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
251 PhysRegState[PhysReg] = regFree;
254 killVirtReg(VirtReg);
258 // This is a disabled register, we have to check aliases.
259 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
260 unsigned Alias = *AS; ++AS) {
261 switch (unsigned VirtReg = PhysRegState[Alias]) {
266 PhysRegState[Alias] = regFree;
269 killVirtReg(VirtReg);
275 /// spillPhysReg - Spill any dirty virtual registers that aliases PhysReg. If
276 /// isKill is set, they are also killed.
277 void RAFast::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
278 unsigned PhysReg, bool isKill) {
279 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
286 PhysRegState[PhysReg] = regFree;
289 spillVirtReg(MBB, MI, VirtReg, isKill);
293 // This is a disabled register, we have to check aliases.
294 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
295 unsigned Alias = *AS; ++AS) {
296 switch (unsigned VirtReg = PhysRegState[Alias]) {
302 PhysRegState[Alias] = regFree;
305 spillVirtReg(MBB, MI, VirtReg, isKill);
311 /// assignVirtToPhysReg - This method updates local state so that we know
312 /// that PhysReg is the proper container for VirtReg now. The physical
313 /// register must not be used for anything else when this is called.
315 RAFast::LiveRegMap::iterator
316 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
317 DEBUG(dbgs() << " Assigning %reg" << VirtReg << " to "
318 << TRI->getName(PhysReg) << "\n");
319 PhysRegState[PhysReg] = VirtReg;
320 return LiveVirtRegs.insert(std::make_pair(VirtReg, PhysReg)).first;
323 /// allocVirtReg - Allocate a physical register for VirtReg.
324 RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
327 const unsigned spillCost = 100;
328 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
329 "Can only allocate virtual registers");
331 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
332 TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
333 TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
335 // First try to find a completely free register.
336 unsigned BestCost = 0, BestReg = 0;
337 bool hasDisabled = false;
338 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
339 unsigned PhysReg = *I;
340 switch(PhysRegState[PhysReg]) {
346 if (!UsedInInstr.test(PhysReg))
347 return assignVirtToPhysReg(VirtReg, PhysReg);
350 // Grab the first spillable register we meet.
351 if (!BestReg && !UsedInInstr.test(PhysReg))
352 BestReg = PhysReg, BestCost = spillCost;
357 DEBUG(dbgs() << " Allocating %reg" << VirtReg << " from " << RC->getName()
358 << " candidate=" << TRI->getName(BestReg) << "\n");
360 // Try to extend the working set for RC if there were any disabled registers.
361 if (hasDisabled && (!BestReg || BestCost >= spillCost)) {
362 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
363 unsigned PhysReg = *I;
364 if (PhysRegState[PhysReg] != regDisabled || UsedInInstr.test(PhysReg))
367 // Calculate the cost of bringing PhysReg into the working set.
369 bool Impossible = false;
370 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
371 unsigned Alias = *AS; ++AS) {
372 if (UsedInInstr.test(Alias)) {
376 switch (PhysRegState[Alias]) {
390 if (Impossible) continue;
391 DEBUG(dbgs() << " - candidate " << TRI->getName(PhysReg)
392 << " cost=" << Cost << "\n");
393 if (!BestReg || Cost < BestCost) {
396 if (Cost < spillCost) break;
402 // BestCost is 0 when all aliases are already disabled.
404 if (PhysRegState[BestReg] != regDisabled)
405 spillVirtReg(MBB, MI, PhysRegState[BestReg], true);
407 // Make sure all aliases are disabled.
408 for (const unsigned *AS = TRI->getAliasSet(BestReg);
409 unsigned Alias = *AS; ++AS) {
410 switch (PhysRegState[Alias]) {
414 PhysRegState[Alias] = regDisabled;
417 spillVirtReg(MBB, MI, PhysRegState[Alias], true);
418 PhysRegState[Alias] = regDisabled;
424 return assignVirtToPhysReg(VirtReg, BestReg);
427 // Nothing we can do.
429 raw_string_ostream Msg(msg);
430 Msg << "Ran out of registers during register allocation!";
431 if (MI->isInlineAsm()) {
432 Msg << "\nPlease check your inline asm statement for "
433 << "invalid constraints:\n";
436 report_fatal_error(Msg.str());
437 return LiveVirtRegs.end();
440 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
441 unsigned RAFast::defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
442 unsigned OpNum, unsigned VirtReg) {
443 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
444 "Not a virtual register");
445 LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg);
446 if (i == LiveVirtRegs.end())
447 i = allocVirtReg(MBB, MI, VirtReg);
448 LiveReg &LR = i->second;
450 LR.LastOpNum = OpNum;
452 UsedInInstr.set(LR.PhysReg);
456 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
457 unsigned RAFast::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
458 unsigned OpNum, unsigned VirtReg) {
459 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
460 "Not a virtual register");
461 LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg);
462 if (i == LiveVirtRegs.end()) {
463 i = allocVirtReg(MBB, MI, VirtReg);
464 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
465 int FrameIndex = getStackSpaceFor(VirtReg, RC);
466 DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into "
467 << TRI->getName(i->second.PhysReg) << "\n");
468 TII->loadRegFromStackSlot(MBB, MI, i->second.PhysReg, FrameIndex, RC, TRI);
471 LiveReg &LR = i->second;
473 LR.LastOpNum = OpNum;
474 UsedInInstr.set(LR.PhysReg);
478 /// reservePhysReg - Mark PhysReg as reserved. This is very similar to
479 /// defineVirtReg except the physreg is reverved instead of allocated.
480 void RAFast::reservePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
482 UsedInInstr.set(PhysReg);
483 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
487 PhysRegState[PhysReg] = regReserved;
492 spillVirtReg(MBB, MI, VirtReg, true);
493 PhysRegState[PhysReg] = regReserved;
497 // This is a disabled register, disable all aliases.
498 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
499 unsigned Alias = *AS; ++AS) {
500 UsedInInstr.set(Alias);
501 switch (unsigned VirtReg = PhysRegState[Alias]) {
506 // is a super register already reserved?
507 if (TRI->isSuperRegister(PhysReg, Alias))
511 spillVirtReg(MBB, MI, VirtReg, true);
514 PhysRegState[Alias] = regDisabled;
516 PhysRegState[PhysReg] = regReserved;
519 // setPhysReg - Change MO the refer the PhysReg, considering subregs.
520 void RAFast::setPhysReg(MachineOperand &MO, unsigned PhysReg) {
521 if (unsigned Idx = MO.getSubReg()) {
522 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, Idx) : 0);
528 void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
529 DEBUG(dbgs() << "\nBB#" << MBB.getNumber() << ", "<< MBB.getName() << "\n");
531 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
532 assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
534 MachineBasicBlock::iterator MII = MBB.begin();
536 // Add live-in registers as live.
537 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
538 E = MBB.livein_end(); I != E; ++I)
539 reservePhysReg(MBB, MII, *I);
541 SmallVector<unsigned, 8> VirtKills, PhysKills, PhysDefs;
543 // Otherwise, sequentially allocate each instruction in the MBB.
544 while (MII != MBB.end()) {
545 MachineInstr *MI = MII++;
546 const TargetInstrDesc &TID = MI->getDesc();
548 dbgs() << "\nStarting RegAlloc of: " << *MI << "Working set:";
549 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
550 if (PhysRegState[Reg] == regDisabled) continue;
551 dbgs() << " " << TRI->getName(Reg);
552 switch(PhysRegState[Reg]) {
559 dbgs() << "=%reg" << PhysRegState[Reg];
560 if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
562 assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
568 // Check that LiveVirtRegs is the inverse.
569 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
570 e = LiveVirtRegs.end(); i != e; ++i) {
571 assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
573 assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
575 assert(PhysRegState[i->second.PhysReg] == i->first &&
580 // Debug values are not allowed to change codegen in any way.
581 if (MI->isDebugValue()) {
582 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
583 MachineOperand &MO = MI->getOperand(i);
584 if (!MO.isReg()) continue;
585 unsigned Reg = MO.getReg();
586 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
587 LiveRegMap::iterator it = LiveVirtRegs.find(Reg);
588 if (it != LiveVirtRegs.end())
589 setPhysReg(MO, it->second.PhysReg);
591 MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
597 // Track registers used by instruction.
602 // Mark physreg uses and early clobbers as used.
603 // Collect PhysKills.
604 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
605 MachineOperand &MO = MI->getOperand(i);
606 if (!MO.isReg()) continue;
608 // FIXME: For now, don't trust kill flags
609 if (MO.isUse()) MO.setIsKill(false);
611 unsigned Reg = MO.getReg();
612 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg) ||
613 ReservedRegs.test(Reg)) continue;
615 PhysKills.push_back(Reg); // Any clean physreg use is a kill.
616 UsedInInstr.set(Reg);
617 } else if (MO.isEarlyClobber()) {
618 spillPhysReg(MBB, MI, Reg, true);
619 UsedInInstr.set(Reg);
620 PhysDefs.push_back(Reg);
625 // Allocate virtreg uses and early clobbers.
627 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
628 MachineOperand &MO = MI->getOperand(i);
629 if (!MO.isReg()) continue;
630 unsigned Reg = MO.getReg();
631 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
633 setPhysReg(MO, reloadVirtReg(MBB, MI, i, Reg));
635 VirtKills.push_back(Reg);
636 } else if (MO.isEarlyClobber()) {
637 unsigned PhysReg = defineVirtReg(MBB, MI, i, Reg);
638 setPhysReg(MO, PhysReg);
639 PhysDefs.push_back(PhysReg);
643 // Process virtreg kills
644 for (unsigned i = 0, e = VirtKills.size(); i != e; ++i)
645 killVirtReg(VirtKills[i]);
648 // Process physreg kills
649 for (unsigned i = 0, e = PhysKills.size(); i != e; ++i)
650 killPhysReg(PhysKills[i]);
653 MF->getRegInfo().addPhysRegsUsed(UsedInInstr);
655 // Track registers defined by instruction - early clobbers at this point.
657 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
658 unsigned PhysReg = PhysDefs[i];
659 UsedInInstr.set(PhysReg);
660 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
661 unsigned Alias = *AS; ++AS)
662 UsedInInstr.set(Alias);
666 // Allocate defs and collect dead defs.
667 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
668 MachineOperand &MO = MI->getOperand(i);
669 if (!MO.isReg() || !MO.isDef() || !MO.getReg()) continue;
670 unsigned Reg = MO.getReg();
672 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
673 if (ReservedRegs.test(Reg)) continue;
675 spillPhysReg(MBB, MI, Reg, true);
677 reservePhysReg(MBB, MI, Reg);
679 PhysKills.push_back(Reg);
683 VirtKills.push_back(Reg);
684 setPhysReg(MO, defineVirtReg(MBB, MI, i, Reg));
687 // Spill all dirty virtregs before a call, in case of an exception.
689 DEBUG(dbgs() << " Spilling remaining registers before call.\n");
693 // Process virtreg deads.
694 for (unsigned i = 0, e = VirtKills.size(); i != e; ++i)
695 killVirtReg(VirtKills[i]);
698 // Process physreg deads.
699 for (unsigned i = 0, e = PhysKills.size(); i != e; ++i)
700 killPhysReg(PhysKills[i]);
703 MF->getRegInfo().addPhysRegsUsed(UsedInInstr);
706 // Spill all physical registers holding virtual registers now.
707 DEBUG(dbgs() << "Killing live registers at end of block.\n");
708 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
709 while (!LiveVirtRegs.empty())
710 spillVirtReg(MBB, MI, LiveVirtRegs.begin()->first, true);
715 /// runOnMachineFunction - Register allocate the whole function
717 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
718 DEBUG(dbgs() << "Machine Function\n");
721 TM = &Fn.getTarget();
722 TRI = TM->getRegisterInfo();
723 TII = TM->getInstrInfo();
725 UsedInInstr.resize(TRI->getNumRegs());
726 ReservedRegs = TRI->getReservedRegs(*MF);
728 // initialize the virtual->physical register map to have a 'null'
729 // mapping for all virtual registers
730 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
731 StackSlotForVirtReg.grow(LastVirtReg);
733 // Loop over all of the basic blocks, eliminating virtual register references
734 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
736 AllocateBasicBlock(*MBB);
738 // Make sure the set of used physregs is closed under subreg operations.
739 MF->getRegInfo().closePhysRegsUsed(*TRI);
741 StackSlotForVirtReg.clear();
745 FunctionPass *llvm::createFastRegisterAllocator() {