1 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/IndexedMap.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/SparseSet.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegAllocRegistry.h"
29 #include "llvm/CodeGen/RegisterClassInfo.h"
30 #include "llvm/IR/BasicBlock.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "regalloc"
42 STATISTIC(NumStores, "Number of stores added");
43 STATISTIC(NumLoads , "Number of loads added");
44 STATISTIC(NumCopies, "Number of copies coalesced");
46 static RegisterRegAlloc
47 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
50 class RAFast : public MachineFunctionPass {
53 RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
54 isBulkSpilling(false) {}
57 MachineRegisterInfo *MRI;
58 const TargetRegisterInfo *TRI;
59 const TargetInstrInfo *TII;
60 RegisterClassInfo RegClassInfo;
62 // Basic block currently being allocated.
63 MachineBasicBlock *MBB;
65 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
66 // values are spilled.
67 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
69 // Everything we know about a live virtual register.
71 MachineInstr *LastUse; // Last instr to use reg.
72 unsigned VirtReg; // Virtual register number.
73 unsigned PhysReg; // Currently held here.
74 unsigned short LastOpNum; // OpNum on LastUse.
75 bool Dirty; // Register needs spill.
77 explicit LiveReg(unsigned v)
78 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
80 unsigned getSparseSetIndex() const {
81 return TargetRegisterInfo::virtReg2Index(VirtReg);
85 typedef SparseSet<LiveReg> LiveRegMap;
87 // LiveVirtRegs - This map contains entries for each virtual register
88 // that is currently available in a physical register.
89 LiveRegMap LiveVirtRegs;
91 DenseMap<unsigned, SmallVector<MachineInstr *, 4> > LiveDbgValueMap;
93 // RegState - Track the state of a physical register.
95 // A disabled register is not available for allocation, but an alias may
96 // be in use. A register can only be moved out of the disabled state if
97 // all aliases are disabled.
100 // A free register is not currently in use and can be allocated
101 // immediately without checking aliases.
104 // A reserved register has been assigned explicitly (e.g., setting up a
105 // call parameter), and it remains reserved until it is used.
108 // A register state may also be a virtual register number, indication that
109 // the physical register is currently allocated to a virtual register. In
110 // that case, LiveVirtRegs contains the inverse mapping.
113 // PhysRegState - One of the RegState enums, or a virtreg.
114 std::vector<unsigned> PhysRegState;
116 // Set of register units.
117 typedef SparseSet<unsigned> UsedInInstrSet;
119 // Set of register units that are used in the current instruction, and so
120 // cannot be allocated.
121 UsedInInstrSet UsedInInstr;
123 // Mark a physreg as used in this instruction.
124 void markRegUsedInInstr(unsigned PhysReg) {
125 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
126 UsedInInstr.insert(*Units);
129 // Check if a physreg or any of its aliases are used in this instruction.
130 bool isRegUsedInInstr(unsigned PhysReg) const {
131 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
132 if (UsedInInstr.count(*Units))
137 // SkippedInstrs - Descriptors of instructions whose clobber list was
138 // ignored because all registers were spilled. It is still necessary to
139 // mark all the clobbered registers as used by the function.
140 SmallPtrSet<const MCInstrDesc*, 4> SkippedInstrs;
142 // isBulkSpilling - This flag is set when LiveRegMap will be cleared
143 // completely after spilling all live registers. LiveRegMap entries should
150 spillImpossible = ~0u
153 const char *getPassName() const override {
154 return "Fast Register Allocator";
157 void getAnalysisUsage(AnalysisUsage &AU) const override {
158 AU.setPreservesCFG();
159 MachineFunctionPass::getAnalysisUsage(AU);
163 bool runOnMachineFunction(MachineFunction &Fn) override;
164 void AllocateBasicBlock();
165 void handleThroughOperands(MachineInstr *MI,
166 SmallVectorImpl<unsigned> &VirtDead);
167 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
168 bool isLastUseOfLocalReg(MachineOperand&);
170 void addKillFlag(const LiveReg&);
171 void killVirtReg(LiveRegMap::iterator);
172 void killVirtReg(unsigned VirtReg);
173 void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
174 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
176 void usePhysReg(MachineOperand&);
177 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
178 unsigned calcSpillCost(unsigned PhysReg) const;
179 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg);
180 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
181 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
183 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
184 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
186 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
187 LiveRegMap::iterator allocVirtReg(MachineInstr *MI, LiveRegMap::iterator,
189 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
190 unsigned VirtReg, unsigned Hint);
191 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
192 unsigned VirtReg, unsigned Hint);
193 void spillAll(MachineBasicBlock::iterator MI);
194 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
199 /// getStackSpaceFor - This allocates space for the specified virtual register
200 /// to be held on the stack.
201 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
202 // Find the location Reg would belong...
203 int SS = StackSlotForVirtReg[VirtReg];
205 return SS; // Already has space allocated?
207 // Allocate a new stack object for this spill location...
208 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
212 StackSlotForVirtReg[VirtReg] = FrameIdx;
216 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
217 /// its virtual register, and it is guaranteed to be a block-local register.
219 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
220 // If the register has ever been spilled or reloaded, we conservatively assume
221 // it is a global register used in multiple blocks.
222 if (StackSlotForVirtReg[MO.getReg()] != -1)
225 // Check that the use/def chain has exactly one operand - MO.
226 MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg());
229 return ++I == MRI->reg_nodbg_end();
232 /// addKillFlag - Set kill flags on last use of a virtual register.
233 void RAFast::addKillFlag(const LiveReg &LR) {
234 if (!LR.LastUse) return;
235 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
236 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
237 if (MO.getReg() == LR.PhysReg)
240 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
244 /// killVirtReg - Mark virtreg as no longer available.
245 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
247 assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
248 "Broken RegState mapping");
249 PhysRegState[LRI->PhysReg] = regFree;
250 // Erase from LiveVirtRegs unless we're spilling in bulk.
252 LiveVirtRegs.erase(LRI);
255 /// killVirtReg - Mark virtreg as no longer available.
256 void RAFast::killVirtReg(unsigned VirtReg) {
257 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
258 "killVirtReg needs a virtual register");
259 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
260 if (LRI != LiveVirtRegs.end())
264 /// spillVirtReg - This method spills the value specified by VirtReg into the
265 /// corresponding stack slot if needed.
266 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
267 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
268 "Spilling a physical register is illegal!");
269 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
270 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
271 spillVirtReg(MI, LRI);
274 /// spillVirtReg - Do the actual work of spilling.
275 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
276 LiveRegMap::iterator LRI) {
278 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
281 // If this physreg is used by the instruction, we want to kill it on the
282 // instruction, not on the spill.
283 bool SpillKill = LR.LastUse != MI;
285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
286 << " in " << PrintReg(LR.PhysReg, TRI));
287 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
288 int FI = getStackSpaceFor(LRI->VirtReg, RC);
289 DEBUG(dbgs() << " to stack slot #" << FI << "\n");
290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
291 ++NumStores; // Update statistics
293 // If this register is used by DBG_VALUE then insert new DBG_VALUE to
294 // identify spilled location as the place to find corresponding variable's
296 SmallVectorImpl<MachineInstr *> &LRIDbgValues =
297 LiveDbgValueMap[LRI->VirtReg];
298 for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {
299 MachineInstr *DBG = LRIDbgValues[li];
300 const MDNode *Var = DBG->getDebugVariable();
301 const MDNode *Expr = DBG->getDebugExpression();
302 bool IsIndirect = DBG->isIndirectDebugValue();
303 uint64_t Offset = IsIndirect ? DBG->getOperand(1).getImm() : 0;
305 if (MI == MBB->end()) {
306 // If MI is at basic block end then use last instruction's location.
307 MachineBasicBlock::iterator EI = MI;
308 DL = (--EI)->getDebugLoc();
310 DL = MI->getDebugLoc();
311 MachineInstr *NewDV =
312 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE))
317 assert(NewDV->getParent() == MBB && "dangling parent pointer");
319 DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
321 // Now this register is spilled there is should not be any DBG_VALUE
322 // pointing to this register because they are all pointing to spilled value
324 LRIDbgValues.clear();
326 LR.LastUse = nullptr; // Don't kill register again
331 /// spillAll - Spill all dirty virtregs without killing them.
332 void RAFast::spillAll(MachineBasicBlock::iterator MI) {
333 if (LiveVirtRegs.empty()) return;
334 isBulkSpilling = true;
335 // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
336 // of spilling here is deterministic, if arbitrary.
337 for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
340 LiveVirtRegs.clear();
341 isBulkSpilling = false;
344 /// usePhysReg - Handle the direct use of a physical register.
345 /// Check that the register is not used by a virtreg.
346 /// Kill the physreg, marking it free.
347 /// This may add implicit kills to MO->getParent() and invalidate MO.
348 void RAFast::usePhysReg(MachineOperand &MO) {
349 unsigned PhysReg = MO.getReg();
350 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
351 "Bad usePhysReg operand");
352 markRegUsedInInstr(PhysReg);
353 switch (PhysRegState[PhysReg]) {
357 PhysRegState[PhysReg] = regFree;
363 // The physreg was allocated to a virtual register. That means the value we
364 // wanted has been clobbered.
365 llvm_unreachable("Instruction uses an allocated register");
368 // Maybe a superregister is reserved?
369 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
370 unsigned Alias = *AI;
371 switch (PhysRegState[Alias]) {
375 // Either PhysReg is a subregister of Alias and we mark the
376 // whole register as free, or PhysReg is the superregister of
377 // Alias and we mark all the aliases as disabled before freeing
379 // In the latter case, since PhysReg was disabled, this means that
380 // its value is defined only by physical sub-registers. This check
381 // is performed by the assert of the default case in this loop.
382 // Note: The value of the superregister may only be partial
383 // defined, that is why regDisabled is a valid state for aliases.
384 assert((TRI->isSuperRegister(PhysReg, Alias) ||
385 TRI->isSuperRegister(Alias, PhysReg)) &&
386 "Instruction is not using a subregister of a reserved register");
389 if (TRI->isSuperRegister(PhysReg, Alias)) {
390 // Leave the superregister in the working set.
391 PhysRegState[Alias] = regFree;
392 MO.getParent()->addRegisterKilled(Alias, TRI, true);
395 // Some other alias was in the working set - clear it.
396 PhysRegState[Alias] = regDisabled;
399 llvm_unreachable("Instruction uses an alias of an allocated register");
403 // All aliases are disabled, bring register into working set.
404 PhysRegState[PhysReg] = regFree;
408 /// definePhysReg - Mark PhysReg as reserved or free after spilling any
409 /// virtregs. This is very similar to defineVirtReg except the physreg is
410 /// reserved instead of allocated.
411 void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
413 markRegUsedInInstr(PhysReg);
414 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
418 spillVirtReg(MI, VirtReg);
422 PhysRegState[PhysReg] = NewState;
426 // This is a disabled register, disable all aliases.
427 PhysRegState[PhysReg] = NewState;
428 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
429 unsigned Alias = *AI;
430 switch (unsigned VirtReg = PhysRegState[Alias]) {
434 spillVirtReg(MI, VirtReg);
438 PhysRegState[Alias] = regDisabled;
439 if (TRI->isSuperRegister(PhysReg, Alias))
447 // calcSpillCost - Return the cost of spilling clearing out PhysReg and
448 // aliases so it is free for allocation.
449 // Returns 0 when PhysReg is free or disabled with all aliases disabled - it
450 // can be allocated directly.
451 // Returns spillImpossible when PhysReg or an alias can't be spilled.
452 unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
453 if (isRegUsedInInstr(PhysReg)) {
454 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n");
455 return spillImpossible;
457 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
463 DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
464 << PrintReg(PhysReg, TRI) << " is reserved already.\n");
465 return spillImpossible;
467 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
468 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
469 return I->Dirty ? spillDirty : spillClean;
473 // This is a disabled register, add up cost of aliases.
474 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n");
476 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
477 unsigned Alias = *AI;
478 switch (unsigned VirtReg = PhysRegState[Alias]) {
485 return spillImpossible;
487 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
488 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
489 Cost += I->Dirty ? spillDirty : spillClean;
498 /// assignVirtToPhysReg - This method updates local state so that we know
499 /// that PhysReg is the proper container for VirtReg now. The physical
500 /// register must not be used for anything else when this is called.
502 void RAFast::assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) {
503 DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
504 << PrintReg(PhysReg, TRI) << "\n");
505 PhysRegState[PhysReg] = LR.VirtReg;
506 assert(!LR.PhysReg && "Already assigned a physreg");
507 LR.PhysReg = PhysReg;
510 RAFast::LiveRegMap::iterator
511 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
512 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
513 assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared");
514 assignVirtToPhysReg(*LRI, PhysReg);
518 /// allocVirtReg - Allocate a physical register for VirtReg.
519 RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI,
520 LiveRegMap::iterator LRI,
522 const unsigned VirtReg = LRI->VirtReg;
524 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
525 "Can only allocate virtual registers");
527 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
529 // Ignore invalid hints.
530 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
531 !RC->contains(Hint) || !MRI->isAllocatable(Hint)))
534 // Take hint when possible.
536 // Ignore the hint if we would have to spill a dirty register.
537 unsigned Cost = calcSpillCost(Hint);
538 if (Cost < spillDirty) {
540 definePhysReg(MI, Hint, regFree);
541 // definePhysReg may kill virtual registers and modify LiveVirtRegs.
542 // That invalidates LRI, so run a new lookup for VirtReg.
543 return assignVirtToPhysReg(VirtReg, Hint);
547 ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
549 // First try to find a completely free register.
550 for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
551 unsigned PhysReg = *I;
552 if (PhysRegState[PhysReg] == regFree && !isRegUsedInInstr(PhysReg)) {
553 assignVirtToPhysReg(*LRI, PhysReg);
558 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
559 << TRI->getRegClassName(RC) << "\n");
561 unsigned BestReg = 0, BestCost = spillImpossible;
562 for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
563 unsigned Cost = calcSpillCost(*I);
564 DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n");
565 DEBUG(dbgs() << "\tCost: " << Cost << "\n");
566 DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n");
567 // Cost is 0 when all aliases are already disabled.
569 assignVirtToPhysReg(*LRI, *I);
573 BestReg = *I, BestCost = Cost;
577 definePhysReg(MI, BestReg, regFree);
578 // definePhysReg may kill virtual registers and modify LiveVirtRegs.
579 // That invalidates LRI, so run a new lookup for VirtReg.
580 return assignVirtToPhysReg(VirtReg, BestReg);
583 // Nothing we can do. Report an error and keep going with a bad allocation.
584 if (MI->isInlineAsm())
585 MI->emitError("inline assembly requires more registers than available");
587 MI->emitError("ran out of registers during register allocation");
588 definePhysReg(MI, *AO.begin(), regFree);
589 return assignVirtToPhysReg(VirtReg, *AO.begin());
592 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
593 RAFast::LiveRegMap::iterator
594 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
595 unsigned VirtReg, unsigned Hint) {
596 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
597 "Not a virtual register");
598 LiveRegMap::iterator LRI;
600 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
602 // If there is no hint, peek at the only use of this register.
603 if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
604 MRI->hasOneNonDBGUse(VirtReg)) {
605 const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg);
606 // It's a copy, use the destination register as a hint.
607 if (UseMI.isCopyLike())
608 Hint = UseMI.getOperand(0).getReg();
610 LRI = allocVirtReg(MI, LRI, Hint);
611 } else if (LRI->LastUse) {
612 // Redefining a live register - kill at the last use, unless it is this
613 // instruction defining VirtReg multiple times.
614 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse())
617 assert(LRI->PhysReg && "Register not assigned");
619 LRI->LastOpNum = OpNum;
621 markRegUsedInInstr(LRI->PhysReg);
625 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
626 RAFast::LiveRegMap::iterator
627 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
628 unsigned VirtReg, unsigned Hint) {
629 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
630 "Not a virtual register");
631 LiveRegMap::iterator LRI;
633 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
634 MachineOperand &MO = MI->getOperand(OpNum);
636 LRI = allocVirtReg(MI, LRI, Hint);
637 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
638 int FrameIndex = getStackSpaceFor(VirtReg, RC);
639 DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
640 << PrintReg(LRI->PhysReg, TRI) << "\n");
641 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
643 } else if (LRI->Dirty) {
644 if (isLastUseOfLocalReg(MO)) {
645 DEBUG(dbgs() << "Killing last use: " << MO << "\n");
650 } else if (MO.isKill()) {
651 DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
653 } else if (MO.isDead()) {
654 DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
657 } else if (MO.isKill()) {
658 // We must remove kill flags from uses of reloaded registers because the
659 // register would be killed immediately, and there might be a second use:
660 // %foo = OR %x<kill>, %x
661 // This would cause a second reload of %x into a different register.
662 DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
664 } else if (MO.isDead()) {
665 DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
668 assert(LRI->PhysReg && "Register not assigned");
670 LRI->LastOpNum = OpNum;
671 markRegUsedInInstr(LRI->PhysReg);
675 // setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering
676 // subregs. This may invalidate any operand pointers.
677 // Return true if the operand kills its register.
678 bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) {
679 MachineOperand &MO = MI->getOperand(OpNum);
680 bool Dead = MO.isDead();
681 if (!MO.getSubReg()) {
683 return MO.isKill() || Dead;
686 // Handle subregister index.
687 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
690 // A kill flag implies killing the full register. Add corresponding super
693 MI->addRegisterKilled(PhysReg, TRI, true);
697 // A <def,read-undef> of a sub-register requires an implicit def of the full
699 if (MO.isDef() && MO.isUndef())
700 MI->addRegisterDefined(PhysReg, TRI);
705 // Handle special instruction operand like early clobbers and tied ops when
706 // there are additional physreg defines.
707 void RAFast::handleThroughOperands(MachineInstr *MI,
708 SmallVectorImpl<unsigned> &VirtDead) {
709 DEBUG(dbgs() << "Scanning for through registers:");
710 SmallSet<unsigned, 8> ThroughRegs;
711 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
712 MachineOperand &MO = MI->getOperand(i);
713 if (!MO.isReg()) continue;
714 unsigned Reg = MO.getReg();
715 if (!TargetRegisterInfo::isVirtualRegister(Reg))
717 if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
718 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
719 if (ThroughRegs.insert(Reg).second)
720 DEBUG(dbgs() << ' ' << PrintReg(Reg));
724 // If any physreg defines collide with preallocated through registers,
725 // we must spill and reallocate.
726 DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
727 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
728 MachineOperand &MO = MI->getOperand(i);
729 if (!MO.isReg() || !MO.isDef()) continue;
730 unsigned Reg = MO.getReg();
731 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
732 markRegUsedInInstr(Reg);
733 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
734 if (ThroughRegs.count(PhysRegState[*AI]))
735 definePhysReg(MI, *AI, regFree);
739 SmallVector<unsigned, 8> PartialDefs;
740 DEBUG(dbgs() << "Allocating tied uses.\n");
741 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
742 MachineOperand &MO = MI->getOperand(i);
743 if (!MO.isReg()) continue;
744 unsigned Reg = MO.getReg();
745 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
748 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
749 DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
751 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
752 unsigned PhysReg = LRI->PhysReg;
753 setPhysReg(MI, i, PhysReg);
754 // Note: we don't update the def operand yet. That would cause the normal
755 // def-scan to attempt spilling.
756 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
757 DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
758 // Reload the register, but don't assign to the operand just yet.
759 // That would confuse the later phys-def processing pass.
760 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
761 PartialDefs.push_back(LRI->PhysReg);
765 DEBUG(dbgs() << "Allocating early clobbers.\n");
766 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
767 MachineOperand &MO = MI->getOperand(i);
768 if (!MO.isReg()) continue;
769 unsigned Reg = MO.getReg();
770 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
771 if (!MO.isEarlyClobber())
773 // Note: defineVirtReg may invalidate MO.
774 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
775 unsigned PhysReg = LRI->PhysReg;
776 if (setPhysReg(MI, i, PhysReg))
777 VirtDead.push_back(Reg);
780 // Restore UsedInInstr to a state usable for allocating normal virtual uses.
782 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
783 MachineOperand &MO = MI->getOperand(i);
784 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
785 unsigned Reg = MO.getReg();
786 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
787 DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI)
788 << " as used in instr\n");
789 markRegUsedInInstr(Reg);
792 // Also mark PartialDefs as used to avoid reallocation.
793 for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
794 markRegUsedInInstr(PartialDefs[i]);
797 void RAFast::AllocateBasicBlock() {
798 DEBUG(dbgs() << "\nAllocating " << *MBB);
800 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
801 assert(LiveVirtRegs.empty() && "Mapping not cleared from last block?");
803 MachineBasicBlock::iterator MII = MBB->begin();
805 // Add live-in registers as live.
806 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
807 E = MBB->livein_end(); I != E; ++I)
808 if (MRI->isAllocatable(*I))
809 definePhysReg(MII, *I, regReserved);
811 SmallVector<unsigned, 8> VirtDead;
812 SmallVector<MachineInstr*, 32> Coalesced;
814 // Otherwise, sequentially allocate each instruction in the MBB.
815 while (MII != MBB->end()) {
816 MachineInstr *MI = MII++;
817 const MCInstrDesc &MCID = MI->getDesc();
819 dbgs() << "\n>> " << *MI << "Regs:";
820 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
821 if (PhysRegState[Reg] == regDisabled) continue;
822 dbgs() << " " << TRI->getName(Reg);
823 switch(PhysRegState[Reg]) {
830 dbgs() << '=' << PrintReg(PhysRegState[Reg]);
831 LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]);
832 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
835 assert(I->PhysReg == Reg && "Bad inverse map");
841 // Check that LiveVirtRegs is the inverse.
842 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
843 e = LiveVirtRegs.end(); i != e; ++i) {
844 assert(TargetRegisterInfo::isVirtualRegister(i->VirtReg) &&
846 assert(TargetRegisterInfo::isPhysicalRegister(i->PhysReg) &&
848 assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");
852 // Debug values are not allowed to change codegen in any way.
853 if (MI->isDebugValue()) {
854 bool ScanDbgValue = true;
855 while (ScanDbgValue) {
856 ScanDbgValue = false;
857 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
858 MachineOperand &MO = MI->getOperand(i);
859 if (!MO.isReg()) continue;
860 unsigned Reg = MO.getReg();
861 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
862 LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
863 if (LRI != LiveVirtRegs.end())
864 setPhysReg(MI, i, LRI->PhysReg);
866 int SS = StackSlotForVirtReg[Reg];
868 // We can't allocate a physreg for a DebugValue, sorry!
869 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
873 // Modify DBG_VALUE now that the value is in a spill slot.
874 bool IsIndirect = MI->isIndirectDebugValue();
875 uint64_t Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
876 const MDNode *Var = MI->getDebugVariable();
877 const MDNode *Expr = MI->getDebugExpression();
878 DebugLoc DL = MI->getDebugLoc();
879 MachineBasicBlock *MBB = MI->getParent();
880 MachineInstr *NewDV = BuildMI(*MBB, MBB->erase(MI), DL,
881 TII->get(TargetOpcode::DBG_VALUE))
886 DEBUG(dbgs() << "Modifying debug info due to spill:"
888 // Scan NewDV operands from the beginning.
894 LiveDbgValueMap[Reg].push_back(MI);
901 // If this is a copy, we may be able to coalesce.
902 unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
904 CopyDst = MI->getOperand(0).getReg();
905 CopySrc = MI->getOperand(1).getReg();
906 CopyDstSub = MI->getOperand(0).getSubReg();
907 CopySrcSub = MI->getOperand(1).getSubReg();
910 // Track registers used by instruction.
914 // Mark physreg uses and early clobbers as used.
915 // Find the end of the virtreg operands
916 unsigned VirtOpEnd = 0;
917 bool hasTiedOps = false;
918 bool hasEarlyClobbers = false;
919 bool hasPartialRedefs = false;
920 bool hasPhysDefs = false;
921 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
922 MachineOperand &MO = MI->getOperand(i);
923 // Make sure MRI knows about registers clobbered by regmasks.
924 if (MO.isRegMask()) {
925 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
928 if (!MO.isReg()) continue;
929 unsigned Reg = MO.getReg();
931 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
934 hasTiedOps = hasTiedOps ||
935 MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1;
937 if (MO.isEarlyClobber())
938 hasEarlyClobbers = true;
939 if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
940 hasPartialRedefs = true;
944 if (!MRI->isAllocatable(Reg)) continue;
947 } else if (MO.isEarlyClobber()) {
948 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
949 regFree : regReserved);
950 hasEarlyClobbers = true;
955 // The instruction may have virtual register operands that must be allocated
956 // the same register at use-time and def-time: early clobbers and tied
957 // operands. If there are also physical defs, these registers must avoid
958 // both physical defs and uses, making them more constrained than normal
960 // Similarly, if there are multiple defs and tied operands, we must make
961 // sure the same register is allocated to uses and defs.
962 // We didn't detect inline asm tied operands above, so just make this extra
963 // pass for all inline asm.
964 if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
965 (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) {
966 handleThroughOperands(MI, VirtDead);
967 // Don't attempt coalescing when we have funny stuff going on.
969 // Pretend we have early clobbers so the use operands get marked below.
970 // This is not necessary for the common case of a single tied use.
971 hasEarlyClobbers = true;
975 // Allocate virtreg uses.
976 for (unsigned i = 0; i != VirtOpEnd; ++i) {
977 MachineOperand &MO = MI->getOperand(i);
978 if (!MO.isReg()) continue;
979 unsigned Reg = MO.getReg();
980 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
982 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
983 unsigned PhysReg = LRI->PhysReg;
984 CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
985 if (setPhysReg(MI, i, PhysReg))
990 for (UsedInInstrSet::iterator
991 I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I)
992 MRI->setRegUnitUsed(*I);
994 // Track registers defined by instruction - early clobbers and tied uses at
997 if (hasEarlyClobbers) {
998 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
999 MachineOperand &MO = MI->getOperand(i);
1000 if (!MO.isReg()) continue;
1001 unsigned Reg = MO.getReg();
1002 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1003 // Look for physreg defs and tied uses.
1004 if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue;
1005 markRegUsedInInstr(Reg);
1009 unsigned DefOpEnd = MI->getNumOperands();
1011 // Spill all virtregs before a call. This serves two purposes: 1. If an
1012 // exception is thrown, the landing pad is going to expect to find
1013 // registers in their spill slots, and 2. we don't have to wade through
1014 // all the <imp-def> operands on the call instruction.
1015 DefOpEnd = VirtOpEnd;
1016 DEBUG(dbgs() << " Spilling remaining registers before call.\n");
1019 // The imp-defs are skipped below, but we still need to mark those
1020 // registers as used by the function.
1021 SkippedInstrs.insert(&MCID);
1025 // Allocate defs and collect dead defs.
1026 for (unsigned i = 0; i != DefOpEnd; ++i) {
1027 MachineOperand &MO = MI->getOperand(i);
1028 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
1030 unsigned Reg = MO.getReg();
1032 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1033 if (!MRI->isAllocatable(Reg)) continue;
1034 definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
1037 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
1038 unsigned PhysReg = LRI->PhysReg;
1039 if (setPhysReg(MI, i, PhysReg)) {
1040 VirtDead.push_back(Reg);
1041 CopyDst = 0; // cancel coalescing;
1043 CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
1046 // Kill dead defs after the scan to ensure that multiple defs of the same
1047 // register are allocated identically. We didn't need to do this for uses
1048 // because we are crerating our own kill flags, and they are always at the
1050 for (unsigned i = 0, e = VirtDead.size(); i != e; ++i)
1051 killVirtReg(VirtDead[i]);
1054 for (UsedInInstrSet::iterator
1055 I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I)
1056 MRI->setRegUnitUsed(*I);
1058 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
1059 DEBUG(dbgs() << "-- coalescing: " << *MI);
1060 Coalesced.push_back(MI);
1062 DEBUG(dbgs() << "<< " << *MI);
1066 // Spill all physical registers holding virtual registers now.
1067 DEBUG(dbgs() << "Spilling live registers at end of block.\n");
1068 spillAll(MBB->getFirstTerminator());
1070 // Erase all the coalesced copies. We are delaying it until now because
1071 // LiveVirtRegs might refer to the instrs.
1072 for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
1073 MBB->erase(Coalesced[i]);
1074 NumCopies += Coalesced.size();
1079 /// runOnMachineFunction - Register allocate the whole function
1081 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
1082 DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
1083 << "********** Function: " << Fn.getName() << '\n');
1085 MRI = &MF->getRegInfo();
1086 TRI = MF->getSubtarget().getRegisterInfo();
1087 TII = MF->getSubtarget().getInstrInfo();
1088 MRI->freezeReservedRegs(Fn);
1089 RegClassInfo.runOnMachineFunction(Fn);
1090 UsedInInstr.clear();
1091 UsedInInstr.setUniverse(TRI->getNumRegUnits());
1093 assert(!MRI->isSSA() && "regalloc requires leaving SSA");
1095 // initialize the virtual->physical register map to have a 'null'
1096 // mapping for all virtual registers
1097 StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
1098 LiveVirtRegs.setUniverse(MRI->getNumVirtRegs());
1100 // Loop over all of the basic blocks, eliminating virtual register references
1101 for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
1102 MBBi != MBBe; ++MBBi) {
1104 AllocateBasicBlock();
1107 // Add the clobber lists for all the instructions we skipped earlier.
1108 for (const MCInstrDesc *Desc : SkippedInstrs)
1109 if (const uint16_t *Defs = Desc->getImplicitDefs())
1111 MRI->setPhysRegUsed(*Defs++);
1113 // All machine operands and other references to virtual registers have been
1114 // replaced. Remove the virtual registers.
1115 MRI->clearVirtRegs();
1117 SkippedInstrs.clear();
1118 StackSlotForVirtReg.clear();
1119 LiveDbgValueMap.clear();
1123 FunctionPass *llvm::createFastRegisterAllocator() {
1124 return new RAFast();