1 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/IndexedMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
38 static cl::opt<bool> VerifyFastRegalloc("verify-fast-regalloc", cl::Hidden,
39 cl::desc("Verify machine code before fast regalloc"));
41 STATISTIC(NumStores, "Number of stores added");
42 STATISTIC(NumLoads , "Number of loads added");
43 STATISTIC(NumCopies, "Number of copies coalesced");
45 static RegisterRegAlloc
46 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
49 class RAFast : public MachineFunctionPass {
52 RAFast() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1),
53 isBulkSpilling(false) {}
55 const TargetMachine *TM;
57 MachineRegisterInfo *MRI;
58 const TargetRegisterInfo *TRI;
59 const TargetInstrInfo *TII;
61 // Basic block currently being allocated.
62 MachineBasicBlock *MBB;
64 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
65 // values are spilled.
66 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
68 // Everything we know about a live virtual register.
70 MachineInstr *LastUse; // Last instr to use reg.
71 unsigned PhysReg; // Currently held here.
72 unsigned short LastOpNum; // OpNum on LastUse.
73 bool Dirty; // Register needs spill.
75 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
79 typedef DenseMap<unsigned, LiveReg> LiveRegMap;
80 typedef LiveRegMap::value_type LiveRegEntry;
82 // LiveVirtRegs - This map contains entries for each virtual register
83 // that is currently available in a physical register.
84 LiveRegMap LiveVirtRegs;
86 // RegState - Track the state of a physical register.
88 // A disabled register is not available for allocation, but an alias may
89 // be in use. A register can only be moved out of the disabled state if
90 // all aliases are disabled.
93 // A free register is not currently in use and can be allocated
94 // immediately without checking aliases.
97 // A reserved register has been assigned expolicitly (e.g., setting up a
98 // call parameter), and it remains reserved until it is used.
101 // A register state may also be a virtual register number, indication that
102 // the physical register is currently allocated to a virtual register. In
103 // that case, LiveVirtRegs contains the inverse mapping.
106 // PhysRegState - One of the RegState enums, or a virtreg.
107 std::vector<unsigned> PhysRegState;
109 // UsedInInstr - BitVector of physregs that are used in the current
110 // instruction, and so cannot be allocated.
111 BitVector UsedInInstr;
113 // Allocatable - vector of allocatable physical registers.
114 BitVector Allocatable;
116 // isBulkSpilling - This flag is set when LiveRegMap will be cleared
117 // completely after spilling all live registers. LiveRegMap entries should
124 spillImpossible = ~0u
127 virtual const char *getPassName() const {
128 return "Fast Register Allocator";
131 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
132 AU.setPreservesCFG();
133 AU.addRequiredID(PHIEliminationID);
134 AU.addRequiredID(TwoAddressInstructionPassID);
135 MachineFunctionPass::getAnalysisUsage(AU);
139 bool runOnMachineFunction(MachineFunction &Fn);
140 void AllocateBasicBlock();
141 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
142 bool isLastUseOfLocalReg(MachineOperand&);
144 void addKillFlag(const LiveReg&);
145 void killVirtReg(LiveRegMap::iterator);
146 void killVirtReg(unsigned VirtReg);
147 void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
148 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
150 void usePhysReg(MachineOperand&);
151 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
152 unsigned calcSpillCost(unsigned PhysReg) const;
153 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
154 void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
155 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
156 unsigned VirtReg, unsigned Hint);
157 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
158 unsigned VirtReg, unsigned Hint);
159 void spillAll(MachineInstr *MI);
160 bool setPhysReg(MachineOperand &MO, unsigned PhysReg);
165 /// getStackSpaceFor - This allocates space for the specified virtual register
166 /// to be held on the stack.
167 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
168 // Find the location Reg would belong...
169 int SS = StackSlotForVirtReg[VirtReg];
171 return SS; // Already has space allocated?
173 // Allocate a new stack object for this spill location...
174 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
178 StackSlotForVirtReg[VirtReg] = FrameIdx;
182 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
183 /// its virtual register, and it is guaranteed to be a block-local register.
185 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
186 // Check for non-debug uses or defs following MO.
187 // This is the most likely way to fail - fast path it.
188 MachineOperand *Next = &MO;
189 while ((Next = Next->getNextOperandForReg()))
190 if (!Next->isDebug())
193 // If the register has ever been spilled or reloaded, we conservatively assume
194 // it is a global register used in multiple blocks.
195 if (StackSlotForVirtReg[MO.getReg()] != -1)
198 // Check that the use/def chain has exactly one operand - MO.
199 return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO;
202 /// addKillFlag - Set kill flags on last use of a virtual register.
203 void RAFast::addKillFlag(const LiveReg &LR) {
204 if (!LR.LastUse) return;
205 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
208 else if (!LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum))
212 /// killVirtReg - Mark virtreg as no longer available.
213 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
214 addKillFlag(LRI->second);
215 const LiveReg &LR = LRI->second;
216 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
217 PhysRegState[LR.PhysReg] = regFree;
218 // Erase from LiveVirtRegs unless we're spilling in bulk.
220 LiveVirtRegs.erase(LRI);
223 /// killVirtReg - Mark virtreg as no longer available.
224 void RAFast::killVirtReg(unsigned VirtReg) {
225 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
226 "killVirtReg needs a virtual register");
227 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
228 if (LRI != LiveVirtRegs.end())
232 /// spillVirtReg - This method spills the value specified by VirtReg into the
233 /// corresponding stack slot if needed. If isKill is set, the register is also
235 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
236 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
237 "Spilling a physical register is illegal!");
238 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
239 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
240 spillVirtReg(MI, LRI);
243 /// spillVirtReg - Do the actual work of spilling.
244 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
245 LiveRegMap::iterator LRI) {
246 LiveReg &LR = LRI->second;
247 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
250 // If this physreg is used by the instruction, we want to kill it on the
251 // instruction, not on the spill.
252 bool SpillKill = LR.LastUse != MI;
254 DEBUG(dbgs() << "Spilling %reg" << LRI->first
255 << " in " << TRI->getName(LR.PhysReg));
256 const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
257 int FI = getStackSpaceFor(LRI->first, RC);
258 DEBUG(dbgs() << " to stack slot #" << FI << "\n");
259 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
260 ++NumStores; // Update statistics
263 LR.LastUse = 0; // Don't kill register again
268 /// spillAll - Spill all dirty virtregs without killing them.
269 void RAFast::spillAll(MachineInstr *MI) {
270 if (LiveVirtRegs.empty()) return;
271 isBulkSpilling = true;
272 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
273 e = LiveVirtRegs.end(); i != e; ++i)
275 LiveVirtRegs.clear();
276 isBulkSpilling = false;
279 /// usePhysReg - Handle the direct use of a physical register.
280 /// Check that the register is not used by a virtreg.
281 /// Kill the physreg, marking it free.
282 /// This may add implicit kills to MO->getParent() and invalidate MO.
283 void RAFast::usePhysReg(MachineOperand &MO) {
284 unsigned PhysReg = MO.getReg();
285 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
286 "Bad usePhysReg operand");
288 switch (PhysRegState[PhysReg]) {
292 PhysRegState[PhysReg] = regFree;
295 UsedInInstr.set(PhysReg);
299 // The physreg was allocated to a virtual register. That means to value we
300 // wanted has been clobbered.
301 llvm_unreachable("Instruction uses an allocated register");
304 // Maybe a superregister is reserved?
305 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
306 unsigned Alias = *AS; ++AS) {
307 switch (PhysRegState[Alias]) {
311 assert(TRI->isSuperRegister(PhysReg, Alias) &&
312 "Instruction is not using a subregister of a reserved register");
313 // Leave the superregister in the working set.
314 PhysRegState[Alias] = regFree;
315 UsedInInstr.set(Alias);
316 MO.getParent()->addRegisterKilled(Alias, TRI, true);
319 if (TRI->isSuperRegister(PhysReg, Alias)) {
320 // Leave the superregister in the working set.
321 UsedInInstr.set(Alias);
322 MO.getParent()->addRegisterKilled(Alias, TRI, true);
325 // Some other alias was in the working set - clear it.
326 PhysRegState[Alias] = regDisabled;
329 llvm_unreachable("Instruction uses an alias of an allocated register");
333 // All aliases are disabled, bring register into working set.
334 PhysRegState[PhysReg] = regFree;
335 UsedInInstr.set(PhysReg);
339 /// definePhysReg - Mark PhysReg as reserved or free after spilling any
340 /// virtregs. This is very similar to defineVirtReg except the physreg is
341 /// reserved instead of allocated.
342 void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
344 UsedInInstr.set(PhysReg);
345 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
349 spillVirtReg(MI, VirtReg);
353 PhysRegState[PhysReg] = NewState;
357 // This is a disabled register, disable all aliases.
358 PhysRegState[PhysReg] = NewState;
359 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
360 unsigned Alias = *AS; ++AS) {
361 UsedInInstr.set(Alias);
362 switch (unsigned VirtReg = PhysRegState[Alias]) {
366 spillVirtReg(MI, VirtReg);
370 PhysRegState[Alias] = regDisabled;
371 if (TRI->isSuperRegister(PhysReg, Alias))
379 // calcSpillCost - Return the cost of spilling clearing out PhysReg and
380 // aliases so it is free for allocation.
381 // Returns 0 when PhysReg is free or disabled with all aliases disabled - it
382 // can be allocated directly.
383 // Returns spillImpossible when PhysReg or an alias can't be spilled.
384 unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
385 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
391 return spillImpossible;
393 return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
396 // This is a disabled register, add up const of aliases.
398 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
399 unsigned Alias = *AS; ++AS) {
400 switch (unsigned VirtReg = PhysRegState[Alias]) {
407 return spillImpossible;
409 Cost += LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
417 /// assignVirtToPhysReg - This method updates local state so that we know
418 /// that PhysReg is the proper container for VirtReg now. The physical
419 /// register must not be used for anything else when this is called.
421 void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) {
422 DEBUG(dbgs() << "Assigning %reg" << LRE.first << " to "
423 << TRI->getName(PhysReg) << "\n");
424 PhysRegState[PhysReg] = LRE.first;
425 assert(!LRE.second.PhysReg && "Already assigned a physreg");
426 LRE.second.PhysReg = PhysReg;
429 /// allocVirtReg - Allocate a physical register for VirtReg.
430 void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
431 const unsigned VirtReg = LRE.first;
433 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
434 "Can only allocate virtual registers");
436 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
438 // Ignore invalid hints.
439 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
440 !RC->contains(Hint) || UsedInInstr.test(Hint) ||
441 !Allocatable.test(Hint)))
444 // Take hint when possible.
446 assert(RC->contains(Hint) && !UsedInInstr.test(Hint) &&
447 Allocatable.test(Hint) && "Invalid hint should have been cleared");
448 switch(calcSpillCost(Hint)) {
450 definePhysReg(MI, Hint, regFree);
453 return assignVirtToPhysReg(LRE, Hint);
454 case spillImpossible:
459 TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
460 TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
462 // First try to find a completely free register.
463 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
464 unsigned PhysReg = *I;
465 if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg))
466 return assignVirtToPhysReg(LRE, PhysReg);
469 DEBUG(dbgs() << "Allocating %reg" << VirtReg << " from " << RC->getName()
472 unsigned BestReg = 0, BestCost = spillImpossible;
473 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
474 unsigned Cost = calcSpillCost(*I);
475 // Cost is 0 when all aliases are already disabled.
477 return assignVirtToPhysReg(LRE, *I);
479 BestReg = *I, BestCost = Cost;
483 definePhysReg(MI, BestReg, regFree);
484 return assignVirtToPhysReg(LRE, BestReg);
487 // Nothing we can do.
489 raw_string_ostream Msg(msg);
490 Msg << "Ran out of registers during register allocation!";
491 if (MI->isInlineAsm()) {
492 Msg << "\nPlease check your inline asm statement for "
493 << "invalid constraints:\n";
496 report_fatal_error(Msg.str());
499 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
500 RAFast::LiveRegMap::iterator
501 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
502 unsigned VirtReg, unsigned Hint) {
503 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
504 "Not a virtual register");
505 LiveRegMap::iterator LRI;
507 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
508 LiveReg &LR = LRI->second;
510 // If there is no hint, peek at the only use of this register.
511 if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
512 MRI->hasOneNonDBGUse(VirtReg)) {
513 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
514 // It's a copy, use the destination register as a hint.
515 if (TII->isMoveInstr(*MRI->use_nodbg_begin(VirtReg),
516 SrcReg, DstReg, SrcSubReg, DstSubReg))
519 allocVirtReg(MI, *LRI, Hint);
521 addKillFlag(LR); // Kill before redefine.
522 assert(LR.PhysReg && "Register not assigned");
524 LR.LastOpNum = OpNum;
526 UsedInInstr.set(LR.PhysReg);
530 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
531 RAFast::LiveRegMap::iterator
532 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
533 unsigned VirtReg, unsigned Hint) {
534 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
535 "Not a virtual register");
536 LiveRegMap::iterator LRI;
538 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
539 LiveReg &LR = LRI->second;
540 MachineOperand &MO = MI->getOperand(OpNum);
542 allocVirtReg(MI, *LRI, Hint);
543 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
544 int FrameIndex = getStackSpaceFor(VirtReg, RC);
545 DEBUG(dbgs() << "Reloading %reg" << VirtReg << " into "
546 << TRI->getName(LR.PhysReg) << "\n");
547 TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI);
549 } else if (LR.Dirty) {
550 if (isLastUseOfLocalReg(MO)) {
551 DEBUG(dbgs() << "Killing last use: " << MO << "\n");
553 } else if (MO.isKill()) {
554 DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
557 } else if (MO.isKill()) {
558 // We must remove kill flags from uses of reloaded registers because the
559 // register would be killed immediately, and there might be a second use:
560 // %foo = OR %x<kill>, %x
561 // This would cause a second reload of %x into a different register.
562 DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
565 assert(LR.PhysReg && "Register not assigned");
567 LR.LastOpNum = OpNum;
568 UsedInInstr.set(LR.PhysReg);
572 // setPhysReg - Change MO the refer the PhysReg, considering subregs.
573 // This may invalidate MO if it is necessary to add implicit kills for a
575 // Return tru if MO kills its register.
576 bool RAFast::setPhysReg(MachineOperand &MO, unsigned PhysReg) {
577 if (!MO.getSubReg()) {
579 return MO.isKill() || MO.isDead();
582 // Handle subregister index.
583 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
587 MO.getParent()->addRegisterKilled(PhysReg, TRI, true);
592 // A subregister def implicitly defines the whole physreg.
594 MO.getParent()->addRegisterDead(PhysReg, TRI, true);
597 MO.getParent()->addRegisterDefined(PhysReg, TRI);
601 void RAFast::AllocateBasicBlock() {
602 DEBUG(dbgs() << "\nAllocating " << *MBB);
604 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
605 assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
607 MachineBasicBlock::iterator MII = MBB->begin();
609 // Add live-in registers as live.
610 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
611 E = MBB->livein_end(); I != E; ++I)
612 definePhysReg(MII, *I, regReserved);
614 SmallVector<unsigned, 8> PhysECs;
615 SmallVector<MachineInstr*, 32> Coalesced;
617 // Otherwise, sequentially allocate each instruction in the MBB.
618 while (MII != MBB->end()) {
619 MachineInstr *MI = MII++;
620 const TargetInstrDesc &TID = MI->getDesc();
622 dbgs() << "\n>> " << *MI << "Regs:";
623 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
624 if (PhysRegState[Reg] == regDisabled) continue;
625 dbgs() << " " << TRI->getName(Reg);
626 switch(PhysRegState[Reg]) {
633 dbgs() << "=%reg" << PhysRegState[Reg];
634 if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
636 assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
642 // Check that LiveVirtRegs is the inverse.
643 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
644 e = LiveVirtRegs.end(); i != e; ++i) {
645 assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
647 assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
649 assert(PhysRegState[i->second.PhysReg] == i->first &&
654 // Debug values are not allowed to change codegen in any way.
655 if (MI->isDebugValue()) {
656 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
657 MachineOperand &MO = MI->getOperand(i);
658 if (!MO.isReg()) continue;
659 unsigned Reg = MO.getReg();
660 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
661 LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
662 if (LRI != LiveVirtRegs.end())
663 setPhysReg(MO, LRI->second.PhysReg);
665 MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
671 // If this is a copy, we may be able to coalesce.
672 unsigned CopySrc, CopyDst, CopySrcSub, CopyDstSub;
673 if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
674 CopySrc = CopyDst = 0;
676 // Track registers used by instruction.
681 // Mark physreg uses and early clobbers as used.
682 // Find the end of the virtreg operands
683 unsigned VirtOpEnd = 0;
684 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
685 MachineOperand &MO = MI->getOperand(i);
686 if (!MO.isReg()) continue;
687 unsigned Reg = MO.getReg();
689 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
693 if (!Allocatable.test(Reg)) continue;
696 } else if (MO.isEarlyClobber()) {
697 definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
698 PhysECs.push_back(Reg);
703 // Allocate virtreg uses and early clobbers.
705 for (unsigned i = 0; i != VirtOpEnd; ++i) {
706 MachineOperand &MO = MI->getOperand(i);
707 if (!MO.isReg()) continue;
708 unsigned Reg = MO.getReg();
709 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
711 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
712 unsigned PhysReg = LRI->second.PhysReg;
713 CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
714 if (setPhysReg(MO, PhysReg))
716 } else if (MO.isEarlyClobber()) {
717 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
718 unsigned PhysReg = LRI->second.PhysReg;
719 setPhysReg(MO, PhysReg);
720 PhysECs.push_back(PhysReg);
724 MRI->addPhysRegsUsed(UsedInInstr);
726 // Track registers defined by instruction - early clobbers at this point.
728 for (unsigned i = 0, e = PhysECs.size(); i != e; ++i) {
729 unsigned PhysReg = PhysECs[i];
730 UsedInInstr.set(PhysReg);
731 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
732 unsigned Alias = *AS; ++AS)
733 UsedInInstr.set(Alias);
736 unsigned DefOpEnd = MI->getNumOperands();
738 // Spill all virtregs before a call. This serves two purposes: 1. If an
739 // exception is thrown, the landing pad is going to expect to find registers
740 // in their spill slots, and 2. we don't have to wade through all the
741 // <imp-def> operands on the call instruction.
742 DefOpEnd = VirtOpEnd;
743 DEBUG(dbgs() << " Spilling remaining registers before call.\n");
748 // Allocate defs and collect dead defs.
749 for (unsigned i = 0; i != DefOpEnd; ++i) {
750 MachineOperand &MO = MI->getOperand(i);
751 if (!MO.isReg() || !MO.isDef() || !MO.getReg()) continue;
752 unsigned Reg = MO.getReg();
754 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
755 if (!Allocatable.test(Reg)) continue;
756 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
757 regFree : regReserved);
760 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
761 unsigned PhysReg = LRI->second.PhysReg;
762 if (setPhysReg(MO, PhysReg)) {
764 CopyDst = 0; // cancel coalescing;
766 CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
769 MRI->addPhysRegsUsed(UsedInInstr);
771 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
772 DEBUG(dbgs() << "-- coalescing: " << *MI);
773 Coalesced.push_back(MI);
775 DEBUG(dbgs() << "<< " << *MI);
779 // Spill all physical registers holding virtual registers now.
780 DEBUG(dbgs() << "Spilling live registers at end of block.\n");
781 spillAll(MBB->getFirstTerminator());
783 // Erase all the coalesced copies. We are delaying it until now because
784 // LiveVirtRegs might refer to the instrs.
785 for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
786 MBB->erase(Coalesced[i]);
787 NumCopies += Coalesced.size();
792 /// runOnMachineFunction - Register allocate the whole function
794 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
795 DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
796 << "********** Function: "
797 << ((Value*)Fn.getFunction())->getName() << '\n');
798 if (VerifyFastRegalloc)
799 Fn.verify(this, true);
801 MRI = &MF->getRegInfo();
802 TM = &Fn.getTarget();
803 TRI = TM->getRegisterInfo();
804 TII = TM->getInstrInfo();
806 UsedInInstr.resize(TRI->getNumRegs());
807 Allocatable = TRI->getAllocatableSet(*MF);
809 // initialize the virtual->physical register map to have a 'null'
810 // mapping for all virtual registers
811 unsigned LastVirtReg = MRI->getLastVirtReg();
812 StackSlotForVirtReg.grow(LastVirtReg);
814 // Loop over all of the basic blocks, eliminating virtual register references
815 for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
816 MBBi != MBBe; ++MBBi) {
818 AllocateBasicBlock();
821 // Make sure the set of used physregs is closed under subreg operations.
822 MRI->closePhysRegsUsed(*TRI);
824 StackSlotForVirtReg.clear();
828 FunctionPass *llvm::createFastRegisterAllocator() {